Re: [PATCH/RFC] spi: core: Fix logic mismatch in spi_master.set_cs()

[Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>]

[-- Attachment #1: Type: text/plain, Size: 1020 bytes --]

On Tue, Jan 14, 2014 at 02:23:37PM +0100, Geert Uytterhoeven wrote:
> On Tue, Jan 14, 2014 at 1:52 PM, Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> >On Tue, Jan 14, 2014 at 12:36:51PM +0100, Geert Uytterhoeven wrote:

> > This also pushes the handling of CS_HIGH back out into the driver which
> > doesn't seem like it's helping anything.  Flipping the sense of enable

> It depends: on hardware with separate register bits for chip select polarity
> and chip select assertion it avoids having to invert the enable value a second
> time.

If we're manually setting /CS it really makes no difference what the
chip thinks the polarity is - something that is controlling /CS
autonomously can't implement this operation and something that can just
set it at any time doesn't need to worry if the chip thinks it's
asserted or not.

> > when calling set_cs() is probably OK though.

> Just flipping the sense of enable still needs a documentation update.

Huh?  Why were you updating the code then...

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]