From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>
Cc: "Usyskin, Alexander" <alexander.usyskin@intel.com>,
"Winkler, Tomas" <tomas.winkler@intel.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
"Lubart, Vitaly" <vitaly.lubart@intel.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>
Subject: Re: [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
Date: Wed, 27 Sep 2023 16:54:38 +0200 [thread overview]
Message-ID: <20230927165350.470bea0f@xps-13> (raw)
In-Reply-To: <ZRQ+LzIoD+J0BzVp@finisterre.sirena.org.uk>
Hi Mark,
broonie@kernel.org wrote on Wed, 27 Sep 2023 16:37:35 +0200:
> On Wed, Sep 27, 2023 at 02:11:47PM +0000, Usyskin, Alexander wrote:
>
> > There is a Discreet Graphic device with embedded SPI (controller & flash).
> > The embedded SPI is not visible to OS.
> > There is another HW in the chip that gates access to the controller and
> > exposes registers for:
> > region select; read and write (4 and 8 bytes); erase (4K); error register;
>
> So assuming that's flash region select it sounds like this is a MTD
> controller and the fact that there's SPI isn't really relevant at all
> from a programming model point of view and it should probably be
> described as a MTD controller of some kind. Does that sound about
> right?
Yeah in this case it seems the best option if the OS only has access to
a very small subset of what the spi controller can do.
Thanks,
Miquèl
next prev parent reply other threads:[~2023-09-27 14:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230910123949.1251964-1-alexander.usyskin@intel.com>
2023-09-11 7:42 ` [PATCH 00/10] drm/i915/spi: spi access for discrete graphics Miquel Raynal
2023-09-12 10:50 ` Usyskin, Alexander
2023-09-12 12:14 ` Mark Brown
2023-09-12 13:15 ` Usyskin, Alexander
2023-09-12 13:21 ` Miquel Raynal
2023-09-12 13:36 ` Mark Brown
2023-09-20 13:52 ` Usyskin, Alexander
2023-09-20 15:54 ` Mark Brown
2023-09-20 21:00 ` Winkler, Tomas
2023-09-21 11:29 ` Mark Brown
2023-09-27 14:11 ` Usyskin, Alexander
2023-09-27 14:37 ` Mark Brown
2023-09-27 14:54 ` Miquel Raynal [this message]
2023-09-28 6:33 ` Usyskin, Alexander
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