From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Mark Brown <broonie@kernel.org>
Cc: Sudip Mukherjee <sudip.mukherjee@sifive.com>,
Serge Semin <fancer.lancer@gmail.com>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v1 06/11] spi: dw: send cmd and addr to start the spi transfer
Date: Wed, 8 Jul 2026 22:51:59 -0700 [thread overview]
Message-ID: <20260709055204.138168-7-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260709055204.138168-1-changhuang.liang@starfivetech.com>
From: Sudip Mukherjee <sudip.mukherjee@sifive.com>
In enhanced spi mode, read or write will start by sending the cmd
and address (if present).
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
Co-developed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/spi/spi-dw-core.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 9f3ee1d78c05..9f0f7e0b93a1 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -836,6 +836,19 @@ static void dw_spi_init_enh_mem_buf(struct dw_spi *dws, const struct spi_mem_op
}
}
+static void dw_spi_enh_write_cmd_addr(struct dw_spi *dws, const struct spi_mem_op *op)
+{
+ /* Send cmd as 32 bit value */
+ dw_write_io_reg(dws, DW_SPI_DR, op->cmd.opcode);
+ if (op->addr.nbytes) {
+ dw_write_io_reg(dws, DW_SPI_DR, lower_32_bits(op->addr.val));
+ if (op->addr.nbytes > 4) {
+ /* address more than 32bit */
+ dw_write_io_reg(dws, DW_SPI_DR, upper_32_bits(op->addr.val));
+ }
+ }
+}
+
static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct spi_controller *ctlr = mem->spi->controller;
@@ -895,6 +908,8 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op *
dw_spi_enable_chip(dws, 1);
+ dw_spi_enh_write_cmd_addr(dws, op);
+
return 0;
}
--
2.25.1
next prev parent reply other threads:[~2026-07-09 6:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-09 5:51 [PATCH v1 00/11] Add support for StarFive JHB100 SFC Changhuang Liang
2026-07-09 5:51 ` [PATCH v1 01/11] spi: dw: Introduce spi_frf and STD_SPI Changhuang Liang
2026-07-09 5:51 ` [PATCH v1 02/11] spi: dw: update NDF while using enhanced spi mode Changhuang Liang
2026-07-09 5:51 ` [PATCH v1 03/11] spi: dw: update SPI_CTRLR0 register Changhuang Liang
2026-07-09 5:51 ` [PATCH v1 04/11] spi: dw: add check for support of enhanced spi Changhuang Liang
2026-07-09 5:51 ` [PATCH v1 05/11] spi: dw: Introduce enhanced single/dual/quad/octal spi Changhuang Liang
2026-07-09 5:51 ` Changhuang Liang [this message]
2026-07-09 5:52 ` [PATCH v1 07/11] spi: dw: use irq handler for enhanced spi Changhuang Liang
2026-07-09 5:52 ` [PATCH v1 08/11] spi: dw: adjust size of mem_op Changhuang Liang
2026-07-09 5:52 ` [PATCH v1 09/11] spi: dw: detect enhanced spi mode Changhuang Liang
2026-07-09 5:52 ` [PATCH v1 10/11] spi: dt-bindings: snps,dw-apb-ssi: Add starfive,jhb100-sfc Changhuang Liang
2026-07-09 17:55 ` Conor Dooley
2026-07-09 5:52 ` [PATCH v1 11/11] spi: dw: Add support for StarFive JHB100 SoC SFC Changhuang Liang
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