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From: Mukesh Savaliya <mukesh.savaliya@oss.qualcomm.com>
To: Praveen Talari <praveen.talari@oss.qualcomm.com>,
	konrad.dybcio@oss.qualcomm.com,
	Sudeep Holla <sudeep.holla@kernel.org>,
	Cristian Marussi <cristian.marussi@arm.com>,
	Ulf Hansson <ulfh@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Mark Brown <broonie@kernel.org>,
	Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>,
	Andi Shyti <andi.shyti@kernel.org>
Cc: chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-serial@vger.kernel.org, linux-spi@vger.kernel.org,
	linux-i2c@vger.kernel.org
Subject: Re: [PATCH 7/7] i2c: qcom-geni: Use geni_se_set_rate() for setting source clock frequency
Date: Mon, 24 Aug 2026 19:11:51 +0530	[thread overview]
Message-ID: <8af7a34a-da4f-492f-a51c-cc420edc5e6e@oss.qualcomm.com> (raw)
In-Reply-To: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-7-61171ab1cdce@oss.qualcomm.com>



On 8/5/2026 1:27 AM, Praveen Talari wrote:
> On the SA8255P platform there is no Linux clock handler for the SE source
> clock; resources are instead managed by firmware via a genpd performance
> domain. The I2C driver therefore relies on geni_se_set_rate() to apply the
> fixed 19.2 MHz source clock frequency expected by the SCL divider and

somewhere it's 32 MHz also and this may change too ?

> counter values programmed by qcom_geni_i2c_conf().
> 
> Call geni_se_set_rate() directly from qcom_geni_i2c_conf() so the
> configured frequency is applied to the correct device (the perf domain
> device on the firmware-managed path, or se->dev otherwise) without the I2C
> driver needing to know which resources_init() variant is in use.
> 
> Drop the now-unused set_rate field from struct geni_i2c_desc, the
> geni_se_set_perf_opp() usage on the SA8255P variant, and the unused freq
> parameter from qcom_geni_i2c_conf().
> 
> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
> ---
>   drivers/i2c/busses/i2c-qcom-geni.c | 13 +++++++------
>   1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
> index a23554d101fd..4561e2d235d5 100644
> --- a/drivers/i2c/busses/i2c-qcom-geni.c
> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> @@ -213,11 +213,11 @@ static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
>   	return -EINVAL;
>   }
>   
> -static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq)
> +static int qcom_geni_i2c_conf(struct geni_se *se)
>   {
>   	struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev);
>   	const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
> -	u32 val;
> +	u32 val, ret;
>   
>   	writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
>   
> @@ -233,6 +233,10 @@ static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq)
>   				 itr->clk_div, itr->t_high_cnt,
>   				 itr->t_low_cnt, itr->t_cycle_cnt);
>   
> +	ret = geni_se_set_rate(&gi2c->se, 19200000);

hard code ?
May work currently, but if higher frequency support added, source may 
change.

Also you have added in commit message, but add a comment also here.

> +	if (ret)
> +		return ret;
> +
>   	return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW,
>   				  Bps_to_icc(gi2c->clk_freq_out));
>   }

[...]


  reply	other threads:[~2026-08-24 13:42 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-04 19:57 [PATCH 0/7] soc: qcom: geni: Derive SE clock configuration from OPP table on SA8255P Praveen Talari
2026-08-04 19:57 ` [PATCH 1/7] pmdomain: arm: Fix -EINVAL from scmi_pd_set_perf_state() on state 0 Praveen Talari
2026-08-10 14:19   ` Ulf Hansson
2026-08-12  6:58   ` Mukesh Savaliya
2026-08-12  7:24   ` Mukesh Savaliya
2026-08-12  8:57     ` Ulf Hansson
2026-08-12  9:13       ` Mukesh Savaliya
2026-08-25  8:22   ` Abel Vesa
2026-08-04 19:57 ` [PATCH 2/7] soc: qcom: geni-se: Populate clk_perf_tbl with SE source clock frequencies from perf OPP table Praveen Talari
2026-08-12  7:36   ` Mukesh Savaliya
2026-08-24 14:56   ` Konrad Dybcio
2026-08-24 16:55     ` Praveen Talari
2026-08-26 15:17     ` Praveen Talari
2026-08-04 19:57 ` [PATCH 3/7] soc: qcom: geni-se: Add helper to set SE clock rate via OPP Praveen Talari
2026-08-12  8:55   ` Mukesh Savaliya
2026-08-24 11:07   ` Mukesh Savaliya
2026-08-24 14:58   ` Konrad Dybcio
2026-08-24 17:00     ` Praveen Talari
2026-08-04 19:57 ` [PATCH 4/7] serial: qcom-geni: Use geni_se_set_rate() for source clock configuration Praveen Talari
2026-08-24 11:39   ` Mukesh Savaliya
2026-08-24 11:40   ` Mukesh Savaliya
2026-08-24 15:05   ` Konrad Dybcio
2026-08-25  4:00     ` Praveen Talari
2026-08-25  8:28       ` Konrad Dybcio
2026-08-04 19:57 ` [PATCH 5/7] spi: qcom-geni: Use geni_se_set_rate() for setting source clock frequency Praveen Talari
2026-08-04 20:03   ` Mark Brown
2026-08-24 11:52   ` Mukesh Savaliya
2026-08-04 19:57 ` [PATCH 6/7] i2c: qcom-geni: Use common GENI resource initialization helper Praveen Talari
2026-08-24 13:12   ` Mukesh Savaliya
2026-08-25 13:34     ` Praveen Talari
2026-08-04 19:57 ` [PATCH 7/7] i2c: qcom-geni: Use geni_se_set_rate() for setting source clock frequency Praveen Talari
2026-08-24 13:41   ` Mukesh Savaliya [this message]
2026-08-25 18:03     ` Praveen Talari
     [not found]     ` <e000c3da-32f5-49ba-9aff-b2b17db23927@oss.qualcomm.com>
2026-08-26 11:54       ` Mukesh Savaliya
2026-08-24 15:06   ` Konrad Dybcio
2026-08-25  8:19     ` Praveen Talari

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