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* [PATCH] spi: intel: Fix the offset to get the 64K erase opcode
@ 2022-10-12 15:21 Mauro Lima
  2022-10-13  8:41 ` Mika Westerberg
  2022-10-13 13:41 ` Mark Brown
  0 siblings, 2 replies; 3+ messages in thread
From: Mauro Lima @ 2022-10-12 15:21 UTC (permalink / raw)
  To: broonie; +Cc: mika.westerberg, linux-spi, linux-kernel, Mauro Lima

According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.

Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com>
---
 drivers/spi/spi-intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c
index 55f4ee2db002..605acb1bf4b0 100644
--- a/drivers/spi/spi-intel.c
+++ b/drivers/spi/spi-intel.c
@@ -114,7 +114,7 @@
 #define ERASE_OPCODE_SHIFT		8
 #define ERASE_OPCODE_MASK		(0xff << ERASE_OPCODE_SHIFT)
 #define ERASE_64K_OPCODE_SHIFT		16
-#define ERASE_64K_OPCODE_MASK		(0xff << ERASE_OPCODE_SHIFT)
+#define ERASE_64K_OPCODE_MASK		(0xff << ERASE_64K_OPCODE_SHIFT)
 
 /* Flash descriptor fields */
 #define FLVALSIG_MAGIC			0x0ff0a55a
-- 
2.34.3


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Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2022-10-12 15:21 [PATCH] spi: intel: Fix the offset to get the 64K erase opcode Mauro Lima
2022-10-13  8:41 ` Mika Westerberg
2022-10-13 13:41 ` Mark Brown

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