Re: [PATCH] staging: axis-fifo: remove driver

[Ovidiu Panait <ovidiu.panait.oss@gmail.com>]

Hi,

On 6/2/26 4:11 PM, Dan Carpenter wrote:
> On Tue, Jun 02, 2026 at 06:31:27PM +0530, Grewstad wrote:
>> On Tue, Jun 2, 2026 at 5:07 PM Dan Carpenter <error27@gmail.com> wrote:
>>>
>>> On Tue, Jun 02, 2026 at 04:01:53PM +0530, Arihan Bhor wrote:
>>>
>>> I don't think we should delete this driver.  From reading the git
>>> log, Ovidiu Panait was obviously using this code last year.  Let's
>>> also add Jacob Feder, although he hasn't touched the code in 8 years,
>>> he still might know if there are other users.
>>
>> I could not find any user-space applications that depend on this driver.
>>
>> https://lore.kernel.org/lkml/CAD03fjb=_kW9=q9YV4qnQ5GD=HMB5Bx7pf3+AFcgDR2gVc1V6Q@mail.gmail.com/
>> I was looking for any users of this driver on the linux-kernel, linux-staging,
>> and linux-arm-kernel mailing lists as well as Jacob Feder, and received no
>> replies since I posted it 1 day ago. If someone is using it or maintaining a
>> proprietary app, they will complain and we can bring the driver back.
> 
> Here are people using it and running into issues in Jan 2025.
> https://adaptivesupport.amd.com/s/question/0D54U00008zRBdISAW/vitis-is-not-creating-a-driver-entry-for-axififomm-43?language=zh_CN
> Someone provides a work around:
> https://adaptivesupport.amd.com/s/question/0D54U00008sLBuMSAW/how-to-use-the-axi-stream-fifo-drivers-xllfifoh-xllfifogc-etc-in-the-project?language=en_US
> Then Ovidiu Panait fixed the bug in Sep by adding the correct
> compatible.
> 

I was using this driver to play around with an FPGA board I have (Arty
Z7-20), so not for commercial purposes. This IP provides a convenient
way to move data to/from a custom IP in the FPGA. I am using it mostly
for testing.

I think there are no in-tree users mainly because the IP it talks to
lives in the FPGA fabric, and drivers for custom FPGA IP blocks
generally don't get upstreamed.

However, there is the problem of what subsystem this belongs to. It was
suggested to be turned into a DMA controller to get it moved out of staging:
https://lore.kernel.org/all/20260227-unboxed-customary-7ce6eda1858c@spud/

But I am not sure that this fits as a DMA controller, as it has no DMA
capabilities. The CPU moves every word individually to and from a register.

My understanding is that the real Xilinx dmaengine IP is
drivers/dma/xilinx/xilinx_dma.c and this IP is just a simpler, register
based alternative to move data between the CPU and the FPGA fabric.

Ovidiu

> regards,
> dan carpenter