From: Andre Przywara <andre.przywara@arm.com>
To: Jagan Teki <jagan@amarulasolutions.com>
Cc: Icenowy Zheng <uwu@icenowy.me>,
Jesse Taube <mr.bossman075@gmail.com>, Yifan Gu <me@yifangu.com>,
Giulio Benetti <giulio.benetti@benettiengineering.com>,
George Hilliard <thirtythreeforty@gmail.com>,
Samuel Holland <samuel@sholland.org>,
u-boot@lists.denx.de, linux-sunxi@lists.linux.dev
Subject: [PATCH 6/6] sunxi: add CherryPi-F1C200s support
Date: Wed, 12 Oct 2022 17:34:58 +0100 [thread overview]
Message-ID: <20221012163458.1968900-7-andre.przywara@arm.com> (raw)
In-Reply-To: <20221012163458.1968900-1-andre.przywara@arm.com>
The CherryPi F1C200s board is a small development board, featuring the
F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets,
of which one is connected to a USB-UART chip, that provides easy access
to UART1.
Beside the usual micro-SD card slot, the board comes with a SPI NAND
flash chip, which is not yet supported.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++++
configs/cherrypi_f1c200s_defconfig | 11 +++++
2 files changed, 56 insertions(+)
create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
new file mode 100644
index 00000000000..f0ebcb6d893
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2022 Arm Ltd.
+ * based on another DT, which is:
+ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+/ {
+ model = "Cherry Pi F1C200s";
+ compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart1;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pa_pins>;
+ status = "okay";
+};
diff --git a/configs/cherrypi_f1c200s_defconfig b/configs/cherrypi_f1c200s_defconfig
new file mode 100644
index 00000000000..306d363f485
--- /dev/null
+++ b/configs/cherrypi_f1c200s_defconfig
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s"
+CONFIG_SPL=y
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
+CONFIG_SUNXI_MINIMUM_DRAM_MB=64
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_CONS_INDEX=2
--
2.25.1
next prev parent reply other threads:[~2022-10-12 16:35 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-12 16:34 [PATCH 0/6] sunxi: improve F1C200s support Andre Przywara
2022-10-12 16:34 ` [PATCH 1/6] sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MB Andre Przywara
2022-10-12 21:33 ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 2/6] sunxi: fix 32MB load address layout Andre Przywara
2022-10-12 21:37 ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 3/6] sunxi: f1c100: move SKIP_LOWLEVEL_INIT_ONLY into Kconfig Andre Przywara
2022-10-12 21:38 ` Jernej Škrabec
2022-10-13 8:51 ` Icenowy Zheng
2022-10-12 16:34 ` [PATCH 4/6] sunxi: f1c100: add UART1 support Andre Przywara
2022-10-12 21:42 ` Jernej Škrabec
2022-10-18 9:23 ` Andre Przywara
2022-10-19 3:55 ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 5/6] sunxi: f1c100: dtsi: add UART1 pins Andre Przywara
2022-10-12 21:43 ` Jernej Škrabec
2022-10-12 16:34 ` Andre Przywara [this message]
2022-10-13 8:33 ` [PATCH 6/6] sunxi: add CherryPi-F1C200s support Clément Péron
2022-10-13 9:53 ` Andre Przywara
2022-10-14 5:04 ` Jesse Taube
2022-10-18 14:01 ` Andre Przywara
2022-10-20 15:52 ` Giulio Benetti
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