ARM Sunxi Platform Development
 help / color / mirror / Atom feed
From: Andre Przywara <andre.przywara@arm.com>
To: "Jernej Škrabec" <jernej.skrabec@gmail.com>,
	"Jagan Teki" <jagan@amarulasolutions.com>
Cc: Icenowy Zheng <uwu@icenowy.me>,
	Jesse Taube <mr.bossman075@gmail.com>, Yifan Gu <me@yifangu.com>,
	Giulio Benetti <giulio.benetti@benettiengineering.com>,
	George Hilliard <thirtythreeforty@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	u-boot@lists.denx.de, linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 4/6] sunxi: f1c100: add UART1 support
Date: Tue, 18 Oct 2022 10:23:41 +0100	[thread overview]
Message-ID: <905be4d0-74c3-c563-00e8-fcd039694cb7@arm.com> (raw)
In-Reply-To: <1917971.yKVeVyVuyW@kista>

On 12/10/2022 22:42, Jernej Škrabec wrote:

Hi Jernej,

many thanks for the review of this series, that's much appreciated!

> Dne sreda, 12. oktober 2022 ob 18:34:56 CEST je Andre Przywara napisal(a):
>> Some boards use UART1 for its debug UART, so define the pins for the SPL
>> and the pinmux name and mux value for U-Boot proper.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>>   arch/arm/mach-sunxi/board.c           | 4 ++++
>>   drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 +
>>   2 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
>> index 62bb40b8c89..77216157908 100644
>> --- a/arch/arm/mach-sunxi/board.c
>> +++ b/arch/arm/mach-sunxi/board.c
>> @@ -147,6 +147,10 @@ static int gpio_init(void)
>>   	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
>>   	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
>>   	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
>> +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
>> +	sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
>> +	sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
>> +	sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
>>   #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
>>   	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
>>   	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9ce2bc1b3af..061104be056
>> 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> @@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function
>> suniv_f1c100s_pinctrl_functions[] = { #else
>>   	{ "uart0",	5 },	/* PE0-PE1 */
>>   #endif
>> +	{ "uart1",	5 },	/* PA0-PA3 */
> 
> Comment should be PA2-PA3. With that fixed:

Well, PA0 and PA1 are RTS and CTS for UART1, so if you don't mind, I 
will keep it like this. Not that the comment really matters anyway ;-)

Cheers,
Andre

> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> 
> Best regards,
> Jernej
> 
>>   };
>>
>>   static const struct sunxi_pinctrl_desc __maybe_unused
>> suniv_f1c100s_pinctrl_desc = { --
>> 2.25.1
> 
> 
> 


  reply	other threads:[~2022-10-18  9:24 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-12 16:34 [PATCH 0/6] sunxi: improve F1C200s support Andre Przywara
2022-10-12 16:34 ` [PATCH 1/6] sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MB Andre Przywara
2022-10-12 21:33   ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 2/6] sunxi: fix 32MB load address layout Andre Przywara
2022-10-12 21:37   ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 3/6] sunxi: f1c100: move SKIP_LOWLEVEL_INIT_ONLY into Kconfig Andre Przywara
2022-10-12 21:38   ` Jernej Škrabec
2022-10-13  8:51   ` Icenowy Zheng
2022-10-12 16:34 ` [PATCH 4/6] sunxi: f1c100: add UART1 support Andre Przywara
2022-10-12 21:42   ` Jernej Škrabec
2022-10-18  9:23     ` Andre Przywara [this message]
2022-10-19  3:55       ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 5/6] sunxi: f1c100: dtsi: add UART1 pins Andre Przywara
2022-10-12 21:43   ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 6/6] sunxi: add CherryPi-F1C200s support Andre Przywara
2022-10-13  8:33   ` Clément Péron
2022-10-13  9:53     ` Andre Przywara
2022-10-14  5:04       ` Jesse Taube
2022-10-18 14:01         ` Andre Przywara
2022-10-20 15:52           ` Giulio Benetti

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=905be4d0-74c3-c563-00e8-fcd039694cb7@arm.com \
    --to=andre.przywara@arm.com \
    --cc=giulio.benetti@benettiengineering.com \
    --cc=jagan@amarulasolutions.com \
    --cc=jernej.skrabec@gmail.com \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=me@yifangu.com \
    --cc=mr.bossman075@gmail.com \
    --cc=samuel@sholland.org \
    --cc=thirtythreeforty@gmail.com \
    --cc=u-boot@lists.denx.de \
    --cc=uwu@icenowy.me \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox