From: Roman Beranek <me@crly.cz>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>
Cc: Roman Beranek <me@crly.cz>, Frank Oltmanns <frank@oltmanns.dev>,
Icenowy Zheng <icenowy@aosp.io>, Ondrej Jirman <megi@xff.cz>,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH v2 2/7] clk: sunxi-ng: a64: export PLL_MIPI
Date: Tue, 18 Apr 2023 09:40:03 +0200 [thread overview]
Message-ID: <20230418074008.69752-3-me@crly.cz> (raw)
In-Reply-To: <20230418074008.69752-1-me@crly.cz>
PLL_MIPI will be referenced as assigned parent to TCON0
Signed-off-by: Roman Beranek <me@crly.cz>
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 4 +++-
include/dt-bindings/clock/sun50i-a64-ccu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
index a8c11c0b4e06..35ab84e03e77 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
@@ -32,7 +32,9 @@
#define CLK_PLL_PERIPH1_2X 14
#define CLK_PLL_VIDEO1 15
#define CLK_PLL_GPU 16
-#define CLK_PLL_MIPI 17
+
+/* PLL_MIPI exported for TCON0 */
+
#define CLK_PLL_HSIC 18
#define CLK_PLL_DE 19
#define CLK_PLL_DDR1 20
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index 175892189e9d..5ad769a29c4e 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -45,6 +45,7 @@
#define CLK_PLL_VIDEO0 7
#define CLK_PLL_PERIPH0 11
+#define CLK_PLL_MIPI 17
#define CLK_CPUX 21
#define CLK_BUS_MIPI_DSI 28
--
2.34.1
next prev parent reply other threads:[~2023-04-18 7:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-18 7:40 [PATCH v2 0/7] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Roman Beranek
2023-04-18 7:40 ` [PATCH v2 1/7] clk: sunxi-ng: a64: propagate rate change from pll-mipi Roman Beranek
2023-04-25 16:09 ` Maxime Ripard
2023-04-18 7:40 ` Roman Beranek [this message]
2023-04-18 7:40 ` [PATCH v2 3/7] clk: sunxi-ng: a64: prevent CLK_TCON0 being reparented Roman Beranek
2023-04-18 7:40 ` [PATCH v2 4/7] arm64: dts: allwinner: a64: assign PLL_MIPI to CLK_TCON0 Roman Beranek
2023-04-25 16:10 ` Maxime Ripard
2023-04-18 7:40 ` [PATCH v2 5/7] ARM: dts: sunxi: rename tcon's clock output Roman Beranek
2023-04-18 7:40 ` [PATCH v2 6/7] drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk Roman Beranek
2023-04-18 7:40 ` [PATCH v2 7/7] drm: sun4i: calculate proper DCLK rate for DSI Roman Beranek
2023-04-23 13:24 ` [PATCH v2 0/7] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Frank Oltmanns
2023-05-01 13:40 ` Frank Oltmanns
2023-05-03 14:22 ` Roman Beranek
2023-05-08 6:54 ` Frank Oltmanns
2023-05-08 14:08 ` Frank Oltmanns
2023-05-10 18:41 ` Jernej Škrabec
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