ARM Sunxi Platform Development
 help / color / mirror / Atom feed
From: Andre Przywara <andre.przywara@arm.com>
To: Yixun Lan <dlan@gentoo.org>
Cc: Tom Rini <trini@konsulko.com>, Simon Glass <sjg@chromium.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Mikhail Kalashnikov <iuncuim@gmail.com>,
	u-boot@lists.denx.de, linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 00/34] sunxi: clock refactoring and Allwinner A523 support
Date: Sat, 5 Apr 2025 13:32:48 +0100	[thread overview]
Message-ID: <20250405133248.62927bff@minigeek.lan> (raw)
In-Reply-To: <20250405024433-GYA8928@gentoo>

On Sat, 5 Apr 2025 02:44:33 +0000
Yixun Lan <dlan@gentoo.org> wrote:

Hi,

> On 11:35 Sun 23 Mar     , Andre Przywara wrote:
> > This series introduces support for the Allwinner A523 SoC family. The
> > same die is used in different packages: the A523, A527, T527, and H728:
> > they connect a different set of peripherals to the pins, or enable extra
> > goodies like an NPU. From a U-Boot perspective those chips do not differ
> > much, all the differences are described in the board DT files.
> > These patches are not the most refined at the moment, but I hope that
> > people start reviewing them, so we can merge the ones that are ready,
> > to reduce their number.
> > 
> > To be able to share the SPL clock code, the existing H6 code gets
> > refactored in patches 01-13. This removes the C struct describing the
> > 127 clock registers, and replaces it with macros defining the register
> > offsets. For more rationale and explanation see the 01/34 commit message.
> > 
> > Patches 14-20 extend the existing Allwinner U-Boot drivers to cope with
> > some of the changed peripherals, this includes the mandatory clock and
> > pinctrl drivers, but also some clock tweaks for the MMC controller
> > driver, and support for the new watchdog and the AXP323 used.
> > 
> > Patches 21-23 update some SPL bits to be able to cope with the A523.
> > Patches 24-28 extend the FEL handling code: the A523 has a GICv3, which
> > requires saving some GICv3 system registers, plus the IRQ mode stack
> > pointer. Patches 25-27 refactor the CPU clock code, and add the new
> > clock bits required by the A523.
> > 
> > Patch 29-32 add the new SPL bits for the A523, most prominently the DRAM
> > initialisation code. Many thanks to Jernej and Mikhail for providing
> > this part, there is a great reverse engineering and testing effort behind
> > this.
> > 
> > Patch 33 copies the DT files from the proposed Linux patches. They have
> > not been merged yet, mostly due to one missing DT binding dependency in
> > the linux-next tree, but have otherwise been agreed upon, with almost
> > every used binding being already merged. Eventually we will use the copy
> > from the DT rebasing repo, but for now those files must do.
> > 
> > The final patch adds defconfig files for the three boards that seem to be
> > the most popular at the moment, they include two development boards and
> > one TV box. The most interesting bits in there are the DRAM parameters.
> > 
> > Please have a look, review, and test.
> > 
> > Thanks!
> > Andre
> >   
> 
> 
> Is there any docs about how to compile and run this patch series?
> I've got some complaint while apply to v2025.04-rc5 (not found correct base myself)

Yes, it's pretty much work in progress, I just wanted to get the
patches out on the list, to start the review process.
You should be able to base it on "sunxi-next" or U-Boot's main next
branch.

> 
> I'm following doc/board/allwinner/sunxi.rst to build and using sunxi-tools to run,
> but it seems stuck at running uboot (should pass SPL stage)
> 
> here are steps I tried
> 
> 1) build trust firmware
> $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
> $ make CROSS_COMPILE=aarch64-unknown-linux-gnu- PLAT=sun50i_a64
> is sun50i_a64 correct for a527 SoC?

No, A64 will not work, as you figured ;-)
Jernej has a WIP branch for TF-A here:
https://github.com/jernejsk/arm-trusted-firmware/commits/a523/
Please use this and the "sun55i_a523" build target.

> besides, got a oversize error if DEBUG=1 enabled

Yes, this is a known issue, the available secure SRAM on the A64 is
just too small for all the features. Should not be a problem on other
SoCs including the A523/T527, though.

> 
> 2) build SCP

SCP is highly optional, and there is no port available anyway.
I would not know of someone working on it as well.

> 
> 3) build uboot
> $ export BL31=/home/work/trusted-firmware-a/build/sun50i_a64/release/bl31.bin  
> export SCP..
> $ make ARCH=arm CROSS_COMPILE=aarch64-unknown-linux-gnu- -j30 radxa-a5e_defconfig
> $ make ARCH=arm CROSS_COMPILE=aarch64-unknown-linux-gnu- -j30

Just use .../build/sun55i_a523/debug/bl31.bin, as mentioned above.

> 
> 4) run:  sunxi-fel -v uboot u-boot-sunxi-with-spl.bin
>  4.a) serial console from a527 board
> 
> U-Boot SPL 2025.04-rc5-00048-g432f0f975187 (Apr 05 2025 - 10:21:15 +0800)
> DRAM: 4096 MiB
> Trying to boot from FEL

Yes, this is the effect when TF-A is built for the wrong target,
normally you would see TF-A messages here.
 
>  4.b) from host which run sunxi-fel
> 
>  $ sunxi-fel -v uboot u-boot-sunxi-with-spl.bin
> found DT name in SPL header: sun55i-a527-radxa-a5e
> Stack pointers: sp_irq=0x00045400, sp=0x00060300
> MMU is not enabled by BROM
> => Executing the SPL... done.  
> loading image "ARM Trusted Firmware" (37076 bytes) to 0x54000
> loading image "U-Boot" (657216 bytes) to 0x4a000000
> loading DTB "sun55i-a527-radxa-a5e" (19024 bytes)
> Starting U-Boot (0x00054000).
> Store entry point 0x00054000 to RVBAR 0x08000040, and request warm reset with RMR mode 3... done.
> 
> is ATF loading address correct, 0x54000 here? which seems override sp address?

Yes, that's the correct address. Which SP would it collide with, anyway?

So in summary you did everything right, and the SPL is returning to FEL
with DRAM initialised, which is the biggest hurdle.
Just use the correct A523 TF-A branch and build target.

Cheers,
Andre.

  reply	other threads:[~2025-04-05 12:33 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-23 11:35 [PATCH 00/34] sunxi: clock refactoring and Allwinner A523 support Andre Przywara
2025-03-23 11:35 ` [PATCH 01/34] sunxi: clock: H6: drop usage of struct sunxi_ccm_reg Andre Przywara
2025-03-23 11:56   ` Jernej Škrabec
2025-03-23 23:50     ` Andre Przywara
2025-03-23 11:35 ` [PATCH 02/34] sunxi: mmc: remove " Andre Przywara
2025-03-23 12:04   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 03/34] sunxi: H616: dram: " Andre Przywara
2025-03-23 11:35 ` [PATCH 04/34] sunxi: H6: " Andre Przywara
2025-03-23 11:35 ` [PATCH 05/34] sunxi: clock: H6: remove " Andre Przywara
2025-03-23 11:35 ` [PATCH 06/34] sunxi: clock: H6: drop usage of struct sunxi_prcm_reg Andre Przywara
2025-03-23 11:35 ` [PATCH 07/34] sunxi: H6/H616: dram: remove " Andre Przywara
2025-03-23 11:35 ` [PATCH 08/34] sunxi: clock: H6: remove " Andre Przywara
2025-03-23 11:35 ` [PATCH 09/34] sunxi: clock: H6: unify PLL control bit definitions Andre Przywara
2025-03-23 11:35 ` [PATCH 10/34] sunxi: clock: H6: factor out clock_set_pll() Andre Przywara
2025-03-23 11:35 ` [PATCH 11/34] sunxi: clock: H6: factor out H6/H616 CPU clock setup Andre Przywara
2025-03-23 11:35 ` [PATCH 12/34] sunxi: clock: H6: add A523 CPU PLL support Andre Przywara
2025-03-23 11:35 ` [PATCH 13/34] sunxi: spl: add support for Allwinner A523 watchdog Andre Przywara
2025-03-23 12:15   ` Jernej Škrabec
2025-03-23 23:57     ` Andre Przywara
2025-03-23 11:35 ` [PATCH 14/34] dt-bindings: add Allwinner A523 CCU bindings Andre Przywara
2025-03-23 11:35 ` [PATCH 15/34] clk: sunxi: Add support for the A523 CCU Andre Przywara
2025-03-23 11:35 ` [PATCH 16/34] clk: sunxi: Add support for the A523 -R CCU Andre Przywara
2025-03-23 12:18   ` Jernej Škrabec
2025-03-24  0:37     ` Andre Przywara
2025-03-23 11:35 ` [PATCH 17/34] pinctrl: sunxi: add Allwinner A523 pinctrl description Andre Przywara
2025-03-23 11:35 ` [PATCH 18/34] sunxi: mmc: add support for Allwinner A523 MMC mod clock Andre Przywara
2025-03-23 11:35 ` [PATCH 19/34] watchdog: sunxi: add A523 support Andre Przywara
2025-03-24  8:38   ` Stefan Roese
2025-03-23 11:35 ` [PATCH 20/34] power: regulator: add AXP323 support Andre Przywara
2025-03-23 11:35 ` [PATCH 21/34] sunxi: update cpu_sunxi_ncat2.h Andre Przywara
2025-03-23 11:35 ` [PATCH 22/34] sunxi: Kconfig: consolidate SYS_CLK_FREQ selection Andre Przywara
2025-03-23 12:21   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 23/34] spl: reorder SPL_MAX_SIZE defaults for sunxi Andre Przywara
2025-03-23 12:22   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 24/34] sunxi: armv8: fel: move fel_stash variable to the front Andre Przywara
2025-03-23 12:23   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 25/34] sunxi: arm64: boot0.h: move fel_stash_addr " Andre Przywara
2025-03-23 12:23   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 26/34] sunxi: update rmr_switch.S source code Andre Przywara
2025-03-23 12:24   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 27/34] sunxi: armv8: FEL: save and restore GICv3 registers Andre Przywara
2025-03-23 12:25   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 28/34] sunxi: armv8: FEL: save and restore SP_IRQ Andre Przywara
2025-03-23 12:26   ` Jernej Škrabec
2025-03-23 23:52     ` Andre Przywara
2025-03-23 11:35 ` [PATCH 29/34] sunxi: sun50i_h6: add A523 SPL clock setup code Andre Przywara
2025-03-23 12:36   ` Jernej Škrabec
2025-03-23 11:35 ` [PATCH 30/34] sunxi: A523: add DRAM initialisation routine Andre Przywara
2025-03-23 13:15   ` Jernej Škrabec
2025-04-05 22:01   ` Yixun Lan
2025-04-07  9:26     ` Andre Przywara
2025-03-23 11:35 ` [PATCH 31/34] sunxi: A523: add DDR3 DRAM support Andre Przywara
2025-03-23 11:35 ` [PATCH 32/34] sunxi: add basic A523 support Andre Przywara
2025-03-23 11:35 ` [PATCH 33/34] sunxi: A523: add DT files from Linux v3 branch Andre Przywara
2025-04-09 14:28   ` Yixun Lan
2025-03-23 11:35 ` [PATCH 34/34] sunxi: A523: add defconfigs for three boards Andre Przywara
2025-04-05  2:44 ` [PATCH 00/34] sunxi: clock refactoring and Allwinner A523 support Yixun Lan
2025-04-05 12:32   ` Andre Przywara [this message]
2025-04-05 13:04     ` Yixun Lan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250405133248.62927bff@minigeek.lan \
    --to=andre.przywara@arm.com \
    --cc=dlan@gentoo.org \
    --cc=iuncuim@gmail.com \
    --cc=jernej.skrabec@gmail.com \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=sjg@chromium.org \
    --cc=trini@konsulko.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox