[PATCH v2 0/6] clk: sun6i-rtc: Add support for Allwinner A733 SoC

[PATCH v2 0/6] clk: sun6i-rtc: Add support for Allwinner A733 SoC

[Jerome Brunet]

Add support for the Allwinner A733 RTC and its internal Clock Control
Unit (CCU). Reuse the rtc-sun6i rtc driver while introducing a new
SoC-specific RTC CCU driver to handle the hardware's evolved clock
structure.

The A733 implementation supports hardware detection of three external
crystal frequencies (19.2MHz, 24MHz and 26MHz), which is represented in
the driver via read-only divider operations. Implement logic to derive a
normalized 32kHz reference from these DCXO sources using fixed
pre-dividers. Additionally, provide several new DCXO gate clocks for
peripherals, including SerDes, HDMI, and UFS.

This was tested on a Raxda Cubie A7A.

Changes in v2:
* Changed DT bindings as suggested. Those have changed significantly
  since v1 so I did not pick up Rob's review trailer
* Support added in the existing RTC CCU driver rather than a separate driver
* Added DT parsing clean up of the existing driver
* Xtal detection exposed by RO divider rather than a MUX.
* Dropped conversion to aux device for now. This is not strictly related
  the a733 support and will submitted again later on.
* Link to v1: https://lore.kernel.org/r/20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech

---
Jerome Brunet (5):
      dt-bindings: rtc: sun6i: add sun60i-a733 support
      clk: sunxi-ng: sun6i-rtc: clean up DT usage
      clk: sunxi-ng: div: add read-only operation support
      clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate.
      clk: sunxi-ng: sun6i-rtc: add a733 support

Junhui Liu (1):
      clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration

 .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml      |   1 +
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c               | 124 +++++++++++++++------
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.h               |   3 +-
 drivers/clk/sunxi-ng/ccu_common.h                  |   1 +
 drivers/clk/sunxi-ng/ccu_div.c                     |  11 ++
 drivers/clk/sunxi-ng/ccu_div.h                     |   1 +
 include/dt-bindings/clock/sun6i-rtc.h              |   4 +
 7 files changed, 109 insertions(+), 36 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20251226-a733-rtc-c5167df14e6e

Best regards,
--  
Jerome

[PATCH v2 1/6] dt-bindings: rtc: sun6i: add sun60i-a733 support

[Jerome Brunet]

Add a new rtc compatible for the sun60i-a733 SoC and new IDs for the
peripheral oscillator clock gates of this SoC.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 1 +
 include/dt-bindings/clock/sun6i-rtc.h                              | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
index 9df5cdb6f63f..197a6f67b180 100644
--- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
@@ -33,6 +33,7 @@ properties:
           - enum:
               - allwinner,sun20i-d1-rtc
               - allwinner,sun55i-a523-rtc
+              - allwinner,sun60i-a733-rtc
           - const: allwinner,sun50i-r329-rtc
 
   reg:
diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
index 3bd3aa3d57ce..5132a393ca4b 100644
--- a/include/dt-bindings/clock/sun6i-rtc.h
+++ b/include/dt-bindings/clock/sun6i-rtc.h
@@ -6,5 +6,9 @@
 #define CLK_OSC32K		0
 #define CLK_OSC32K_FANOUT	1
 #define CLK_IOSC		2
+#define CLK_HOSC_UFS		8
+#define CLK_HOSC_HDMI		9
+#define CLK_HOSC_SERDES0	10
+#define CLK_HOSC_SERDES1	11
 
 #endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */

-- 
2.47.3

Re: [PATCH v2 1/6] dt-bindings: rtc: sun6i: add sun60i-a733 support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `clock-output-names` property has a global `maxItems: 3` constraint and a description limiting it to three clocks, which contradicts the new clock outputs (IDs up to 11) added for the sun60i-a733-rtc.
--

commit a1565b632e372c724867216463a453c9d1600ad2
Author: Jerome Brunet <jbrunet@baylibre.com>

dt-bindings: rtc: sun6i: add sun60i-a733 support
    
Adds a new rtc compatible for the sun60i-a733 SoC and new IDs for the
peripheral oscillator clock gates of this SoC.

> diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> index 9df5cdb6f63f2..197a6f67b180a 100644
> --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> @@ -33,6 +33,7 @@ properties:
>            - enum:
>                - allwinner,sun20i-d1-rtc
>                - allwinner,sun55i-a523-rtc
> +              - allwinner,sun60i-a733-rtc
>            - const: allwinner,sun50i-r329-rtc

[ ... ]

> diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
> index 3bd3aa3d57ce1..5132a393ca4b6 100644
> --- a/include/dt-bindings/clock/sun6i-rtc.h
> +++ b/include/dt-bindings/clock/sun6i-rtc.h
> @@ -6,5 +6,9 @@
>  #define CLK_OSC32K		0
>  #define CLK_OSC32K_FANOUT	1
>  #define CLK_IOSC		2
> +#define CLK_HOSC_UFS		8
> +#define CLK_HOSC_HDMI		9
> +#define CLK_HOSC_SERDES0	10
> +#define CLK_HOSC_SERDES1	11

[Severity: Low]
Will adding clock IDs up to 11 conflict with the existing clock-output-names
constraint in allwinner,sun6i-a31-rtc.yaml?

The clock-output-names property currently has a global maxItems constraint
alongside its description:

  clock-output-names:
    minItems: 1
    maxItems: 3
    description:
      The RTC provides up to three clocks

If a device tree author attempts to define an array of clock-output-names
to document all outputs for the allwinner,sun60i-a733-rtc node, won't it fail
dt_binding_check validation because it exceeds the maximum allowed items?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629-a733-rtc-v2-0-7b72112784f8@baylibre.com?part=1

Re: [PATCH v2 1/6] dt-bindings: rtc: sun6i: add sun60i-a733 support

[Jerome Brunet]

On lun. 29 juin 2026 at 12:53, sashiko-bot@kernel.org wrote:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] The `clock-output-names` property has a global `maxItems: 3`
> constraint and a description limiting it to three clocks, which contradicts
> the new clock outputs (IDs up to 11) added for the sun60i-a733-rtc.
> --
>
> commit a1565b632e372c724867216463a453c9d1600ad2
> Author: Jerome Brunet <jbrunet@baylibre.com>
>
> dt-bindings: rtc: sun6i: add sun60i-a733 support
>     
> Adds a new rtc compatible for the sun60i-a733 SoC and new IDs for the
> peripheral oscillator clock gates of this SoC.
>
>> diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
>> index 9df5cdb6f63f2..197a6f67b180a 100644
>> --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
>> +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
>> @@ -33,6 +33,7 @@ properties:
>>            - enum:
>>                - allwinner,sun20i-d1-rtc
>>                - allwinner,sun55i-a523-rtc
>> +              - allwinner,sun60i-a733-rtc
>>            - const: allwinner,sun50i-r329-rtc
>
> [ ... ]
>
>> diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
>> index 3bd3aa3d57ce1..5132a393ca4b6 100644
>> --- a/include/dt-bindings/clock/sun6i-rtc.h
>> +++ b/include/dt-bindings/clock/sun6i-rtc.h
>> @@ -6,5 +6,9 @@
>>  #define CLK_OSC32K		0
>>  #define CLK_OSC32K_FANOUT	1
>>  #define CLK_IOSC		2
>> +#define CLK_HOSC_UFS		8
>> +#define CLK_HOSC_HDMI		9
>> +#define CLK_HOSC_SERDES0	10
>> +#define CLK_HOSC_SERDES1	11
>
> [Severity: Low]
> Will adding clock IDs up to 11 conflict with the existing clock-output-names
> constraint in allwinner,sun6i-a31-rtc.yaml?
>
> The clock-output-names property currently has a global maxItems constraint
> alongside its description:
>
>   clock-output-names:
>     minItems: 1
>     maxItems: 3
>     description:
>       The RTC provides up to three clocks
>
> If a device tree author attempts to define an array of clock-output-names
> to document all outputs for the allwinner,sun60i-a733-rtc node, won't it fail
> dt_binding_check validation because it exceeds the maximum allowed items?

Not quite sure what to do with that one.

The h616 compatible devices all exposed more than 3 clock through the
provider, even if the higher IDs did not have define.

The clock output names for the h616 compatible device are not really
supposed to be defined through DT ... at least AFAIU ??

-- 
Jerome

Re: [PATCH v2 1/6] dt-bindings: rtc: sun6i: add sun60i-a733 support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3124 bytes --]

On Mon, Jun 29, 2026 at 05:05:51PM +0200, Jerome Brunet wrote:
> On lun. 29 juin 2026 at 12:53, sashiko-bot@kernel.org wrote:
> 
> > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> > - [Low] The `clock-output-names` property has a global `maxItems: 3`
> > constraint and a description limiting it to three clocks, which contradicts
> > the new clock outputs (IDs up to 11) added for the sun60i-a733-rtc.
> > --
> >
> > commit a1565b632e372c724867216463a453c9d1600ad2
> > Author: Jerome Brunet <jbrunet@baylibre.com>
> >
> > dt-bindings: rtc: sun6i: add sun60i-a733 support
> >     
> > Adds a new rtc compatible for the sun60i-a733 SoC and new IDs for the
> > peripheral oscillator clock gates of this SoC.
> >
> >> diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> >> index 9df5cdb6f63f2..197a6f67b180a 100644
> >> --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> >> +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> >> @@ -33,6 +33,7 @@ properties:
> >>            - enum:
> >>                - allwinner,sun20i-d1-rtc
> >>                - allwinner,sun55i-a523-rtc
> >> +              - allwinner,sun60i-a733-rtc
> >>            - const: allwinner,sun50i-r329-rtc
> >
> > [ ... ]
> >
> >> diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
> >> index 3bd3aa3d57ce1..5132a393ca4b6 100644
> >> --- a/include/dt-bindings/clock/sun6i-rtc.h
> >> +++ b/include/dt-bindings/clock/sun6i-rtc.h
> >> @@ -6,5 +6,9 @@
> >>  #define CLK_OSC32K		0
> >>  #define CLK_OSC32K_FANOUT	1
> >>  #define CLK_IOSC		2
> >> +#define CLK_HOSC_UFS		8
> >> +#define CLK_HOSC_HDMI		9
> >> +#define CLK_HOSC_SERDES0	10
> >> +#define CLK_HOSC_SERDES1	11
> >
> > [Severity: Low]
> > Will adding clock IDs up to 11 conflict with the existing clock-output-names
> > constraint in allwinner,sun6i-a31-rtc.yaml?
> >
> > The clock-output-names property currently has a global maxItems constraint
> > alongside its description:
> >
> >   clock-output-names:
> >     minItems: 1
> >     maxItems: 3
> >     description:
> >       The RTC provides up to three clocks
> >
> > If a device tree author attempts to define an array of clock-output-names
> > to document all outputs for the allwinner,sun60i-a733-rtc node, won't it fail
> > dt_binding_check validation because it exceeds the maximum allowed items?
> 
> Not quite sure what to do with that one.
> 
> The h616 compatible devices all exposed more than 3 clock through the
> provider, even if the higher IDs did not have define.
> 
> The clock output names for the h616 compatible device are not really
> supposed to be defined through DT ... at least AFAIU ??

The output names aren't even defined anyway, so the property is not
really all that helpful. It's worth increasing the max to whatever is
permitted now and look into the conditional sections to see if any
constraints need updating.

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Re: [PATCH v2 1/6] dt-bindings: rtc: sun6i: add sun60i-a733 support

[Chen-Yu Tsai]

On Mon, Jun 29, 2026 at 11:16 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Mon, Jun 29, 2026 at 05:05:51PM +0200, Jerome Brunet wrote:
> > On lun. 29 juin 2026 at 12:53, sashiko-bot@kernel.org wrote:
> >
> > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> > > - [Low] The `clock-output-names` property has a global `maxItems: 3`
> > > constraint and a description limiting it to three clocks, which contradicts
> > > the new clock outputs (IDs up to 11) added for the sun60i-a733-rtc.
> > > --
> > >
> > > commit a1565b632e372c724867216463a453c9d1600ad2
> > > Author: Jerome Brunet <jbrunet@baylibre.com>
> > >
> > > dt-bindings: rtc: sun6i: add sun60i-a733 support
> > >
> > > Adds a new rtc compatible for the sun60i-a733 SoC and new IDs for the
> > > peripheral oscillator clock gates of this SoC.
> > >
> > >> diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> > >> index 9df5cdb6f63f2..197a6f67b180a 100644
> > >> --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> > >> +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> > >> @@ -33,6 +33,7 @@ properties:
> > >>            - enum:
> > >>                - allwinner,sun20i-d1-rtc
> > >>                - allwinner,sun55i-a523-rtc
> > >> +              - allwinner,sun60i-a733-rtc
> > >>            - const: allwinner,sun50i-r329-rtc
> > >
> > > [ ... ]
> > >
> > >> diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
> > >> index 3bd3aa3d57ce1..5132a393ca4b6 100644
> > >> --- a/include/dt-bindings/clock/sun6i-rtc.h
> > >> +++ b/include/dt-bindings/clock/sun6i-rtc.h
> > >> @@ -6,5 +6,9 @@
> > >>  #define CLK_OSC32K                0
> > >>  #define CLK_OSC32K_FANOUT 1
> > >>  #define CLK_IOSC          2
> > >> +#define CLK_HOSC_UFS              8
> > >> +#define CLK_HOSC_HDMI             9
> > >> +#define CLK_HOSC_SERDES0  10
> > >> +#define CLK_HOSC_SERDES1  11
> > >
> > > [Severity: Low]
> > > Will adding clock IDs up to 11 conflict with the existing clock-output-names
> > > constraint in allwinner,sun6i-a31-rtc.yaml?
> > >
> > > The clock-output-names property currently has a global maxItems constraint
> > > alongside its description:
> > >
> > >   clock-output-names:
> > >     minItems: 1
> > >     maxItems: 3
> > >     description:
> > >       The RTC provides up to three clocks
> > >
> > > If a device tree author attempts to define an array of clock-output-names
> > > to document all outputs for the allwinner,sun60i-a733-rtc node, won't it fail
> > > dt_binding_check validation because it exceeds the maximum allowed items?
> >
> > Not quite sure what to do with that one.
> >
> > The h616 compatible devices all exposed more than 3 clock through the
> > provider, even if the higher IDs did not have define.
> >
> > The clock output names for the h616 compatible device are not really
> > supposed to be defined through DT ... at least AFAIU ??
>
> The output names aren't even defined anyway, so the property is not
> really all that helpful. It's worth increasing the max to whatever is
> permitted now and look into the conditional sections to see if any
> constraints need updating.

Or just not allow it for the newer RTC compatible? On the kernel side,
the sunxi-ng clk library doesn't even use the property, presumably because
the library mainly targets the main clock controller that has at least
tens of clocks. Writing clock-output-names for them isn't really scalable,
and sort of useless as the name can be inferred by the clock ID and
compatible.


ChenYu

Re: [PATCH v2 1/6] dt-bindings: rtc: sun6i: add sun60i-a733 support

[Jerome Brunet]

On lun. 29 juin 2026 at 23:20, Chen-Yu Tsai <wens@kernel.org> wrote:

> On Mon, Jun 29, 2026 at 11:16 PM Conor Dooley <conor@kernel.org> wrote:
>>
>> On Mon, Jun 29, 2026 at 05:05:51PM +0200, Jerome Brunet wrote:
>> > On lun. 29 juin 2026 at 12:53, sashiko-bot@kernel.org wrote:
>> >
>> > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>> > > - [Low] The `clock-output-names` property has a global `maxItems: 3`
>> > > constraint and a description limiting it to three clocks, which contradicts
>> > > the new clock outputs (IDs up to 11) added for the sun60i-a733-rtc.
>> > > --
>> > >
>> > > commit a1565b632e372c724867216463a453c9d1600ad2
>> > > Author: Jerome Brunet <jbrunet@baylibre.com>
>> > >
>> > > dt-bindings: rtc: sun6i: add sun60i-a733 support
>> > >
>> > > Adds a new rtc compatible for the sun60i-a733 SoC and new IDs for the
>> > > peripheral oscillator clock gates of this SoC.
>> > >
>> > >> diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
>> > >> index 9df5cdb6f63f2..197a6f67b180a 100644
>> > >> --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
>> > >> +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
>> > >> @@ -33,6 +33,7 @@ properties:
>> > >>            - enum:
>> > >>                - allwinner,sun20i-d1-rtc
>> > >>                - allwinner,sun55i-a523-rtc
>> > >> +              - allwinner,sun60i-a733-rtc
>> > >>            - const: allwinner,sun50i-r329-rtc
>> > >
>> > > [ ... ]
>> > >
>> > >> diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
>> > >> index 3bd3aa3d57ce1..5132a393ca4b6 100644
>> > >> --- a/include/dt-bindings/clock/sun6i-rtc.h
>> > >> +++ b/include/dt-bindings/clock/sun6i-rtc.h
>> > >> @@ -6,5 +6,9 @@
>> > >>  #define CLK_OSC32K                0
>> > >>  #define CLK_OSC32K_FANOUT 1
>> > >>  #define CLK_IOSC          2
>> > >> +#define CLK_HOSC_UFS              8
>> > >> +#define CLK_HOSC_HDMI             9
>> > >> +#define CLK_HOSC_SERDES0  10
>> > >> +#define CLK_HOSC_SERDES1  11
>> > >
>> > > [Severity: Low]
>> > > Will adding clock IDs up to 11 conflict with the existing clock-output-names
>> > > constraint in allwinner,sun6i-a31-rtc.yaml?
>> > >
>> > > The clock-output-names property currently has a global maxItems constraint
>> > > alongside its description:
>> > >
>> > >   clock-output-names:
>> > >     minItems: 1
>> > >     maxItems: 3
>> > >     description:
>> > >       The RTC provides up to three clocks
>> > >
>> > > If a device tree author attempts to define an array of clock-output-names
>> > > to document all outputs for the allwinner,sun60i-a733-rtc node, won't it fail
>> > > dt_binding_check validation because it exceeds the maximum allowed items?
>> >
>> > Not quite sure what to do with that one.
>> >
>> > The h616 compatible devices all exposed more than 3 clock through the
>> > provider, even if the higher IDs did not have define.
>> >
>> > The clock output names for the h616 compatible device are not really
>> > supposed to be defined through DT ... at least AFAIU ??
>>
>> The output names aren't even defined anyway, so the property is not
>> really all that helpful. It's worth increasing the max to whatever is
>> permitted now and look into the conditional sections to see if any
>> constraints need updating.
>
> Or just not allow it for the newer RTC compatible? On the kernel side,

I was edging toward this. Would this be acceptable to you Conor ?
I'm thinking about disallowing it for all the h616 compatible ones, not
just the a733.

> the sunxi-ng clk library doesn't even use the property, presumably because
> the library mainly targets the main clock controller that has at least
> tens of clocks. Writing clock-output-names for them isn't really scalable,
> and sort of useless as the name can be inferred by the clock ID and
> compatible.
>
>
> ChenYu

-- 
Jerome

Re: [PATCH v2 1/6] dt-bindings: rtc: sun6i: add sun60i-a733 support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 4089 bytes --]

On Mon, Jun 29, 2026 at 05:27:01PM +0200, Jerome Brunet wrote:
> On lun. 29 juin 2026 at 23:20, Chen-Yu Tsai <wens@kernel.org> wrote:
> 
> > On Mon, Jun 29, 2026 at 11:16 PM Conor Dooley <conor@kernel.org> wrote:
> >>
> >> On Mon, Jun 29, 2026 at 05:05:51PM +0200, Jerome Brunet wrote:
> >> > On lun. 29 juin 2026 at 12:53, sashiko-bot@kernel.org wrote:
> >> >
> >> > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> >> > > - [Low] The `clock-output-names` property has a global `maxItems: 3`
> >> > > constraint and a description limiting it to three clocks, which contradicts
> >> > > the new clock outputs (IDs up to 11) added for the sun60i-a733-rtc.
> >> > > --
> >> > >
> >> > > commit a1565b632e372c724867216463a453c9d1600ad2
> >> > > Author: Jerome Brunet <jbrunet@baylibre.com>
> >> > >
> >> > > dt-bindings: rtc: sun6i: add sun60i-a733 support
> >> > >
> >> > > Adds a new rtc compatible for the sun60i-a733 SoC and new IDs for the
> >> > > peripheral oscillator clock gates of this SoC.
> >> > >
> >> > >> diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> >> > >> index 9df5cdb6f63f2..197a6f67b180a 100644
> >> > >> --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> >> > >> +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> >> > >> @@ -33,6 +33,7 @@ properties:
> >> > >>            - enum:
> >> > >>                - allwinner,sun20i-d1-rtc
> >> > >>                - allwinner,sun55i-a523-rtc
> >> > >> +              - allwinner,sun60i-a733-rtc
> >> > >>            - const: allwinner,sun50i-r329-rtc
> >> > >
> >> > > [ ... ]
> >> > >
> >> > >> diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
> >> > >> index 3bd3aa3d57ce1..5132a393ca4b6 100644
> >> > >> --- a/include/dt-bindings/clock/sun6i-rtc.h
> >> > >> +++ b/include/dt-bindings/clock/sun6i-rtc.h
> >> > >> @@ -6,5 +6,9 @@
> >> > >>  #define CLK_OSC32K                0
> >> > >>  #define CLK_OSC32K_FANOUT 1
> >> > >>  #define CLK_IOSC          2
> >> > >> +#define CLK_HOSC_UFS              8
> >> > >> +#define CLK_HOSC_HDMI             9
> >> > >> +#define CLK_HOSC_SERDES0  10
> >> > >> +#define CLK_HOSC_SERDES1  11
> >> > >
> >> > > [Severity: Low]
> >> > > Will adding clock IDs up to 11 conflict with the existing clock-output-names
> >> > > constraint in allwinner,sun6i-a31-rtc.yaml?
> >> > >
> >> > > The clock-output-names property currently has a global maxItems constraint
> >> > > alongside its description:
> >> > >
> >> > >   clock-output-names:
> >> > >     minItems: 1
> >> > >     maxItems: 3
> >> > >     description:
> >> > >       The RTC provides up to three clocks
> >> > >
> >> > > If a device tree author attempts to define an array of clock-output-names
> >> > > to document all outputs for the allwinner,sun60i-a733-rtc node, won't it fail
> >> > > dt_binding_check validation because it exceeds the maximum allowed items?
> >> >
> >> > Not quite sure what to do with that one.
> >> >
> >> > The h616 compatible devices all exposed more than 3 clock through the
> >> > provider, even if the higher IDs did not have define.
> >> >
> >> > The clock output names for the h616 compatible device are not really
> >> > supposed to be defined through DT ... at least AFAIU ??
> >>
> >> The output names aren't even defined anyway, so the property is not
> >> really all that helpful. It's worth increasing the max to whatever is
> >> permitted now and look into the conditional sections to see if any
> >> constraints need updating.
> >
> > Or just not allow it for the newer RTC compatible? On the kernel side,
> 
> I was edging toward this. Would this be acceptable to you Conor ?
> I'm thinking about disallowing it for all the h616 compatible ones, not
> just the a733.

Works for me.
Just make sure you note somewhere that the names aren't ever defined
anyway.

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[PATCH v2 2/6] clk: sunxi-ng: sun6i-rtc: clean up DT usage

[Jerome Brunet]

With sun6i-rtc compatible devices, the "ext-osc32k" clock input
is optional for the devices that support this input (r329 and onward).

Probably preparing for older SoC support, the driver does something funny
when parsing DT. It check if "ext-osc32k" is present in the clock-names and
if it is not, it uses the first clock as "ext-osc32k". This clock will
actually be the rtc bus clock so what the driver does is wrong.

At the moment, the driver does not support the older SoCs that would have
an external 32k clock provided on index #0 so just remove this quirk.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 23 +++--------------------
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
index f6bfeba009e8..0f528bfaed00 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -191,10 +191,8 @@ static struct ccu_common iosc_32k_clk = {
 					 CLK_GET_RATE_NOCACHE),
 };
 
-static const struct clk_hw *ext_osc32k[] = { NULL }; /* updated during probe */
-
-static SUNXI_CCU_GATE_HWS(ext_osc32k_gate_clk, "ext-osc32k-gate",
-			  ext_osc32k, 0x0, BIT(4), 0);
+static SUNXI_CCU_GATE_FW(ext_osc32k_gate_clk, "ext-osc32k-gate",
+			  "ext-osc32k", 0x0, BIT(4), 0);
 
 static const struct clk_hw *osc32k_parents[] = {
 	&iosc_32k_clk.hw,
@@ -352,7 +350,6 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match);
 int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
 {
 	const struct sun6i_rtc_match_data *data;
-	struct clk *ext_osc32k_clk = NULL;
 	const struct of_device_id *match;
 
 	/* This driver is only used for newer variants of the hardware. */
@@ -363,21 +360,7 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
 	data = match->data;
 	have_iosc_calibration = data->have_iosc_calibration;
 
-	if (data->have_ext_osc32k) {
-		const char *fw_name;
-
-		/* ext-osc32k was the only input clock in the old binding. */
-		fw_name = of_property_present(dev->of_node, "clock-names")
-			? "ext-osc32k" : NULL;
-		ext_osc32k_clk = devm_clk_get_optional(dev, fw_name);
-		if (IS_ERR(ext_osc32k_clk))
-			return PTR_ERR(ext_osc32k_clk);
-	}
-
-	if (ext_osc32k_clk) {
-		/* Link ext-osc32k-gate to its parent. */
-		*ext_osc32k = __clk_get_hw(ext_osc32k_clk);
-	} else {
+	if (!data->have_ext_osc32k) {
 		/* ext-osc32k-gate is an orphan, so do not register it. */
 		sun6i_rtc_ccu_hw_clks.hws[CLK_EXT_OSC32K_GATE] = NULL;
 		osc32k_init_data.num_parents = 1;

-- 
2.47.3

Re: [PATCH v2 2/6] clk: sunxi-ng: sun6i-rtc: clean up DT usage

[Chen-Yu Tsai]

On Mon, Jun 29, 2026 at 8:42 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> With sun6i-rtc compatible devices, the "ext-osc32k" clock input
> is optional for the devices that support this input (r329 and onward).
>
> Probably preparing for older SoC support, the driver does something funny
> when parsing DT. It check if "ext-osc32k" is present in the clock-names and
> if it is not, it uses the first clock as "ext-osc32k". This clock will
> actually be the rtc bus clock so what the driver does is wrong.
>
> At the moment, the driver does not support the older SoCs that would have
> an external 32k clock provided on index #0 so just remove this quirk.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>

[PATCH v2 3/6] clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration

[Jerome Brunet]

From: Junhui Liu <junhui.liu@pigmoral.tech>

The sun6i-rtc CCU driver currently uses a global static variable to
denote whether calibration is supported, which makes IOSC operations
tightly coupled to this file.

Convert this into a feature bit to decouple the logic. This allows the
IOSC clock code to be moved into a shared module for reuse by other SoCs.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Jerome Brunet<jbrunet@baylibre.com>
---
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 17 +++++++++--------
 drivers/clk/sunxi-ng/ccu_common.h    |  1 +
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
index 0f528bfaed00..b24c8b196e66 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -52,8 +52,6 @@ struct sun6i_rtc_match_data {
 	u8				osc32k_fanout_nparents;
 };
 
-static bool have_iosc_calibration;
-
 static int ccu_iosc_enable(struct clk_hw *hw)
 {
 	struct ccu_common *cm = hw_to_ccu_common(hw);
@@ -80,7 +78,7 @@ static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw,
 {
 	struct ccu_common *cm = hw_to_ccu_common(hw);
 
-	if (have_iosc_calibration) {
+	if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) {
 		u32 reg = readl(cm->base + IOSC_CLK_CALI_REG);
 
 		/*
@@ -119,7 +117,7 @@ static int ccu_iosc_32k_prepare(struct clk_hw *hw)
 	struct ccu_common *cm = hw_to_ccu_common(hw);
 	u32 val;
 
-	if (!have_iosc_calibration)
+	if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION))
 		return 0;
 
 	val = readl(cm->base + IOSC_CLK_CALI_REG);
@@ -134,7 +132,7 @@ static void ccu_iosc_32k_unprepare(struct clk_hw *hw)
 	struct ccu_common *cm = hw_to_ccu_common(hw);
 	u32 val;
 
-	if (!have_iosc_calibration)
+	if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION))
 		return;
 
 	val = readl(cm->base + IOSC_CLK_CALI_REG);
@@ -148,7 +146,7 @@ static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw,
 	struct ccu_common *cm = hw_to_ccu_common(hw);
 	u32 val;
 
-	if (have_iosc_calibration) {
+	if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) {
 		val = readl(cm->base + IOSC_CLK_CALI_REG);
 
 		/* Assume the calibrated 32k clock is accurate. */
@@ -167,7 +165,7 @@ static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw,
 	struct ccu_common *cm = hw_to_ccu_common(hw);
 	u32 val;
 
-	if (have_iosc_calibration) {
+	if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) {
 		val = readl(cm->base + IOSC_CLK_CALI_REG);
 
 		/* Assume the calibrated 32k clock is accurate. */
@@ -358,7 +356,10 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
 		return 0;
 
 	data = match->data;
-	have_iosc_calibration = data->have_iosc_calibration;
+	if (data->have_iosc_calibration) {
+		iosc_clk.features |= CCU_FEATURE_IOSC_CALIBRATION;
+		iosc_32k_clk.features |= CCU_FEATURE_IOSC_CALIBRATION;
+	}
 
 	if (!data->have_ext_osc32k) {
 		/* ext-osc32k-gate is an orphan, so do not register it. */
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index bbec283b9d99..d9dc24ad5503 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -21,6 +21,7 @@
 #define CCU_FEATURE_CLOSEST_RATE	BIT(9)
 #define CCU_FEATURE_DUAL_DIV		BIT(10)
 #define CCU_FEATURE_UPDATE_BIT		BIT(11)
+#define CCU_FEATURE_IOSC_CALIBRATION	BIT(12)
 
 /* MMC timing mode switch bit */
 #define CCU_MMC_NEW_TIMING_MODE		BIT(30)

-- 
2.47.3

Re: [PATCH v2 3/6] clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration

[Chen-Yu Tsai]

On Mon, Jun 29, 2026 at 8:42 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> From: Junhui Liu <junhui.liu@pigmoral.tech>
>
> The sun6i-rtc CCU driver currently uses a global static variable to
> denote whether calibration is supported, which makes IOSC operations
> tightly coupled to this file.
>
> Convert this into a feature bit to decouple the logic. This allows the
> IOSC clock code to be moved into a shared module for reuse by other SoCs.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> Signed-off-by: Jerome Brunet<jbrunet@baylibre.com>

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>

[PATCH v2 4/6] clk: sunxi-ng: div: add read-only operation support

[Jerome Brunet]

Add support for sunxi-ng read-only dividers. This will be
useful to the a733 oscillator detection logic.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/sunxi-ng/ccu_div.c | 11 +++++++++++
 drivers/clk/sunxi-ng/ccu_div.h |  1 +
 2 files changed, 12 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index 62d680ccb524..0e3d9e6e30fb 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -143,3 +143,14 @@ const struct clk_ops ccu_div_ops = {
 	.set_rate	= ccu_div_set_rate,
 };
 EXPORT_SYMBOL_NS_GPL(ccu_div_ops, "SUNXI_CCU");
+
+const struct clk_ops ccu_rodiv_ops = {
+	.disable	= ccu_div_disable,
+	.enable		= ccu_div_enable,
+	.is_enabled	= ccu_div_is_enabled,
+
+	.get_parent	= ccu_div_get_parent,
+
+	.recalc_rate	= ccu_div_recalc_rate,
+};
+EXPORT_SYMBOL_NS_GPL(ccu_rodiv_ops, "SUNXI_CCU");
diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
index be00b3277e97..a30a92780a05 100644
--- a/drivers/clk/sunxi-ng/ccu_div.h
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -300,5 +300,6 @@ static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
 }
 
 extern const struct clk_ops ccu_div_ops;
+extern const struct clk_ops ccu_rodiv_ops;
 
 #endif /* _CCU_DIV_H_ */

-- 
2.47.3

Re: [PATCH v2 4/6] clk: sunxi-ng: div: add read-only operation support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] `ccu_rodiv_ops` omits the `.determine_rate` callback, which breaks rate rounding, reparenting, and proper rate propagation for clocks using `CLK_SET_RATE_PARENT`.
--

commit 97a1d0e7adc68eb81524d76b0c667da1b5f1be50
Author: Jerome Brunet <jbrunet@baylibre.com>

clk: sunxi-ng: div: add read-only operation support

Add support for sunxi-ng read-only dividers to be used by the a733
oscillator detection logic.

> diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
> index 62d680ccb524b..0e3d9e6e30fb0 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.c
> +++ b/drivers/clk/sunxi-ng/ccu_div.c
> @@ -143,3 +143,14 @@ const struct clk_ops ccu_div_ops = {
>  	.set_rate	= ccu_div_set_rate,
>  };
>  EXPORT_SYMBOL_NS_GPL(ccu_div_ops, "SUNXI_CCU");
> +
> +const struct clk_ops ccu_rodiv_ops = {
> +	.disable	= ccu_div_disable,
> +	.enable		= ccu_div_enable,
> +	.is_enabled	= ccu_div_is_enabled,
> +
> +	.get_parent	= ccu_div_get_parent,
> +
> +	.recalc_rate	= ccu_div_recalc_rate,

[Severity: Medium]
Does this struct need a .determine_rate callback to prevent breaking rate
rounding and parent rate propagation?

If a driver registers a clock using these exported operations and sets the
CLK_SET_RATE_PARENT flag, the Common Clock Framework's
clk_core_round_rate_nolock() falls back to a pass-through behavior when
.determine_rate is missing. This causes it to forward the child's requested
rate unmodified to the parent, ignoring the divider scaling, and also causes
mux reparenting to fail.

> +};
> +EXPORT_SYMBOL_NS_GPL(ccu_rodiv_ops, "SUNXI_CCU");

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629-a733-rtc-v2-0-7b72112784f8@baylibre.com?part=4

Re: [PATCH v2 4/6] clk: sunxi-ng: div: add read-only operation support

[Jerome Brunet]

On lun. 29 juin 2026 at 13:03, sashiko-bot@kernel.org wrote:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] `ccu_rodiv_ops` omits the `.determine_rate` callback, which breaks rate rounding, reparenting, and proper rate propagation for clocks using `CLK_SET_RATE_PARENT`.
> --
>
> commit 97a1d0e7adc68eb81524d76b0c667da1b5f1be50
> Author: Jerome Brunet <jbrunet@baylibre.com>
>
> clk: sunxi-ng: div: add read-only operation support
>
> Add support for sunxi-ng read-only dividers to be used by the a733
> oscillator detection logic.
>
>> diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
>> index 62d680ccb524b..0e3d9e6e30fb0 100644
>> --- a/drivers/clk/sunxi-ng/ccu_div.c
>> +++ b/drivers/clk/sunxi-ng/ccu_div.c
>> @@ -143,3 +143,14 @@ const struct clk_ops ccu_div_ops = {
>>  	.set_rate	= ccu_div_set_rate,
>>  };
>>  EXPORT_SYMBOL_NS_GPL(ccu_div_ops, "SUNXI_CCU");
>> +
>> +const struct clk_ops ccu_rodiv_ops = {
>> +	.disable	= ccu_div_disable,
>> +	.enable		= ccu_div_enable,
>> +	.is_enabled	= ccu_div_is_enabled,
>> +
>> +	.get_parent	= ccu_div_get_parent,
>> +
>> +	.recalc_rate	= ccu_div_recalc_rate,
>
> [Severity: Medium]
> Does this struct need a .determine_rate callback to prevent breaking rate
> rounding and parent rate propagation?

I don't think is a problem in the specific context of this series since
not parent on the RO clock may adjust but it is indeed something to fix
in the next revision

>
> If a driver registers a clock using these exported operations and sets the
> CLK_SET_RATE_PARENT flag, the Common Clock Framework's
> clk_core_round_rate_nolock() falls back to a pass-through behavior when
> .determine_rate is missing. This causes it to forward the child's requested
> rate unmodified to the parent, ignoring the divider scaling, and also causes
> mux reparenting to fail.
>
>> +};
>> +EXPORT_SYMBOL_NS_GPL(ccu_rodiv_ops, "SUNXI_CCU");

-- 
Jerome

[PATCH v2 5/6] clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate.

[Jerome Brunet]

On the a733 the "osc24M-32k" clock has the same gate bits as the previously
supported SoC but a different divider implementation.

Instead of a fixed 750 divider, the divider is selected based on the
rate of the oscillator. It can be seen as a simple read-only divider.

To easily replace the divider part depending the SoC, split the divider
and gate into two separate clock entities.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 20 +++++++++++---------
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.h |  3 ++-
 2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
index b24c8b196e66..25dd87e78eb7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -218,17 +218,18 @@ static const struct clk_parent_data osc24M[] = {
 	{ .fw_name = "hosc", .name = "osc24M" }
 };
 
-static struct ccu_gate osc24M_32k_clk = {
-	.enable	= BIT(16),
-	.common	= {
-		.reg		= LOSC_OUT_GATING_REG,
-		.prediv		= 750,
-		.features	= CCU_FEATURE_ALL_PREDIV,
-		.hw.init	= CLK_HW_INIT_PARENTS_DATA("osc24M-32k", osc24M,
-							   &ccu_gate_ops, 0),
-	},
+static struct clk_fixed_factor osc24M_32k_div_clk = {
+	.mult = 1,
+	.div = 750,
+	.hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div",
+					    osc24M,
+					    &clk_fixed_factor_ops,
+					    0),
 };
 
+static SUNXI_CCU_GATE_HW(osc24M_32k_clk, "osc24M-32k", &osc24M_32k_div_clk.hw,
+			 LOSC_OUT_GATING_REG, BIT(16), 0);
+
 static const struct clk_hw *rtc_32k_parents[] = {
 	&osc32k_clk.common.hw,
 	&osc24M_32k_clk.common.hw
@@ -286,6 +287,7 @@ static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
 		[CLK_EXT_OSC32K_GATE]	= &ext_osc32k_gate_clk.common.hw,
 		[CLK_OSC24M_32K]	= &osc24M_32k_clk.common.hw,
 		[CLK_RTC_32K]		= &rtc_32k_clk.common.hw,
+		[CLK_OSC24M_32K_DIV]	= &osc24M_32k_div_clk.hw,
 	},
 };
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
index 9ae821fc2599..ab7b92b47f59 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
@@ -9,7 +9,8 @@
 #define CLK_EXT_OSC32K_GATE	4
 #define CLK_OSC24M_32K		5
 #define CLK_RTC_32K		6
+#define CLK_OSC24M_32K_DIV	7
 
-#define CLK_NUMBER		(CLK_RTC_32K + 1)
+#define CLK_NUMBER		(CLK_OSC24M_32K_DIV + 1)
 
 #endif /* _CCU_SUN6I_RTC_H */

-- 
2.47.3

Re: [PATCH v2 5/6] clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate.

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but the error path in `sunxi_ccu_probe` unregisters clocks using the wrong loop limit, causing either memory leaks or out-of-bounds array reads depending on the struct array sizes of the specific CCU driver.
--

commit fe4850822f9e2e522aaac703e02ecb786fb47f26
Author: Jerome Brunet <jbrunet@baylibre.com>

clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate.

This commit splits the oscillator divider and gate into two separate clock 
entities to support the A733 SoC. It introduces a new read-only divider 
based on the oscillator rate to replace the fixed 750 divider.

> diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> index b24c8b196e664..25dd87e78eb7a 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c

[ ... ]

> @@ -286,6 +287,7 @@ static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
>  		[CLK_EXT_OSC32K_GATE]	= &ext_osc32k_gate_clk.common.hw,
>  		[CLK_OSC24M_32K]	= &osc24M_32k_clk.common.hw,
>  		[CLK_RTC_32K]		= &rtc_32k_clk.common.hw,
> +		[CLK_OSC24M_32K_DIV]	= &osc24M_32k_div_clk.hw,
>  	},
>  };

[Severity: High]
This isn't a bug introduced by this patch, but does adding an extra clock
here expose an issue in the error handling path of sunxi_ccu_probe()?

In drivers/clk/sunxi-ng/ccu_common.c:sunxi_ccu_probe(), the err_clk_unreg
path unregisters clocks using a loop limit that appears incorrect:

err_clk_unreg:
	while (--i >= 0) {
		struct clk_hw *hw = desc->hw_clks->hws[i];

The variable 'i' incorrectly retains the value of 'desc->num_ccu_clks' from
the preceding loop, rather than using the correct bound 'desc->hw_clks->num'.

For drivers where num_ccu_clks < hw_clks->num (such as sun6i-rtc after this
patch), will this skip unregistering the extra clocks if probe fails? And for
drivers where num_ccu_clks > hw_clks->num, could this read past the end of
the hws array?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629-a733-rtc-v2-0-7b72112784f8@baylibre.com?part=5

Re: [PATCH v2 5/6] clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate.

[Jerome Brunet]

On lun. 29 juin 2026 at 13:12, sashiko-bot@kernel.org wrote:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>
> Pre-existing issues:
> - [High] This problem wasn't introduced by this patch, but the error path
> in `sunxi_ccu_probe` unregisters clocks using the wrong loop limit, causing
> either memory leaks or out-of-bounds array reads depending on the struct
> array sizes of the specific CCU driver.
> --
>
> commit fe4850822f9e2e522aaac703e02ecb786fb47f26
> Author: Jerome Brunet <jbrunet@baylibre.com>
>
> clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate.
>
> This commit splits the oscillator divider and gate into two separate clock 
> entities to support the A733 SoC. It introduces a new read-only divider 
> based on the oscillator rate to replace the fixed 750 divider.
>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
>> index b24c8b196e664..25dd87e78eb7a 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
>
> [ ... ]
>
>> @@ -286,6 +287,7 @@ static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
>>  		[CLK_EXT_OSC32K_GATE]	= &ext_osc32k_gate_clk.common.hw,
>>  		[CLK_OSC24M_32K]	= &osc24M_32k_clk.common.hw,
>>  		[CLK_RTC_32K]		= &rtc_32k_clk.common.hw,
>> +		[CLK_OSC24M_32K_DIV]	= &osc24M_32k_div_clk.hw,
>>  	},
>>  };
>
> [Severity: High]
> This isn't a bug introduced by this patch, but does adding an extra clock
> here expose an issue in the error handling path of sunxi_ccu_probe()?
>
> In drivers/clk/sunxi-ng/ccu_common.c:sunxi_ccu_probe(), the err_clk_unreg
> path unregisters clocks using a loop limit that appears incorrect:
>
> err_clk_unreg:
> 	while (--i >= 0) {
> 		struct clk_hw *hw = desc->hw_clks->hws[i];
>
> The variable 'i' incorrectly retains the value of 'desc->num_ccu_clks' from
> the preceding loop, rather than using the correct bound 'desc->hw_clks->num'.
>
> For drivers where num_ccu_clks < hw_clks->num (such as sun6i-rtc after this
> patch), will this skip unregistering the extra clocks if probe fails? And for
> drivers where num_ccu_clks > hw_clks->num, could this read past the end of
> the hws array?

Good catch, using a different iterator should fix the problem

-- 
Jerome

[PATCH v2 6/6] clk: sunxi-ng: sun6i-rtc: add a733 support

[Jerome Brunet]

Add support for the sun60i a733 CCU RTC.

Compared to the a523, this SoC has a different input oscillator divider
which auto-detects the oscillator rate and select a divider to provide
a fixed 32768Hz clock. It also provides several phy reference clocks
with dedicated clock gates.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 74 ++++++++++++++++++++++++++++++++++--
 drivers/clk/sunxi-ng/ccu-sun6i-rtc.h |  2 +-
 2 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
index 25dd87e78eb7..2ec09e346472 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -42,11 +42,16 @@
 #define LOSC_OUT_GATING_REG		0x60
 
 #define DCXO_CTRL_REG			0x160
+#define DCXO_CTRL_DCXO_EN		BIT(1)
 #define DCXO_CTRL_CLK16M_RC_EN		BIT(0)
 
+#define DCXO_GATING_REG			0x16c
+
 struct sun6i_rtc_match_data {
 	bool				have_ext_osc32k		: 1;
 	bool				have_iosc_calibration	: 1;
+	bool				have_dcxo_status	: 1;
+	bool				have_phy_ref_gates	: 1;
 	bool				rtc_32k_single_parent	: 1;
 	const struct clk_parent_data	*osc32k_fanout_parents;
 	u8				osc32k_fanout_nparents;
@@ -213,7 +218,12 @@ static struct ccu_mux osc32k_clk = {
 	},
 };
 
-/* This falls back to the global name for fwnodes without a named reference. */
+/*
+ * This falls back to the global name for fwnodes without a named reference.
+ * NOTE: osc24M name might be misleading the oscillator could also be a 26MHz
+ * or a 19.2MHz one starting with the a733. The original name is kept anyway
+ * in case anything is relying on it.
+ */
 static const struct clk_parent_data osc24M[] = {
 	{ .fw_name = "hosc", .name = "osc24M" }
 };
@@ -227,8 +237,28 @@ static struct clk_fixed_factor osc24M_32k_div_clk = {
 					    0),
 };
 
-static SUNXI_CCU_GATE_HW(osc24M_32k_clk, "osc24M-32k", &osc24M_32k_div_clk.hw,
-			 LOSC_OUT_GATING_REG, BIT(16), 0);
+static struct clk_div_table osc24M_32k_div_a733_table[] = {
+	{ .val = 0, .div = 732 },
+	{ .val = 1, .div = 586 },
+	{ .val = 2, .div = 793 },
+	{ .val = 3, .div = 732 },
+	{ /* Sentinel */ },
+};
+
+static struct ccu_div osc24M_32k_div_a733_clk = {
+	.enable = BIT(1),
+	.div	= _SUNXI_CCU_DIV_TABLE(14, 2, osc24M_32k_div_a733_table),
+	.common	= {
+		.reg		= DCXO_CTRL_REG,
+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div",
+							   osc24M,
+							   &ccu_rodiv_ops,
+							   0),
+	},
+};
+
+static SUNXI_CCU_GATE(osc24M_32k_clk, "osc24M-32k", "osc24M-32k-div",
+		      LOSC_OUT_GATING_REG, BIT(16), 0);
 
 static const struct clk_hw *rtc_32k_parents[] = {
 	&osc32k_clk.common.hw,
@@ -267,6 +297,15 @@ static struct ccu_mux osc32k_fanout_clk = {
 	},
 };
 
+static SUNXI_CCU_GATE_FW(hosc_serdes1_clk, "hosc-serdes1", "hosc",
+		      DCXO_GATING_REG, BIT(5), 0);
+static SUNXI_CCU_GATE_FW(hosc_serdes0_clk, "hosc-serdes0", "hosc",
+		      DCXO_GATING_REG, BIT(4), 0);
+static SUNXI_CCU_GATE_FW(hosc_hdmi_clk, "hosc-hdmi", "hosc",
+		      DCXO_GATING_REG, BIT(1), 0);
+static SUNXI_CCU_GATE_FW(hosc_ufs_clk, "hosc-ufs", "hosc",
+		      DCXO_GATING_REG, BIT(0), 0);
+
 static struct ccu_common *sun6i_rtc_ccu_clks[] = {
 	&iosc_clk,
 	&iosc_32k_clk,
@@ -275,6 +314,11 @@ static struct ccu_common *sun6i_rtc_ccu_clks[] = {
 	&osc24M_32k_clk.common,
 	&rtc_32k_clk.common,
 	&osc32k_fanout_clk.common,
+	&osc24M_32k_div_a733_clk.common,
+	&hosc_serdes1_clk.common,
+	&hosc_serdes0_clk.common,
+	&hosc_hdmi_clk.common,
+	&hosc_ufs_clk.common,
 };
 
 static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
@@ -288,6 +332,10 @@ static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
 		[CLK_OSC24M_32K]	= &osc24M_32k_clk.common.hw,
 		[CLK_RTC_32K]		= &rtc_32k_clk.common.hw,
 		[CLK_OSC24M_32K_DIV]	= &osc24M_32k_div_clk.hw,
+		[CLK_HOSC_UFS]		= &hosc_ufs_clk.common.hw,
+		[CLK_HOSC_HDMI]		= &hosc_hdmi_clk.common.hw,
+		[CLK_HOSC_SERDES0]	= &hosc_serdes0_clk.common.hw,
+		[CLK_HOSC_SERDES1]	= &hosc_serdes1_clk.common.hw,
 	},
 };
 
@@ -330,6 +378,15 @@ static const struct sun6i_rtc_match_data sun55i_a523_rtc_ccu_data = {
 	.osc32k_fanout_nparents	= ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
 };
 
+static const struct sun6i_rtc_match_data sun60i_a733_rtc_ccu_data = {
+	.have_ext_osc32k	= true,
+	.have_iosc_calibration	= true,
+	.have_dcxo_status	= true,
+	.have_phy_ref_gates	= true,
+	.osc32k_fanout_parents	= sun50i_r329_osc32k_fanout_parents,
+	.osc32k_fanout_nparents	= ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
+};
+
 static const struct of_device_id sun6i_rtc_ccu_match[] = {
 	{
 		.compatible	= "allwinner,sun50i-h616-rtc",
@@ -343,6 +400,10 @@ static const struct of_device_id sun6i_rtc_ccu_match[] = {
 		.compatible	= "allwinner,sun55i-a523-rtc",
 		.data		= &sun55i_a523_rtc_ccu_data,
 	},
+	{
+		.compatible	= "allwinner,sun60i-a733-rtc",
+		.data		= &sun60i_a733_rtc_ccu_data,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match);
@@ -375,6 +436,13 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
 	osc32k_fanout_init_data.parent_data = data->osc32k_fanout_parents;
 	osc32k_fanout_init_data.num_parents = data->osc32k_fanout_nparents;
 
+	if (data->have_dcxo_status)
+		sun6i_rtc_ccu_hw_clks.hws[CLK_OSC24M_32K_DIV] =
+			&osc24M_32k_div_a733_clk.common.hw;
+
+	if (!data->have_phy_ref_gates)
+		sun6i_rtc_ccu_hw_clks.num = CLK_OSC24M_32K_DIV + 1;
+
 	return devm_sunxi_ccu_probe(dev, reg, &sun6i_rtc_ccu_desc);
 }
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
index ab7b92b47f59..4f4f4cb00f1d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
@@ -11,6 +11,6 @@
 #define CLK_RTC_32K		6
 #define CLK_OSC24M_32K_DIV	7
 
-#define CLK_NUMBER		(CLK_OSC24M_32K_DIV + 1)
+#define CLK_NUMBER		(CLK_HOSC_SERDES1 + 1)
 
 #endif /* _CCU_SUN6I_RTC_H */

-- 
2.47.3

Re: [PATCH v2 6/6] clk: sunxi-ng: sun6i-rtc: add a733 support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] The master DCXO enable bit is incorrectly mapped as the exclusive enable bit for the 32kHz divider. This will cause the clock framework to inadvertently turn off the master oscillator, freezing the system.
--

commit 83ebb861eeea7934e5df335b0d1620cad0b733bf
Author: Jerome Brunet <jbrunet@baylibre.com>

clk: sunxi-ng: sun6i-rtc: add a733 support

This commit adds support for the sun60i a733 CCU RTC. It introduces a
new auto-detecting oscillator divider and several phy reference clocks
with dedicated clock gates.

> diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> index 25dd87e78eb7a..2ec09e3464724 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c

[ ... ]

> @@ -227,8 +237,28 @@ static struct clk_fixed_factor osc24M_32k_div_clk = {
>  					    0),
>  };
>  
> -static SUNXI_CCU_GATE_HW(osc24M_32k_clk, "osc24M-32k", &osc24M_32k_div_clk.hw,
> -			 LOSC_OUT_GATING_REG, BIT(16), 0);
> +static struct clk_div_table osc24M_32k_div_a733_table[] = {
> +	{ .val = 0, .div = 732 },
> +	{ .val = 1, .div = 586 },
> +	{ .val = 2, .div = 793 },
> +	{ .val = 3, .div = 732 },
> +	{ /* Sentinel */ },
> +};
> +
> +static struct ccu_div osc24M_32k_div_a733_clk = {
> +	.enable = BIT(1),

[Severity: Critical]
This maps the master DCXO enable bit, BIT(1) defined earlier as
DCXO_CTRL_DCXO_EN, directly to the 32kHz divider's lifecycle.

If a board uses an external 32kHz crystal, the rtc-32k clock mux is
reparented to osc32k_clk, leaving this internal osc24M-32k-div clock with
zero active consumers.

During late boot, the clock framework's clk_disable_unused() routine walks
the clock tree and will disable this clock, clearing BIT(1) in DCXO_CTRL_REG.

Could this cause a hard system freeze? Since this bit physically turns off
the shared master 24MHz crystal (DCXO), does it immediately stop the CPU,
PLLs, and all peripherals?

> +	.div	= _SUNXI_CCU_DIV_TABLE(14, 2, osc24M_32k_div_a733_table),
> +	.common	= {
> +		.reg		= DCXO_CTRL_REG,
> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div",
> +							   osc24M,
> +							   &ccu_rodiv_ops,
> +							   0),
> +	},
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629-a733-rtc-v2-0-7b72112784f8@baylibre.com?part=6

Re: [PATCH v2 6/6] clk: sunxi-ng: sun6i-rtc: add a733 support

[Jerome Brunet]

On lun. 29 juin 2026 at 13:15, sashiko-bot@kernel.org wrote:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Critical] The master DCXO enable bit is incorrectly mapped as the
> exclusive enable bit for the 32kHz divider. This will cause the clock
> framework to inadvertently turn off the master oscillator, freezing the
> system.
> --
>
> commit 83ebb861eeea7934e5df335b0d1620cad0b733bf
> Author: Jerome Brunet <jbrunet@baylibre.com>
>
> clk: sunxi-ng: sun6i-rtc: add a733 support
>
> This commit adds support for the sun60i a733 CCU RTC. It introduces a
> new auto-detecting oscillator divider and several phy reference clocks
> with dedicated clock gates.
>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
>> index 25dd87e78eb7a..2ec09e3464724 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
>
> [ ... ]
>
>> @@ -227,8 +237,28 @@ static struct clk_fixed_factor osc24M_32k_div_clk = {
>>  					    0),
>>  };
>>  
>> -static SUNXI_CCU_GATE_HW(osc24M_32k_clk, "osc24M-32k", &osc24M_32k_div_clk.hw,
>> -			 LOSC_OUT_GATING_REG, BIT(16), 0);
>> +static struct clk_div_table osc24M_32k_div_a733_table[] = {
>> +	{ .val = 0, .div = 732 },
>> +	{ .val = 1, .div = 586 },
>> +	{ .val = 2, .div = 793 },
>> +	{ .val = 3, .div = 732 },
>> +	{ /* Sentinel */ },
>> +};
>> +
>> +static struct ccu_div osc24M_32k_div_a733_clk = {
>> +	.enable = BIT(1),
>
> [Severity: Critical]
> This maps the master DCXO enable bit, BIT(1) defined earlier as
> DCXO_CTRL_DCXO_EN, directly to the 32kHz divider's lifecycle.

Forgot to remove that unused define

>
> If a board uses an external 32kHz crystal, the rtc-32k clock mux is
> reparented to osc32k_clk, leaving this internal osc24M-32k-div clock with
> zero active consumers.
>
> During late boot, the clock framework's clk_disable_unused() routine walks
> the clock tree and will disable this clock, clearing BIT(1) in DCXO_CTRL_REG.
>
> Could this cause a hard system freeze? Since this bit physically turns off
> the shared master 24MHz crystal (DCXO), does it immediately stop the CPU,
> PLLs, and all peripherals?

I don't quite get what the AI is trying to report here. If there are no
user, the clock will be gated ... so ? Am I missing something ?

>
>> +	.div	= _SUNXI_CCU_DIV_TABLE(14, 2, osc24M_32k_div_a733_table),
>> +	.common	= {
>> +		.reg		= DCXO_CTRL_REG,
>> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div",
>> +							   osc24M,
>> +							   &ccu_rodiv_ops,
>> +							   0),
>> +	},
>> +};

-- 
Jerome

Re: [PATCH v2 6/6] clk: sunxi-ng: sun6i-rtc: add a733 support

[Chen-Yu Tsai]

On Mon, Jun 29, 2026 at 10:25 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> On lun. 29 juin 2026 at 13:15, sashiko-bot@kernel.org wrote:
>
> > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> > - [Critical] The master DCXO enable bit is incorrectly mapped as the
> > exclusive enable bit for the 32kHz divider. This will cause the clock
> > framework to inadvertently turn off the master oscillator, freezing the
> > system.
> > --
> >
> > commit 83ebb861eeea7934e5df335b0d1620cad0b733bf
> > Author: Jerome Brunet <jbrunet@baylibre.com>
> >
> > clk: sunxi-ng: sun6i-rtc: add a733 support
> >
> > This commit adds support for the sun60i a733 CCU RTC. It introduces a
> > new auto-detecting oscillator divider and several phy reference clocks
> > with dedicated clock gates.
> >
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> >> index 25dd87e78eb7a..2ec09e3464724 100644
> >> --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> >
> > [ ... ]
> >
> >> @@ -227,8 +237,28 @@ static struct clk_fixed_factor osc24M_32k_div_clk = {
> >>                                          0),
> >>  };
> >>
> >> -static SUNXI_CCU_GATE_HW(osc24M_32k_clk, "osc24M-32k", &osc24M_32k_div_clk.hw,
> >> -                     LOSC_OUT_GATING_REG, BIT(16), 0);
> >> +static struct clk_div_table osc24M_32k_div_a733_table[] = {
> >> +    { .val = 0, .div = 732 },
> >> +    { .val = 1, .div = 586 },
> >> +    { .val = 2, .div = 793 },
> >> +    { .val = 3, .div = 732 },
> >> +    { /* Sentinel */ },
> >> +};
> >> +
> >> +static struct ccu_div osc24M_32k_div_a733_clk = {
> >> +    .enable = BIT(1),
> >
> > [Severity: Critical]
> > This maps the master DCXO enable bit, BIT(1) defined earlier as
> > DCXO_CTRL_DCXO_EN, directly to the 32kHz divider's lifecycle.
>
> Forgot to remove that unused define
>
> >
> > If a board uses an external 32kHz crystal, the rtc-32k clock mux is
> > reparented to osc32k_clk, leaving this internal osc24M-32k-div clock with
> > zero active consumers.
> >
> > During late boot, the clock framework's clk_disable_unused() routine walks
> > the clock tree and will disable this clock, clearing BIT(1) in DCXO_CTRL_REG.
> >
> > Could this cause a hard system freeze? Since this bit physically turns off
> > the shared master 24MHz crystal (DCXO), does it immediately stop the CPU,
> > PLLs, and all peripherals?
>
> I don't quite get what the AI is trying to report here. If there are no
> user, the clock will be gated ... so ? Am I missing something ?

I think it's just getting confused. Since you said it was unused and you
plan to remove it, I would just ignore the AI.


ChenYu

> >
> >> +    .div    = _SUNXI_CCU_DIV_TABLE(14, 2, osc24M_32k_div_a733_table),
> >> +    .common = {
> >> +            .reg            = DCXO_CTRL_REG,
> >> +            .hw.init        = CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div",
> >> +                                                       osc24M,
> >> +                                                       &ccu_rodiv_ops,
> >> +                                                       0),
> >> +    },
> >> +};
>
> --
> Jerome
>