[PATCH] sunxi: dram: only probe DRAM inside the addressable range

[PATCH] sunxi: dram: only probe DRAM inside the addressable range

[Jernej Skrabec]

The non-power-of-2 size check probes the memory cell at 3/4 of the
detected size. On SoCs whose DRAM window is smaller than the detected
size, like H6 with 4 GiB chips and a 3 GiB window, that address lies
outside the window and the access hangs the SPL. Such boards cannot be
odd-sized anyway, since the usable size is capped to the window later,
so only run the check when the probed address is addressable.

Fixes: c47b63673736 ("sunxi: dram: detect non-power-of-2 sized DRAM chips")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 arch/arm/mach-sunxi/dram_dw_helpers.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c
index d2af2d57fded..ae13dd154536 100644
--- a/arch/arm/mach-sunxi/dram_dw_helpers.c
+++ b/arch/arm/mach-sunxi/dram_dw_helpers.c
@@ -155,7 +155,8 @@ unsigned long mctl_calc_size(const struct dram_config *config)
 	 * or 3GB. They are detected as the larger power-of-2 (2GB and 4GB),
 	 * so test the last quarter for being able to store values.
 	 */
-	if (!mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3)) {
+	if (size / 4 * 3 < CONFIG_SUNXI_DRAM_MAX_SIZE &&
+	    !mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3)) {
 		if (mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64)) {
 			size = (size / 4) * 3;
 			debug("capping memory at %ld MB\n", size >> 20);
-- 
2.56.0

Re: [PATCH] sunxi: dram: only probe DRAM inside the addressable range

[Andre Przywara]

On Mon, 26 Oct 2026 18:32:35 +0100
Jernej Skrabec <jernej.skrabec@gmail.com> wrote:

Hi Jernej,

> The non-power-of-2 size check probes the memory cell at 3/4 of the
> detected size. On SoCs whose DRAM window is smaller than the detected
> size, like H6 with 4 GiB chips and a 3 GiB window, that address lies
> outside the window and the access hangs the SPL. Such boards cannot be
> odd-sized anyway, since the usable size is capped to the window later,
> so only run the check when the probed address is addressable.

Many thanks for the heads up, and the fix!
I can confirm that it's indeed a problem, and that the change fixes it:
tested on a 3GB Eachlink H6 Mini box.
I added one line to the comment above, to give some clue about the
reason for that added line (beyond just the commit message).

> Fixes: c47b63673736 ("sunxi: dram: detect non-power-of-2 sized DRAM chips")

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Queued for 2027.01.

Cheers,
Andre

> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> ---
>  arch/arm/mach-sunxi/dram_dw_helpers.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c
> index d2af2d57fded..ae13dd154536 100644
> --- a/arch/arm/mach-sunxi/dram_dw_helpers.c
> +++ b/arch/arm/mach-sunxi/dram_dw_helpers.c
> @@ -155,7 +155,8 @@ unsigned long mctl_calc_size(const struct dram_config *config)
>  	 * or 3GB. They are detected as the larger power-of-2 (2GB and 4GB),
>  	 * so test the last quarter for being able to store values.
>  	 */
> -	if (!mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3)) {
> +	if (size / 4 * 3 < CONFIG_SUNXI_DRAM_MAX_SIZE &&
> +	    !mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3)) {
>  		if (mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64)) {
>  			size = (size / 4) * 3;
>  			debug("capping memory at %ld MB\n", size >> 20);