From: Quentin Schulz <quentin.schulz@cherry.de>
To: Andre Przywara <andre.przywara@arm.com>
Cc: u-boot@lists.denx.de, Jagan Teki <jagan@amarulasolutions.com>,
Cody Eksal <masterr3c0rd@epochal.quest>,
Philippe Simons <simons.philippe@gmail.com>,
Sumit Garg <sumit.garg@kernel.org>,
linux-sunxi@lists.linux.dev, Tom Rini <trini@konsulko.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>
Subject: Re: [PATCH v2 3/6] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
Date: Mon, 12 May 2025 17:58:32 +0200 [thread overview]
Message-ID: <7ccf1122-c110-44d7-abfc-0d8b136fff3f@cherry.de> (raw)
In-Reply-To: <20250512114645.60bff4cb@donnerap.manchester.arm.com>
Hi Andre,
On 5/12/25 12:46 PM, Andre Przywara wrote:
> On Mon, 12 May 2025 11:24:07 +0200
> Quentin Schulz <quentin.schulz@cherry.de> wrote:
>
>> Hi Andre,
>>
>> On 5/11/25 3:10 AM, Andre Przywara wrote:
>>> Add an Operating Performance Points table for the CPU cores to
>>> enable Dynamic Voltage & Frequency Scaling on the A100.
>>>
>>> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>>> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
>>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>>> Link: https://patch.msgid.link/20241031070232.1793078-14-masterr3c0rd@epochal.quest
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>>
>>> [ upstream commit: a8181e6861fec3068f393d77ff81b2aaf4ea4203 ]
>>
>> Did you use tools/update-subtree.sh to cherry-pick those commits? The
>
> No, I didn't, just remembered that afterwards. This would only work for
> this patch anyways, since the other two DT patches are not yet merged in a
> tagged release (the last one isn't even reviewed yet), so I just added them
> here for completeness, to give people an idea of how the defconfig would
> look like and to allow compile testing.
>
Considering you're the sunxi maintainer, I assume you wouldn't merge the
patches knowing that they are not fitting the expected workflow so I'm
not too worried :)
> The plan was to maybe merge the first two patches (the DRAM code and
> Kconfig bits), then wait for the DT bits to trickle in.
>
Sounds like a plan! Have fun :)
Cheers,
Quentin
next prev parent reply other threads:[~2025-05-12 15:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-11 1:09 [PATCH v2 0/6] sunxi: Allwinner A133 SoC support Andre Przywara
2025-05-11 1:09 ` [PATCH v2 1/6] sunxi: A133: add DRAM init code Andre Przywara
2025-05-11 9:23 ` Andre Przywara
2025-05-12 9:21 ` Quentin Schulz
2025-05-12 10:49 ` Andre Przywara
2025-05-12 15:12 ` Cody Eksal
2025-05-26 13:45 ` Parthiban
2025-05-11 1:09 ` [PATCH v2 2/6] sunxi: add support for the Allwinner A100/A133 SoC Andre Przywara
2025-05-11 1:10 ` [PATCH v2 3/6] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table Andre Przywara
2025-05-12 9:24 ` Quentin Schulz
2025-05-12 10:46 ` Andre Przywara
2025-05-12 15:58 ` Quentin Schulz [this message]
2025-05-11 1:10 ` [PATCH v2 4/6] arm64: dts: allwinner: a100: set maximum MMC frequency Andre Przywara
2025-05-11 1:10 ` [PATCH v2 5/6] arm64: dts: allwinner: a100: add Liontron H-A133L board support Andre Przywara
2025-05-11 1:10 ` [PATCH v2 6/6] sunxi: add support for Liontron H-A133L board Andre Przywara
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