[PATCH v6 0/4] Multiplex sdmmc low jitter clock path

[PATCH v6 0/4] Multiplex sdmmc low jitter clock path

[Aapo Vienamo]

The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a
divider to achieve better jitter performance with high speed signaling
modes. The clock path with the divider is needed by some of the slower
signaling modes. This series automatically multiplexes the LJ and
non-LJ clock paths based on the requested frequency.

Changelog:
v6:
	- Rename div-frac.c to clk-utils.c
	- Fix checkpatch errors and warnings introduced in v5
	- Replace int mul = 2 with a macro in clk-sdmmc-mux.c
	- Remove unnecessary space from clk_sdmmc_mux_enable() return
	- Free sdmmc_mux if clk_register() fails in
	  tegra_clk_register_sdmmc_mux_div()

v5:
	- Rename div71_get() to div_frac_get()
	- Rename div71.c to div-frac.c

v4:
	- Add a changelog

v3:
	- Use <asm/div64.h> include instead of <linux/kernel.h> for
	  do_div()
	- Use SPDX tags for new files
	- Make mux_lj_idx[] and mux_non_lj_idx[] const
	- Make tegra_clk_sdmmc_mux_ops static
	- Fix the includes for fence_udelay() in a separate patch

v2:
	- Fix the type compatibility error on do_div

Aapo Vienamo (1):
  clk: tegra: Fix includes required by fence_udelay()

Peter De Schrijver (1):
  clk: tegra: Refactor fractional divider calculation

Peter De-Schrijver (2):
  clk: tegra: Add sdmmc mux divider clock
  clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

 drivers/clk/tegra/Makefile           |   2 +
 drivers/clk/tegra/clk-divider.c      |  30 +----
 drivers/clk/tegra/clk-id.h           |   2 -
 drivers/clk/tegra/clk-sdmmc-mux.c    | 251 +++++++++++++++++++++++++++++++++++
 drivers/clk/tegra/clk-tegra-periph.c |  11 --
 drivers/clk/tegra/clk-tegra210.c     |  14 +-
 drivers/clk/tegra/clk-utils.c        |  43 ++++++
 drivers/clk/tegra/clk.h              |  30 +++++
 8 files changed, 343 insertions(+), 40 deletions(-)
 create mode 100644 drivers/clk/tegra/clk-sdmmc-mux.c
 create mode 100644 drivers/clk/tegra/clk-utils.c

-- 
2.7.4

[PATCH v6 1/4] clk: tegra: Fix includes required by fence_udelay()

[Aapo Vienamo]

Add the missing linux/delay.h include statement for udelay() used by
fence_udelay() macro.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/clk/tegra/clk.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e1f8846..e3b9c22 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -19,6 +19,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
+#include <linux/delay.h>
 
 /**
  * struct tegra_clk_sync_source - external clock source from codec
-- 
2.7.4

Re: [PATCH v6 1/4] clk: tegra: Fix includes required by fence_udelay()

[Stephen Boyd]

Quoting Aapo Vienamo (2018-07-12 04:52:59)
> Add the missing linux/delay.h include statement for udelay() used by
> fence_udelay() macro.
> 
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
> ---

Applied to clk-next

[PATCH v6 2/4] clk: tegra: Refactor fractional divider calculation

[Aapo Vienamo]

From: Peter De Schrijver <pdeschrijver@nvidia.com>

Move this to a separate file so it can be used to calculate the sdmmc
clock dividers.

Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/clk/tegra/Makefile      |  1 +
 drivers/clk/tegra/clk-divider.c | 30 +++++-----------------------
 drivers/clk/tegra/clk-utils.c   | 43 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/tegra/clk.h         |  3 +++
 4 files changed, 52 insertions(+), 25 deletions(-)
 create mode 100644 drivers/clk/tegra/clk-utils.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index b716923..c77d072 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
 obj-y					+= cvb.o
 obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
 obj-$(CONFIG_CLK_TEGRA_BPMP)		+= clk-bpmp.o
+obj-y					+= clk-utils.o
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 16e0aee..8f175ff 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -32,35 +32,15 @@
 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
 		   unsigned long parent_rate)
 {
-	u64 divider_ux1 = parent_rate;
-	u8 flags = divider->flags;
-	int mul;
-
-	if (!rate)
-		return 0;
-
-	mul = get_mul(divider);
-
-	if (!(flags & TEGRA_DIVIDER_INT))
-		divider_ux1 *= mul;
-
-	if (flags & TEGRA_DIVIDER_ROUND_UP)
-		divider_ux1 += rate - 1;
-
-	do_div(divider_ux1, rate);
-
-	if (flags & TEGRA_DIVIDER_INT)
-		divider_ux1 *= mul;
+	int div;
 
-	divider_ux1 -= mul;
+	div = div_frac_get(rate, parent_rate, divider->width,
+			   divider->frac_width, divider->flags);
 
-	if ((s64)divider_ux1 < 0)
+	if (div < 0)
 		return 0;
 
-	if (divider_ux1 > get_max_div(divider))
-		return get_max_div(divider);
-
-	return divider_ux1;
+	return div;
 }
 
 static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
diff --git a/drivers/clk/tegra/clk-utils.c b/drivers/clk/tegra/clk-utils.c
new file mode 100644
index 0000000..1a5daae
--- /dev/null
+++ b/drivers/clk/tegra/clk-utils.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#include <asm/div64.h>
+
+#include "clk.h"
+
+#define div_mask(w) ((1 << (w)) - 1)
+
+int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
+		 u8 frac_width, u8 flags)
+{
+	u64 divider_ux1 = parent_rate;
+	int mul;
+
+	if (!rate)
+		return 0;
+
+	mul = 1 << frac_width;
+
+	if (!(flags & TEGRA_DIVIDER_INT))
+		divider_ux1 *= mul;
+
+	if (flags & TEGRA_DIVIDER_ROUND_UP)
+		divider_ux1 += rate - 1;
+
+	do_div(divider_ux1, rate);
+
+	if (flags & TEGRA_DIVIDER_INT)
+		divider_ux1 *= mul;
+
+	if (divider_ux1 < mul)
+		return 0;
+
+	divider_ux1 -= mul;
+
+	if (divider_ux1 > div_mask(width))
+		return div_mask(width);
+
+	return divider_ux1;
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e3b9c22..c733841 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
+int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
+		 u8 frac_width, u8 flags);
+
 
 /* Combined read fence with delay */
 #define fence_udelay(delay, reg)	\
-- 
2.7.4

Re: [PATCH v6 2/4] clk: tegra: Refactor fractional divider calculation

[Stephen Boyd]

Quoting Aapo Vienamo (2018-07-12 04:53:00)
> From: Peter De Schrijver <pdeschrijver@nvidia.com>
> 
> Move this to a separate file so it can be used to calculate the sdmmc
> clock dividers.
> 
> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
> ---

Applied to clk-next

[PATCH v6 3/4] clk: tegra: Add sdmmc mux divider clock

[Aapo Vienamo]

From: Peter De-Schrijver <pdeschrijver@nvidia.com>

Add a clock type to model the sdmmc switch divider clocks which have paths
to source clocks bypassing the divider (Low Jitter paths). These
are handled by selecting the lj path when the divider is 1 (ie the
rate is the parent rate), otherwise the normal path with divider
will be selected. Otherwise this clock behaves as a normal peripheral
clock.

Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/Makefile        |   1 +
 drivers/clk/tegra/clk-sdmmc-mux.c | 251 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/tegra/clk.h           |  26 ++++
 3 files changed, 278 insertions(+)
 create mode 100644 drivers/clk/tegra/clk-sdmmc-mux.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index c77d072..6507acc 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -8,6 +8,7 @@ obj-y					+= clk-periph-fixed.o
 obj-y					+= clk-periph-gate.o
 obj-y					+= clk-pll.o
 obj-y					+= clk-pll-out.o
+obj-y					+= clk-sdmmc-mux.o
 obj-y					+= clk-super.o
 obj-y					+= clk-tegra-audio.o
 obj-y					+= clk-tegra-periph.o
diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c
new file mode 100644
index 0000000..473d418
--- /dev/null
+++ b/drivers/clk/tegra/clk-sdmmc-mux.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * based on clk-mux.c
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/types.h>
+
+#include "clk.h"
+
+#define DIV_MASK GENMASK(7, 0)
+#define MUX_SHIFT 29
+#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)
+#define SDMMC_MUL 2
+
+#define get_max_div(d) DIV_MASK
+#define get_div_field(val) ((val) & DIV_MASK)
+#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT)
+
+static const char * const mux_sdmmc_parents[] = {
+	"pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
+};
+
+static const u8 mux_lj_idx[] = {
+	[0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6
+};
+
+static const u8 mux_non_lj_idx[] = {
+	[0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6
+};
+
+static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	int num_parents, i;
+	u32 src, val;
+	const u8 *mux_idx;
+
+	num_parents = clk_hw_get_num_parents(hw);
+
+	val = readl_relaxed(sdmmc_mux->reg);
+	src = get_mux_field(val);
+	if (get_div_field(val))
+		mux_idx = mux_non_lj_idx;
+	else
+		mux_idx = mux_lj_idx;
+
+	for (i = 0; i < num_parents; i++) {
+		if (mux_idx[i] == src)
+			return i;
+	}
+
+	WARN(1, "Unknown parent selector %d\n", src);
+
+	return 0;
+}
+
+static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	u32 val;
+
+
+	val = readl_relaxed(sdmmc_mux->reg);
+	if (get_div_field(val))
+		index = mux_non_lj_idx[index];
+	else
+		index = mux_lj_idx[index];
+
+	val &= ~MUX_MASK;
+	val |= index << MUX_SHIFT;
+
+	writel(val, sdmmc_mux->reg);
+
+	return 0;
+}
+
+static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw,
+					       unsigned long parent_rate)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	u32 val;
+	int div;
+	u64 rate = parent_rate;
+
+	val = readl_relaxed(sdmmc_mux->reg);
+	div = get_div_field(val);
+
+	div += SDMMC_MUL;
+
+	rate *= SDMMC_MUL;
+	rate += div - 1;
+	do_div(rate, div);
+
+	return rate;
+}
+
+static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw,
+					struct clk_rate_request *req)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	int div;
+	unsigned long output_rate = req->best_parent_rate;
+
+	req->rate = max(req->rate, req->min_rate);
+	req->rate = min(req->rate, req->max_rate);
+
+	if (!req->rate)
+		return output_rate;
+
+	div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags);
+	if (div < 0)
+		div = 0;
+
+	if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)
+		req->rate =  DIV_ROUND_UP(output_rate * SDMMC_MUL,
+					  div + SDMMC_MUL);
+	else
+		req->rate =  output_rate * SDMMC_MUL / (div + SDMMC_MUL);
+
+	return 0;
+}
+
+static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate,
+				  unsigned long parent_rate)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	int div;
+	unsigned long flags = 0;
+	u32 val;
+	u8 src;
+
+	div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags);
+	if (div < 0)
+		return div;
+
+	if (sdmmc_mux->lock)
+		spin_lock_irqsave(sdmmc_mux->lock, flags);
+
+	src = clk_sdmmc_mux_get_parent(hw);
+	if (div)
+		src = mux_non_lj_idx[src];
+	else
+		src = mux_lj_idx[src];
+
+	val = src << MUX_SHIFT;
+	val |= div;
+	writel(val, sdmmc_mux->reg);
+	fence_udelay(2, sdmmc_mux->reg);
+
+	if (sdmmc_mux->lock)
+		spin_unlock_irqrestore(sdmmc_mux->lock, flags);
+
+	return 0;
+}
+
+static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
+	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
+
+	__clk_hw_set_clk(gate_hw, hw);
+
+	return gate_ops->is_enabled(gate_hw);
+}
+
+static int clk_sdmmc_mux_enable(struct clk_hw *hw)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
+	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
+
+	__clk_hw_set_clk(gate_hw, hw);
+
+	return gate_ops->enable(gate_hw);
+}
+
+static void clk_sdmmc_mux_disable(struct clk_hw *hw)
+{
+	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
+	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
+
+	gate_ops->disable(gate_hw);
+}
+
+static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
+	.get_parent = clk_sdmmc_mux_get_parent,
+	.set_parent = clk_sdmmc_mux_set_parent,
+	.determine_rate = clk_sdmmc_mux_determine_rate,
+	.recalc_rate = clk_sdmmc_mux_recalc_rate,
+	.set_rate = clk_sdmmc_mux_set_rate,
+	.is_enabled = clk_sdmmc_mux_is_enabled,
+	.enable = clk_sdmmc_mux_enable,
+	.disable = clk_sdmmc_mux_disable,
+};
+
+struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
+	void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
+	unsigned long flags, void *lock)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	const struct tegra_clk_periph_regs *bank;
+	struct tegra_sdmmc_mux *sdmmc_mux;
+
+	init.ops = &tegra_clk_sdmmc_mux_ops;
+	init.name = name;
+	init.flags = flags;
+	init.parent_names = mux_sdmmc_parents;
+	init.num_parents = ARRAY_SIZE(mux_sdmmc_parents);
+
+	bank = get_reg_bank(clk_num);
+	if (!bank)
+		return ERR_PTR(-EINVAL);
+
+	sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL);
+	if (!sdmmc_mux)
+		return ERR_PTR(-ENOMEM);
+
+	/* Data in .init is copied by clk_register(), so stack variable OK */
+	sdmmc_mux->hw.init = &init;
+	sdmmc_mux->reg = clk_base + offset;
+	sdmmc_mux->lock = lock;
+	sdmmc_mux->gate.clk_base = clk_base;
+	sdmmc_mux->gate.regs = bank;
+	sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt;
+	sdmmc_mux->gate.clk_num = clk_num;
+	sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB;
+	sdmmc_mux->div_flags = div_flags;
+	sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops;
+
+	clk = clk_register(NULL, &sdmmc_mux->hw);
+	if (IS_ERR(clk)) {
+		kfree(sdmmc_mux);
+		return clk;
+	}
+
+	sdmmc_mux->gate.hw.clk = clk;
+
+	return clk;
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index c733841..d2c3a01 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -706,6 +706,32 @@ struct clk *tegra_clk_register_super_clk(const char *name,
 		const char * const *parent_names, u8 num_parents,
 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 		spinlock_t *lock);
+
+/**
+ * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register controlling mux and divider
+ * @flags:	hardware-specific flags
+ * @lock:	optional register lock
+ * @gate:	gate clock
+ * @gate_ops:	gate clock ops
+ */
+struct tegra_sdmmc_mux {
+	struct clk_hw		hw;
+	void __iomem		*reg;
+	spinlock_t		*lock;
+	const struct clk_ops	*gate_ops;
+	struct tegra_clk_periph_gate	gate;
+	u8			div_flags;
+};
+
+#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
+
+struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
+		void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
+		unsigned long flags, void *lock);
+
 /**
  * struct clk_init_table - clock initialization table
  * @clk_id:	clock id as mentioned in device tree bindings
-- 
2.7.4

Re: [PATCH v6 3/4] clk: tegra: Add sdmmc mux divider clock

[Jon Hunter]

On 12/07/18 12:53, Aapo Vienamo wrote:
> From: Peter De-Schrijver <pdeschrijver@nvidia.com>
> 
> Add a clock type to model the sdmmc switch divider clocks which have paths
> to source clocks bypassing the divider (Low Jitter paths). These
> are handled by selecting the lj path when the divider is 1 (ie the
> rate is the parent rate), otherwise the normal path with divider
> will be selected. Otherwise this clock behaves as a normal peripheral
> clock.
> 
> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/Makefile        |   1 +
>  drivers/clk/tegra/clk-sdmmc-mux.c | 251 ++++++++++++++++++++++++++++++++++++++
>  drivers/clk/tegra/clk.h           |  26 ++++
>  3 files changed, 278 insertions(+)
>  create mode 100644 drivers/clk/tegra/clk-sdmmc-mux.c
> 
> diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> index c77d072..6507acc 100644
> --- a/drivers/clk/tegra/Makefile
> +++ b/drivers/clk/tegra/Makefile
> @@ -8,6 +8,7 @@ obj-y					+= clk-periph-fixed.o
>  obj-y					+= clk-periph-gate.o
>  obj-y					+= clk-pll.o
>  obj-y					+= clk-pll-out.o
> +obj-y					+= clk-sdmmc-mux.o
>  obj-y					+= clk-super.o
>  obj-y					+= clk-tegra-audio.o
>  obj-y					+= clk-tegra-periph.o
> diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c
> new file mode 100644
> index 0000000..473d418
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-sdmmc-mux.c
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 NVIDIA CORPORATION.  All rights reserved.
> + *
> + * based on clk-mux.c
> + *
> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/types.h>
> +
> +#include "clk.h"
> +
> +#define DIV_MASK GENMASK(7, 0)
> +#define MUX_SHIFT 29
> +#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)
> +#define SDMMC_MUL 2
> +
> +#define get_max_div(d) DIV_MASK
> +#define get_div_field(val) ((val) & DIV_MASK)
> +#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT)
> +
> +static const char * const mux_sdmmc_parents[] = {
> +	"pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
> +};
> +
> +static const u8 mux_lj_idx[] = {
> +	[0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6
> +};
> +
> +static const u8 mux_non_lj_idx[] = {
> +	[0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6
> +};
> +
> +static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	int num_parents, i;
> +	u32 src, val;
> +	const u8 *mux_idx;
> +
> +	num_parents = clk_hw_get_num_parents(hw);
> +
> +	val = readl_relaxed(sdmmc_mux->reg);
> +	src = get_mux_field(val);
> +	if (get_div_field(val))
> +		mux_idx = mux_non_lj_idx;
> +	else
> +		mux_idx = mux_lj_idx;
> +
> +	for (i = 0; i < num_parents; i++) {
> +		if (mux_idx[i] == src)
> +			return i;
> +	}
> +
> +	WARN(1, "Unknown parent selector %d\n", src);
> +
> +	return 0;
> +}
> +
> +static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	u32 val;
> +
> +
> +	val = readl_relaxed(sdmmc_mux->reg);
> +	if (get_div_field(val))
> +		index = mux_non_lj_idx[index];
> +	else
> +		index = mux_lj_idx[index];
> +
> +	val &= ~MUX_MASK;
> +	val |= index << MUX_SHIFT;
> +
> +	writel(val, sdmmc_mux->reg);
> +
> +	return 0;
> +}
> +
> +static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw,
> +					       unsigned long parent_rate)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	u32 val;
> +	int div;
> +	u64 rate = parent_rate;
> +
> +	val = readl_relaxed(sdmmc_mux->reg);
> +	div = get_div_field(val);
> +
> +	div += SDMMC_MUL;
> +
> +	rate *= SDMMC_MUL;
> +	rate += div - 1;
> +	do_div(rate, div);
> +
> +	return rate;
> +}
> +
> +static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw,
> +					struct clk_rate_request *req)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	int div;
> +	unsigned long output_rate = req->best_parent_rate;
> +
> +	req->rate = max(req->rate, req->min_rate);
> +	req->rate = min(req->rate, req->max_rate);
> +
> +	if (!req->rate)
> +		return output_rate;
> +
> +	div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags);
> +	if (div < 0)
> +		div = 0;
> +
> +	if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)
> +		req->rate =  DIV_ROUND_UP(output_rate * SDMMC_MUL,
> +					  div + SDMMC_MUL);
> +	else
> +		req->rate =  output_rate * SDMMC_MUL / (div + SDMMC_MUL);
> +
> +	return 0;
> +}
> +
> +static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate,
> +				  unsigned long parent_rate)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	int div;
> +	unsigned long flags = 0;
> +	u32 val;
> +	u8 src;
> +
> +	div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags);
> +	if (div < 0)
> +		return div;
> +
> +	if (sdmmc_mux->lock)
> +		spin_lock_irqsave(sdmmc_mux->lock, flags);
> +
> +	src = clk_sdmmc_mux_get_parent(hw);
> +	if (div)
> +		src = mux_non_lj_idx[src];
> +	else
> +		src = mux_lj_idx[src];
> +
> +	val = src << MUX_SHIFT;
> +	val |= div;
> +	writel(val, sdmmc_mux->reg);
> +	fence_udelay(2, sdmmc_mux->reg);
> +
> +	if (sdmmc_mux->lock)
> +		spin_unlock_irqrestore(sdmmc_mux->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
> +	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
> +
> +	__clk_hw_set_clk(gate_hw, hw);
> +
> +	return gate_ops->is_enabled(gate_hw);
> +}
> +
> +static int clk_sdmmc_mux_enable(struct clk_hw *hw)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
> +	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
> +
> +	__clk_hw_set_clk(gate_hw, hw);
> +
> +	return gate_ops->enable(gate_hw);
> +}
> +
> +static void clk_sdmmc_mux_disable(struct clk_hw *hw)
> +{
> +	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> +	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
> +	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
> +
> +	gate_ops->disable(gate_hw);
> +}
> +
> +static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
> +	.get_parent = clk_sdmmc_mux_get_parent,
> +	.set_parent = clk_sdmmc_mux_set_parent,
> +	.determine_rate = clk_sdmmc_mux_determine_rate,
> +	.recalc_rate = clk_sdmmc_mux_recalc_rate,
> +	.set_rate = clk_sdmmc_mux_set_rate,
> +	.is_enabled = clk_sdmmc_mux_is_enabled,
> +	.enable = clk_sdmmc_mux_enable,
> +	.disable = clk_sdmmc_mux_disable,
> +};
> +
> +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
> +	void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
> +	unsigned long flags, void *lock)
> +{
> +	struct clk *clk;
> +	struct clk_init_data init;
> +	const struct tegra_clk_periph_regs *bank;
> +	struct tegra_sdmmc_mux *sdmmc_mux;
> +
> +	init.ops = &tegra_clk_sdmmc_mux_ops;
> +	init.name = name;
> +	init.flags = flags;
> +	init.parent_names = mux_sdmmc_parents;
> +	init.num_parents = ARRAY_SIZE(mux_sdmmc_parents);
> +
> +	bank = get_reg_bank(clk_num);
> +	if (!bank)
> +		return ERR_PTR(-EINVAL);
> +
> +	sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL);
> +	if (!sdmmc_mux)
> +		return ERR_PTR(-ENOMEM);
> +
> +	/* Data in .init is copied by clk_register(), so stack variable OK */
> +	sdmmc_mux->hw.init = &init;
> +	sdmmc_mux->reg = clk_base + offset;
> +	sdmmc_mux->lock = lock;
> +	sdmmc_mux->gate.clk_base = clk_base;
> +	sdmmc_mux->gate.regs = bank;
> +	sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt;
> +	sdmmc_mux->gate.clk_num = clk_num;
> +	sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB;
> +	sdmmc_mux->div_flags = div_flags;
> +	sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops;
> +
> +	clk = clk_register(NULL, &sdmmc_mux->hw);
> +	if (IS_ERR(clk)) {
> +		kfree(sdmmc_mux);
> +		return clk;
> +	}
> +
> +	sdmmc_mux->gate.hw.clk = clk;
> +
> +	return clk;
> +}
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index c733841..d2c3a01 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -706,6 +706,32 @@ struct clk *tegra_clk_register_super_clk(const char *name,
>  		const char * const *parent_names, u8 num_parents,
>  		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
>  		spinlock_t *lock);
> +
> +/**
> + * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
> + *
> + * @hw:		handle between common and hardware-specific interfaces
> + * @reg:	register controlling mux and divider
> + * @flags:	hardware-specific flags
> + * @lock:	optional register lock
> + * @gate:	gate clock
> + * @gate_ops:	gate clock ops
> + */
> +struct tegra_sdmmc_mux {
> +	struct clk_hw		hw;
> +	void __iomem		*reg;
> +	spinlock_t		*lock;
> +	const struct clk_ops	*gate_ops;
> +	struct tegra_clk_periph_gate	gate;
> +	u8			div_flags;
> +};
> +
> +#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
> +
> +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
> +		void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
> +		unsigned long flags, void *lock);
> +
>  /**
>   * struct clk_init_table - clock initialization table
>   * @clk_id:	clock id as mentioned in device tree bindings

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers!
Jon

-- 
nvpublic

Re: [PATCH v6 3/4] clk: tegra: Add sdmmc mux divider clock

[Stephen Boyd]

Quoting Aapo Vienamo (2018-07-12 04:53:01)
> From: Peter De-Schrijver <pdeschrijver@nvidia.com>
> 
> Add a clock type to model the sdmmc switch divider clocks which have paths
> to source clocks bypassing the divider (Low Jitter paths). These
> are handled by selecting the lj path when the divider is 1 (ie the
> rate is the parent rate), otherwise the normal path with divider
> will be selected. Otherwise this clock behaves as a normal peripheral
> clock.
> 
> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---

Applied to clk-next

[PATCH v6 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

[Aapo Vienamo]

From: Peter De-Schrijver <pdeschrijver@nvidia.com>

These clocks have low jitter paths to certain parents. To model these
correctly, use the sdmmc mux divider clock type.

Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-id.h           |  2 --
 drivers/clk/tegra/clk-tegra-periph.c | 11 -----------
 drivers/clk/tegra/clk-tegra210.c     | 14 ++++++++++++--
 3 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index b616e33..de466b4 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -227,13 +227,11 @@ enum clk_id {
 	tegra_clk_sdmmc1_9,
 	tegra_clk_sdmmc2,
 	tegra_clk_sdmmc2_8,
-	tegra_clk_sdmmc2_9,
 	tegra_clk_sdmmc3,
 	tegra_clk_sdmmc3_8,
 	tegra_clk_sdmmc3_9,
 	tegra_clk_sdmmc4,
 	tegra_clk_sdmmc4_8,
-	tegra_clk_sdmmc4_9,
 	tegra_clk_se,
 	tegra_clk_soc_therm,
 	tegra_clk_soc_therm_8,
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 2acba29..38c4eb2 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -451,15 +451,6 @@ static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
 	[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
 };
 
-static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
-	"pll_p",
-	"pll_c4_out2", "pll_c4_out0",	/* LJ input */
-	"pll_c4_out2", "pll_c4_out1",
-	"pll_c4_out1",			/* LJ input */
-	"clk_m", "pll_c4_out0"
-};
-#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
-
 static const char *mux_pllp_pllc2_c_c3_clkm[] = {
 	"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
 };
@@ -686,9 +677,7 @@ static struct tegra_periph_init_data periph_clks[] = {
 	MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
 	MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
 	MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
-	MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
 	MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
-	MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
 	MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
 	MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
 	MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 5435d01..9eb1cb1 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -44,6 +44,8 @@
 #define CLK_SOURCE_EMC 0x19c
 #define CLK_SOURCE_SOR1 0x410
 #define CLK_SOURCE_LA 0x1f8
+#define CLK_SOURCE_SDMMC2 0x154
+#define CLK_SOURCE_SDMMC4 0x164
 
 #define PLLC_BASE 0x80
 #define PLLC_OUT 0x84
@@ -2286,11 +2288,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
 	[tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
 	[tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
-	[tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
 	[tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
 	[tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
 	[tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
-	[tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
 	[tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
 	[tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
 	[tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
@@ -3030,6 +3030,16 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
 				0, NULL);
 	clks[TEGRA210_CLK_ACLK] = clk;
 
+	clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
+					    CLK_SOURCE_SDMMC2, 9,
+					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
+	clks[TEGRA210_CLK_SDMMC2] = clk;
+
+	clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
+					    CLK_SOURCE_SDMMC4, 15,
+					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
+	clks[TEGRA210_CLK_SDMMC4] = clk;
+
 	for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
 		struct tegra_periph_init_data *init = &tegra210_periph[i];
 		struct clk **clkp;
-- 
2.7.4

Re: [PATCH v6 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

[Jon Hunter]

On 12/07/18 12:53, Aapo Vienamo wrote:
> From: Peter De-Schrijver <pdeschrijver@nvidia.com>
> 
> These clocks have low jitter paths to certain parents. To model these
> correctly, use the sdmmc mux divider clock type.
> 
> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk-id.h           |  2 --
>  drivers/clk/tegra/clk-tegra-periph.c | 11 -----------
>  drivers/clk/tegra/clk-tegra210.c     | 14 ++++++++++++--
>  3 files changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
> index b616e33..de466b4 100644
> --- a/drivers/clk/tegra/clk-id.h
> +++ b/drivers/clk/tegra/clk-id.h
> @@ -227,13 +227,11 @@ enum clk_id {
>  	tegra_clk_sdmmc1_9,
>  	tegra_clk_sdmmc2,
>  	tegra_clk_sdmmc2_8,
> -	tegra_clk_sdmmc2_9,
>  	tegra_clk_sdmmc3,
>  	tegra_clk_sdmmc3_8,
>  	tegra_clk_sdmmc3_9,
>  	tegra_clk_sdmmc4,
>  	tegra_clk_sdmmc4_8,
> -	tegra_clk_sdmmc4_9,
>  	tegra_clk_se,
>  	tegra_clk_soc_therm,
>  	tegra_clk_soc_therm_8,
> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
> index 2acba29..38c4eb2 100644
> --- a/drivers/clk/tegra/clk-tegra-periph.c
> +++ b/drivers/clk/tegra/clk-tegra-periph.c
> @@ -451,15 +451,6 @@ static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
>  	[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
>  };
>  
> -static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
> -	"pll_p",
> -	"pll_c4_out2", "pll_c4_out0",	/* LJ input */
> -	"pll_c4_out2", "pll_c4_out1",
> -	"pll_c4_out1",			/* LJ input */
> -	"clk_m", "pll_c4_out0"
> -};
> -#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
> -
>  static const char *mux_pllp_pllc2_c_c3_clkm[] = {
>  	"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
>  };
> @@ -686,9 +677,7 @@ static struct tegra_periph_init_data periph_clks[] = {
>  	MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
>  	MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
>  	MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
> -	MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
>  	MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
> -	MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
>  	MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
>  	MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
>  	MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 5435d01..9eb1cb1 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -44,6 +44,8 @@
>  #define CLK_SOURCE_EMC 0x19c
>  #define CLK_SOURCE_SOR1 0x410
>  #define CLK_SOURCE_LA 0x1f8
> +#define CLK_SOURCE_SDMMC2 0x154
> +#define CLK_SOURCE_SDMMC4 0x164
>  
>  #define PLLC_BASE 0x80
>  #define PLLC_OUT 0x84
> @@ -2286,11 +2288,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
>  	[tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
>  	[tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
>  	[tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
> -	[tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
>  	[tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
>  	[tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
>  	[tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
> -	[tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
>  	[tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
>  	[tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
>  	[tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
> @@ -3030,6 +3030,16 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
>  				0, NULL);
>  	clks[TEGRA210_CLK_ACLK] = clk;
>  
> +	clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
> +					    CLK_SOURCE_SDMMC2, 9,
> +					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
> +	clks[TEGRA210_CLK_SDMMC2] = clk;
> +
> +	clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
> +					    CLK_SOURCE_SDMMC4, 15,
> +					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
> +	clks[TEGRA210_CLK_SDMMC4] = clk;
> +

Peter, do we need to check for an error here before populating the pointer
returned?

Cheers
Jon

-- 
nvpublic

Re: [PATCH v6 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

[Aapo Vienamo]

On Thu, 12 Jul 2018 13:59:58 +0100
Jon Hunter <jonathanh@nvidia.com> wrote:

> On 12/07/18 12:53, Aapo Vienamo wrote:
> > From: Peter De-Schrijver <pdeschrijver@nvidia.com>
> > 
> > These clocks have low jitter paths to certain parents. To model these
> > correctly, use the sdmmc mux divider clock type.
> > 
> > Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> >  drivers/clk/tegra/clk-id.h           |  2 --
> >  drivers/clk/tegra/clk-tegra-periph.c | 11 -----------
> >  drivers/clk/tegra/clk-tegra210.c     | 14 ++++++++++++--
> >  3 files changed, 12 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
> > index b616e33..de466b4 100644
> > --- a/drivers/clk/tegra/clk-id.h
> > +++ b/drivers/clk/tegra/clk-id.h
> > @@ -227,13 +227,11 @@ enum clk_id {
> >  	tegra_clk_sdmmc1_9,
> >  	tegra_clk_sdmmc2,
> >  	tegra_clk_sdmmc2_8,
> > -	tegra_clk_sdmmc2_9,
> >  	tegra_clk_sdmmc3,
> >  	tegra_clk_sdmmc3_8,
> >  	tegra_clk_sdmmc3_9,
> >  	tegra_clk_sdmmc4,
> >  	tegra_clk_sdmmc4_8,
> > -	tegra_clk_sdmmc4_9,
> >  	tegra_clk_se,
> >  	tegra_clk_soc_therm,
> >  	tegra_clk_soc_therm_8,
> > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
> > index 2acba29..38c4eb2 100644
> > --- a/drivers/clk/tegra/clk-tegra-periph.c
> > +++ b/drivers/clk/tegra/clk-tegra-periph.c
> > @@ -451,15 +451,6 @@ static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
> >  	[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
> >  };
> >  
> > -static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
> > -	"pll_p",
> > -	"pll_c4_out2", "pll_c4_out0",	/* LJ input */
> > -	"pll_c4_out2", "pll_c4_out1",
> > -	"pll_c4_out1",			/* LJ input */
> > -	"clk_m", "pll_c4_out0"
> > -};
> > -#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
> > -
> >  static const char *mux_pllp_pllc2_c_c3_clkm[] = {
> >  	"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
> >  };
> > @@ -686,9 +677,7 @@ static struct tegra_periph_init_data periph_clks[] = {
> >  	MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
> >  	MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
> >  	MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
> > -	MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
> >  	MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
> > -	MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
> >  	MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
> >  	MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
> >  	MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
> > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> > index 5435d01..9eb1cb1 100644
> > --- a/drivers/clk/tegra/clk-tegra210.c
> > +++ b/drivers/clk/tegra/clk-tegra210.c
> > @@ -44,6 +44,8 @@
> >  #define CLK_SOURCE_EMC 0x19c
> >  #define CLK_SOURCE_SOR1 0x410
> >  #define CLK_SOURCE_LA 0x1f8
> > +#define CLK_SOURCE_SDMMC2 0x154
> > +#define CLK_SOURCE_SDMMC4 0x164
> >  
> >  #define PLLC_BASE 0x80
> >  #define PLLC_OUT 0x84
> > @@ -2286,11 +2288,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
> >  	[tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
> >  	[tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
> >  	[tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
> > -	[tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
> >  	[tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
> >  	[tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
> >  	[tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
> > -	[tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
> >  	[tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
> >  	[tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
> >  	[tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
> > @@ -3030,6 +3030,16 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
> >  				0, NULL);
> >  	clks[TEGRA210_CLK_ACLK] = clk;
> >  
> > +	clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
> > +					    CLK_SOURCE_SDMMC2, 9,
> > +					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
> > +	clks[TEGRA210_CLK_SDMMC2] = clk;
> > +
> > +	clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
> > +					    CLK_SOURCE_SDMMC4, 15,
> > +					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
> > +	clks[TEGRA210_CLK_SDMMC4] = clk;
> > +  
> 
> Peter, do we need to check for an error here before populating the pointer
> returned?

The error checking is done by the code that uses the clks array, so no.

 -Aapo

Re: [PATCH v6 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

[Jon Hunter]

On 12/07/18 14:11, Aapo Vienamo wrote:
> On Thu, 12 Jul 2018 13:59:58 +0100
> Jon Hunter <jonathanh@nvidia.com> wrote:
> 
>> On 12/07/18 12:53, Aapo Vienamo wrote:
>>> From: Peter De-Schrijver <pdeschrijver@nvidia.com>
>>>
>>> These clocks have low jitter paths to certain parents. To model these
>>> correctly, use the sdmmc mux divider clock type.
>>>
>>> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
>>> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
>>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>> ---
>>>  drivers/clk/tegra/clk-id.h           |  2 --
>>>  drivers/clk/tegra/clk-tegra-periph.c | 11 -----------
>>>  drivers/clk/tegra/clk-tegra210.c     | 14 ++++++++++++--
>>>  3 files changed, 12 insertions(+), 15 deletions(-)
>>>
>>> diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
>>> index b616e33..de466b4 100644
>>> --- a/drivers/clk/tegra/clk-id.h
>>> +++ b/drivers/clk/tegra/clk-id.h
>>> @@ -227,13 +227,11 @@ enum clk_id {
>>>  	tegra_clk_sdmmc1_9,
>>>  	tegra_clk_sdmmc2,
>>>  	tegra_clk_sdmmc2_8,
>>> -	tegra_clk_sdmmc2_9,
>>>  	tegra_clk_sdmmc3,
>>>  	tegra_clk_sdmmc3_8,
>>>  	tegra_clk_sdmmc3_9,
>>>  	tegra_clk_sdmmc4,
>>>  	tegra_clk_sdmmc4_8,
>>> -	tegra_clk_sdmmc4_9,
>>>  	tegra_clk_se,
>>>  	tegra_clk_soc_therm,
>>>  	tegra_clk_soc_therm_8,
>>> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
>>> index 2acba29..38c4eb2 100644
>>> --- a/drivers/clk/tegra/clk-tegra-periph.c
>>> +++ b/drivers/clk/tegra/clk-tegra-periph.c
>>> @@ -451,15 +451,6 @@ static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
>>>  	[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
>>>  };
>>>  
>>> -static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
>>> -	"pll_p",
>>> -	"pll_c4_out2", "pll_c4_out0",	/* LJ input */
>>> -	"pll_c4_out2", "pll_c4_out1",
>>> -	"pll_c4_out1",			/* LJ input */
>>> -	"clk_m", "pll_c4_out0"
>>> -};
>>> -#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
>>> -
>>>  static const char *mux_pllp_pllc2_c_c3_clkm[] = {
>>>  	"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
>>>  };
>>> @@ -686,9 +677,7 @@ static struct tegra_periph_init_data periph_clks[] = {
>>>  	MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
>>>  	MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
>>>  	MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
>>> -	MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
>>>  	MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
>>> -	MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
>>>  	MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
>>>  	MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
>>>  	MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>> index 5435d01..9eb1cb1 100644
>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>> @@ -44,6 +44,8 @@
>>>  #define CLK_SOURCE_EMC 0x19c
>>>  #define CLK_SOURCE_SOR1 0x410
>>>  #define CLK_SOURCE_LA 0x1f8
>>> +#define CLK_SOURCE_SDMMC2 0x154
>>> +#define CLK_SOURCE_SDMMC4 0x164
>>>  
>>>  #define PLLC_BASE 0x80
>>>  #define PLLC_OUT 0x84
>>> @@ -2286,11 +2288,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
>>>  	[tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
>>>  	[tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
>>>  	[tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
>>> -	[tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
>>>  	[tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
>>>  	[tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
>>>  	[tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
>>> -	[tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
>>>  	[tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
>>>  	[tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
>>>  	[tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
>>> @@ -3030,6 +3030,16 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
>>>  				0, NULL);
>>>  	clks[TEGRA210_CLK_ACLK] = clk;
>>>  
>>> +	clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
>>> +					    CLK_SOURCE_SDMMC2, 9,
>>> +					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
>>> +	clks[TEGRA210_CLK_SDMMC2] = clk;
>>> +
>>> +	clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
>>> +					    CLK_SOURCE_SDMMC4, 15,
>>> +					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
>>> +	clks[TEGRA210_CLK_SDMMC4] = clk;
>>> +  
>>
>> Peter, do we need to check for an error here before populating the pointer
>> returned?
> 
> The error checking is done by the code that uses the clks array, so no.

Thanks! In that case ...

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH v6 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

[Stephen Boyd]

Quoting Aapo Vienamo (2018-07-12 04:53:02)
> From: Peter De-Schrijver <pdeschrijver@nvidia.com>
> 
> These clocks have low jitter paths to certain parents. To model these
> correctly, use the sdmmc mux divider clock type.
> 
> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---

Applied to clk-next