Re: [PATCH net-next v4 RESEND] stmmac: tegra: Add MGBE support

[Vladimir Oltean <olteanv@gmail.com>]

On Tue, Nov 22, 2022 at 07:05:22AM +0000, Bhadram Varka wrote:
> Reset values of XPCS IP take care of configuring the IP in 10G mode.
> No need for extra register programming is required from the driver
> side. The only status that the driver expects from XPCS IP is RLU to
> be up which will be done by serdes_up in recent posted changes. Please
> let me know if any other queries on recent changes [0]
> 
> Thank You!
> 
> [0]: https://patchwork.ozlabs.org/project/linux-tegra/patch/20221118075744.49442-2-ruppala@nvidia.com/

What about link status reporting, if the XPCS is connected to an SFP cage?

What I'm trying to get at is that maybe it would be useful to consider
the pcs-xpcs.c phylink pcs driver, even if your XPCS IP is memory mapped,
that is not a problem. Using mdiobus_register(), you can create your own
"MDIO" controller with custom bus read() and write() operations which
translate C45 accesses as seen by the xpcs driver into proper MMIO
accesses at the right address.

If I understand the hardware model right, the XPCS MDIO bus could be
exported by a common, top-level SERDES driver. In addition to the XPCS
MDIO bus, it would also model the lanes as generic PHY devices, on which
you could call phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, phy_mode),
and phy_power_on()/phy_power_off().

Can your SERDES lanes also operate in PCIe mode? If yes, how is the
selection between PCIe and Ethernet/XPCS done?