From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <vkoul@kernel.org>, <kishon@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <vidyas@nvidia.com>
Cc: <linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,
<lpieralisi@kernel.org>, <nkristam@nvidia.com>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH 1/3] dt-bindings: PHY: P2U: Add PCIe lane margining support
Date: Thu, 24 Nov 2022 14:05:08 +0530 [thread overview]
Message-ID: <20221124083510.3008139-2-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20221124083510.3008139-1-mmaddireddy@nvidia.com>
Tegra234 supports PCIe lane margining. P2U HW acts as a relay to exchange
margin control data and margin status between PCIe controller and UPHY.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
.../bindings/phy/phy-tegra194-p2u.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
index 4dc5205d893b..0ba3f6a0b474 100644
--- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
@@ -40,6 +40,51 @@ properties:
'#phy-cells':
const: 0
+ interrupts:
+ items:
+ description: P2U interrupt for Gen4 lane margining functionality.
+
+ interrupt-names:
+ items:
+ - const: intr
+
+ nvidia,bpmp:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: Must contain a pair of phandles to BPMP controller node followed by P2U ID.
+ items:
+ - items:
+ - description: phandle to BPMP controller node
+ - description: P2U instance ID
+ maximum: 24
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra194-p2u
+ then:
+ required:
+ - reg
+ - reg-names
+ - '#phy-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra234-p2u
+ then:
+ required:
+ - reg
+ - reg-names
+ - '#phy-cells'
+ - interrupts
+ - interrupt-names
+ - nvidia,bpmp
+
additionalProperties: false
examples:
@@ -49,5 +94,10 @@ examples:
reg = <0x03e10000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 337 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 1>;
+
#phy-cells = <0>;
};
--
2.25.1
next prev parent reply other threads:[~2022-11-24 8:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 8:35 [IP REVIEW PATCH 0/3] Add support for Lane Margining at Receiver Manikanta Maddireddy
2022-11-24 8:35 ` Manikanta Maddireddy [this message]
2022-11-24 8:45 ` [PATCH 1/3] dt-bindings: PHY: P2U: Add PCIe lane margining support Krzysztof Kozlowski
2022-11-30 15:11 ` Manikanta Maddireddy
2022-11-30 15:15 ` Krzysztof Kozlowski
2022-11-30 16:13 ` Manikanta Maddireddy
2022-11-24 8:35 ` [PATCH 2/3] arm64: tegra: Add uphy lane number and intr in p2u nodes Manikanta Maddireddy
2022-12-01 9:44 ` Jon Hunter
2022-12-02 5:14 ` Manikanta Maddireddy
2022-11-24 8:35 ` [PATCH 3/3] phy: tegra: Add lane margin support Manikanta Maddireddy
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