From: Aaron Kling via B4 Relay <devnull+webgeek1234.gmail.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Joseph Lo <josephl@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
Thierry Reding <treding@nvidia.com>,
Aaron Kling <webgeek1234@gmail.com>
Subject: [PATCH 3/5] soc: tegra: fuse: speedo-tegra210: Add sku 0x8F
Date: Sat, 16 Aug 2025 00:53:35 -0500 [thread overview]
Message-ID: <20250816-tegra210-speedo-v1-3-a981360adc27@gmail.com> (raw)
In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com>
From: Aaron Kling <webgeek1234@gmail.com>
This is used by the Jetson Nano series of SoMs
Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
drivers/soc/tegra/fuse/speedo-tegra210.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c
index 909fdf8fcc9d9f5ac936ae322e7a73dc720e5ab6..1cdd70c59c0753e602709f9179c0ab67d1b8f5e3 100644
--- a/drivers/soc/tegra/fuse/speedo-tegra210.c
+++ b/drivers/soc/tegra/fuse/speedo-tegra210.c
@@ -99,6 +99,14 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
sku_info->gpu_speedo_id = 1;
break;
+ case 0x8F:
+ if (speedo_rev >= 2) {
+ sku_info->cpu_speedo_id = 9;
+ sku_info->gpu_speedo_id = 2;
+ break;
+ }
+ fallthrough;
+
default:
pr_err("Tegra210: unknown SKU %#04x\n", sku);
/* Using the default for the error case */
--
2.50.1
next prev parent reply other threads:[~2025-08-16 5:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-16 5:53 [PATCH 0/5] Properly Limit Tegra210 Clock Rates Aaron Kling via B4 Relay
2025-08-16 5:53 ` [PATCH 1/5] dt-bindings: clock: tegra124-dfll: Add property to limit frequency Aaron Kling via B4 Relay
2025-08-16 8:21 ` Krzysztof Kozlowski
2025-08-18 3:23 ` Aaron Kling
2025-08-18 6:31 ` Krzysztof Kozlowski
2025-08-16 5:53 ` [PATCH 2/5] soc: tegra: fuse: speedo-tegra210: Update speedo ids Aaron Kling via B4 Relay
2025-09-03 6:39 ` Mikko Perttunen
2025-08-16 5:53 ` Aaron Kling via B4 Relay [this message]
2025-08-16 5:53 ` [PATCH 4/5] clk: tegra: dfll: Support limiting max clock per device Aaron Kling via B4 Relay
2025-08-16 5:53 ` [PATCH 5/5] arm64: tegra: Limit max cpu frequency on P3450 Aaron Kling via B4 Relay
2025-09-03 5:50 ` Mikko Perttunen
2025-09-03 6:28 ` Aaron Kling
2025-09-03 7:29 ` Mikko Perttunen
2025-09-03 8:01 ` Aaron Kling
2025-09-04 0:55 ` Mikko Perttunen
2025-09-04 1:55 ` Aaron Kling
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