From: Svyatoslav Ryhel <clamor95@gmail.com>
To: Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Svyatoslav Ryhel <clamor95@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 0/1] clk: tegra: support 48MHz clock for pll_p_out1
Date: Fri, 17 Apr 2026 10:34:51 +0300 [thread overview]
Message-ID: <20260417073452.23342-1-clamor95@gmail.com> (raw)
UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported
by kernel and causes BUG() early on. Fix this by adding 48MHz
clock support for pll_p_out1 along with 48MHz support for pll_a,
main pll_p_out1 descendant.
Dmitry Osipenko (1):
clk: tegra: support 48MHz clock for pll_p_out1
drivers/clk/tegra/clk-pll.c | 1 +
drivers/clk/tegra/clk-tegra114.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
--
2.51.0
next reply other threads:[~2026-04-17 7:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 7:34 Svyatoslav Ryhel [this message]
2026-04-17 7:34 ` [PATCH v1 1/1] clk: tegra: support 48MHz clock for pll_p_out1 Svyatoslav Ryhel
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