Re: [PATCH v6 7/9] cxl/pci: Orchestrate CXL reset for affected memdevs

["Dan Williams (nvidia)" <djbw@kernel.org>]

Srirangan Madhavan wrote:
> Add the reset flow that coordinates the target function, affected CXL
> sibling functions, and any active memdevs in the CXL.cache/mem reset
> scope.
> 
> The flow collects regions for the affected memdevs under
> cxl_rwsem.region, verifies that those regions are idle, flushes CPU
> caches for the affected ranges, saves and disables the target and sibling
> PCI functions, and locks active memdevs to revalidate that their
> endpoints are still present before reset.
> 
> After the CXL DVSEC reset completes, restore PCI config space so CXL
> MMIO is accessible, restore decoder programming for all active affected
> memdevs, commit their restored decoders, and only then re-enable CXL.mem
> for the affected set.
> 
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
[..]
> +	rc = cxl_reset_collect_memdevs(&ctx);

There can never me more than one memdev or cache interface to reset per
device, right? Those controls only exist for function0. The siblings
will not have their own reset and cache disable control DVSECs.

So, per the other observation that this probably does not need to /
cannot worry about save_and_disable precision, it only needs to invoke
the actual reset/cache management for function0.