* [PATCH] arm64: tegra: Update SDMMC1/3 clock source for Tegra194
@ 2022-03-16 9:44 Aniruddha Rao
2022-04-06 13:29 ` Thierry Reding
0 siblings, 1 reply; 2+ messages in thread
From: Aniruddha Rao @ 2022-03-16 9:44 UTC (permalink / raw)
To: Rob Herring, Thierry Reding, Jonathan Hunter
Cc: linux-tegra, linux-kernel, Aniruddha Rao
The default parent for SDMMC1/3 clock sources can provide maximum frequency
of 136MHz for SDR104 mode.
Update parent clock source for SDMMC1/SDMMC3 instances
to increase the output clock frequency to 195MHz and improve the perf.
Signed-off-by: Aniruddha Rao <anrao@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index aaa00da..a6e4b53 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -887,6 +887,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
+ assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
+ assigned-clock-parents =
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
+ <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -921,6 +926,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
+ assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
+ assigned-clock-parents =
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
+ <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: tegra: Update SDMMC1/3 clock source for Tegra194
2022-03-16 9:44 [PATCH] arm64: tegra: Update SDMMC1/3 clock source for Tegra194 Aniruddha Rao
@ 2022-04-06 13:29 ` Thierry Reding
0 siblings, 0 replies; 2+ messages in thread
From: Thierry Reding @ 2022-04-06 13:29 UTC (permalink / raw)
To: Aniruddha Rao; +Cc: Rob Herring, Jonathan Hunter, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 496 bytes --]
On Wed, Mar 16, 2022 at 03:14:45PM +0530, Aniruddha Rao wrote:
> The default parent for SDMMC1/3 clock sources can provide maximum frequency
> of 136MHz for SDR104 mode.
> Update parent clock source for SDMMC1/SDMMC3 instances
> to increase the output clock frequency to 195MHz and improve the perf.
>
> Signed-off-by: Aniruddha Rao <anrao@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Applied, thanks.
Thierry
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2022-03-16 9:44 [PATCH] arm64: tegra: Update SDMMC1/3 clock source for Tegra194 Aniruddha Rao
2022-04-06 13:29 ` Thierry Reding
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