From: Thierry Reding <thierry.reding@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/1] clk: tegra: support 48MHz clock for pll_p_out1
Date: Thu, 28 May 2026 23:55:21 +0200 [thread overview]
Message-ID: <ahi5w_cXMD1cKcMJ@orome> (raw)
In-Reply-To: <20260427132447.118272-2-clamor95@gmail.com>
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On Mon, Apr 27, 2026 at 04:24:47PM +0300, Svyatoslav Ryhel wrote:
> From: Dmitry Osipenko <digetx@gmail.com>
>
> UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported by kernel
> and causes BUG() early on. Add 48MHz clock support for pll_p_out1.
>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/clk/tegra/clk-pll.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Thierry Reding <treding@nvidia.com>
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prev parent reply other threads:[~2026-05-28 21:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-27 13:24 [PATCH v2 0/1] clk: tegra: support 48MHz clock for pll_p_out1 Svyatoslav Ryhel
2026-04-27 13:24 ` [PATCH v2 1/1] " Svyatoslav Ryhel
2026-05-28 21:55 ` Thierry Reding [this message]
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