* [PATCH v2 0/1] clk: tegra: support 48MHz clock for pll_p_out1
@ 2026-04-27 13:24 Svyatoslav Ryhel
2026-04-27 13:24 ` [PATCH v2 1/1] " Svyatoslav Ryhel
0 siblings, 1 reply; 3+ messages in thread
From: Svyatoslav Ryhel @ 2026-04-27 13:24 UTC (permalink / raw)
To: Prashant Gaikwad, Michael Turquette, Stephen Boyd, Thierry Reding,
Jonathan Hunter, Svyatoslav Ryhel
Cc: linux-clk, linux-tegra, linux-kernel
UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported
by kernel and causes BUG() early on. Fix this by adding 48MHz
clock support for pll_p_out1 along with 48MHz support for pll_a,
main pll_p_out1 descendant.
---
Changes in v2:
- aligned with downstream 3.4 kernel for tegra114 logic
---
Dmitry Osipenko (1):
clk: tegra: support 48MHz clock for pll_p_out1
drivers/clk/tegra/clk-pll.c | 1 +
1 file changed, 1 insertion(+)
--
2.51.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2 1/1] clk: tegra: support 48MHz clock for pll_p_out1
2026-04-27 13:24 [PATCH v2 0/1] clk: tegra: support 48MHz clock for pll_p_out1 Svyatoslav Ryhel
@ 2026-04-27 13:24 ` Svyatoslav Ryhel
2026-05-28 21:55 ` Thierry Reding
0 siblings, 1 reply; 3+ messages in thread
From: Svyatoslav Ryhel @ 2026-04-27 13:24 UTC (permalink / raw)
To: Prashant Gaikwad, Michael Turquette, Stephen Boyd, Thierry Reding,
Jonathan Hunter, Svyatoslav Ryhel
Cc: linux-clk, linux-tegra, linux-kernel
From: Dmitry Osipenko <digetx@gmail.com>
UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported by kernel
and causes BUG() early on. Add 48MHz clock support for pll_p_out1.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/clk/tegra/clk-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index d86003b6d94f..adfb74f111ef 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -575,6 +575,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
break;
case 9600000:
case 28800000:
+ case 48000000:
/*
* PLL_P_OUT1 rate is not listed in PLLA table
*/
--
2.51.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/1] clk: tegra: support 48MHz clock for pll_p_out1
2026-04-27 13:24 ` [PATCH v2 1/1] " Svyatoslav Ryhel
@ 2026-05-28 21:55 ` Thierry Reding
0 siblings, 0 replies; 3+ messages in thread
From: Thierry Reding @ 2026-05-28 21:55 UTC (permalink / raw)
To: Svyatoslav Ryhel
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Jonathan Hunter, linux-clk, linux-tegra, linux-kernel
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On Mon, Apr 27, 2026 at 04:24:47PM +0300, Svyatoslav Ryhel wrote:
> From: Dmitry Osipenko <digetx@gmail.com>
>
> UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported by kernel
> and causes BUG() early on. Add 48MHz clock support for pll_p_out1.
>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/clk/tegra/clk-pll.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-04-27 13:24 [PATCH v2 0/1] clk: tegra: support 48MHz clock for pll_p_out1 Svyatoslav Ryhel
2026-04-27 13:24 ` [PATCH v2 1/1] " Svyatoslav Ryhel
2026-05-28 21:55 ` Thierry Reding
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