From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Niklas Cassel <cassel@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Vidya Sagar <vidyas@nvidia.com>,
Vedant Deshpande <vedantd@nvidia.com>
Cc: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>,
Thierry Reding <treding@nvidia.com>,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes
Date: Wed, 15 Oct 2025 22:08:17 +0530 [thread overview]
Message-ID: <b872a001-0d33-4bd5-8805-b92b46c30cc5@nvidia.com> (raw)
In-Reply-To: <20251009142253.2563075-2-cassel@kernel.org>
Looks good to me
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
On 09/10/25 7:52 pm, Niklas Cassel wrote:
> External email: Use caution opening links or attachments
>
>
> When the PCIe controller is running in endpoint mode, the controller
> initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.
>
> The driver has configured an IRQ to trigger when the PERST# GPIO changes
> state. Without the pinctrl definition, we do not get an IRQ when PERST#
> is deasserted, so the PCIe controller never gets initialized.
>
> Add the missing definitions, so that the controller actually gets
> initialized.
>
> Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
> Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
> Changes since v2:
> -Add pinctrl definitions to all pcie-ep nodes, not just C4 controller.
>
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 57 ++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index df034dbb82853..cc929e1a00744 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/power/tegra234-powergate.h>
> #include <dt-bindings/reset/tegra234-reset.h>
> #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
> +#include <dt-bindings/pinctrl/pinctrl-tegra.h>
>
> / {
> compatible = "nvidia,tegra234";
> @@ -127,6 +128,52 @@ gpio: gpio@2200000 {
> pinmux: pinmux@2430000 {
> compatible = "nvidia,tegra234-pinmux";
> reg = <0x0 0x2430000 0x0 0x19100>;
> +
> + pex_rst_c4_in_state: pinmux-pex-rst-c4-in {
> + pex_rst {
> + nvidia,pins = "pex_l4_rst_n_pl1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c5_in_state: pinmux-pex-rst-c5-in {
> + pex_rst {
> + nvidia,pins = "pex_l5_rst_n_paf1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c6_in_state: pinmux-pex-rst-c6-in {
> + pex_rst {
> + nvidia,pins = "pex_l6_rst_n_paf3";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c7_in_state: pinmux-pex-rst-c7-in {
> + pex_rst {
> + nvidia,pins = "pex_l7_rst_n_pag1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c10_in_state: pinmux-pex-rst-c10-in {
> + pex_rst {
> + nvidia,pins = "pex_l10_rst_n_pag7";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> };
>
> gpcdma: dma-controller@2600000 {
> @@ -4630,6 +4677,8 @@ pcie-ep@140e0000 {
> <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c10_in_state>;
> interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -4881,6 +4930,8 @@ pcie-ep@14160000 {
> <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c4_in_state>;
> interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
> nvidia,bpmp = <&bpmp 4>;
> @@ -5023,6 +5074,8 @@ pcie-ep@141a0000 {
> <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c5_in_state>;
> interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -5115,6 +5168,8 @@ pcie-ep@141c0000 {
> <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c6_in_state>;
> interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -5207,6 +5262,8 @@ pcie-ep@141e0000 {
> <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c7_in_state>;
> interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> --
> 2.51.0
>
>
next prev parent reply other threads:[~2025-10-15 16:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 14:22 [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes Niklas Cassel
2025-10-15 16:38 ` Manikanta Maddireddy [this message]
2025-11-04 14:53 ` Niklas Cassel
2025-11-05 13:37 ` Thierry Reding
2025-11-11 13:40 ` Niklas Cassel
2025-11-11 16:37 ` Thierry Reding
2025-11-05 14:04 ` Jon Hunter
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