From: Peter Ujfalusi <peter.ujfalusi@ti.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Sameer Pujar <spujar@nvidia.com>, Vinod Koul <vkoul@kernel.org>
Cc: dan.j.williams@intel.com, tiwai@suse.com,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
sharadg@nvidia.com, rlokhande@nvidia.com, dramesh@nvidia.com,
mkumard@nvidia.com, linux-tegra <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH] [RFC] dmaengine: add fifo_size member
Date: Fri, 7 Jun 2019 08:50:08 +0300 [thread overview]
Message-ID: <d0db90e3-3d05-dfba-8768-28511d9ee3ac@ti.com> (raw)
In-Reply-To: <4593f37c-5e89-8559-4e80-99dbfe4235de@nvidia.com>
Jon,
On 06/06/2019 15.37, Jon Hunter wrote:
>> Looking at the drivers/dma/tegra210-adma.c for the
>> TEGRA*_FIFO_CTRL_DEFAULT definition it is still not clear where the
>> remote FIFO size would fit.
>> There are fields for overflow and starvation(?) thresholds and TX/RX
>> size (assuming word length, 3 == 32bits?).
>
> The TX/RX size are the FIFO size. So 3 equates to a FIFO size of 3 * 64
> bytes.
>
>> Both threshold is set to one, so I assume currently ADMA is
>> pushing/pulling data word by word.
>
> That's different. That indicates thresholds when transfers start.
>
>> Not sure what the burst size is used for, my guess would be that it is
>> used on the memory (DDR) side for optimized, more efficient accesses?
>
> That is the actual burst size.
>
>> My guess is that the threshold values are the counter limits, if the DMA
>> request counter reaches it then ADMA would do a threshold limit worth of
>> push/pull to ADMAIF.
>> Or there is another register where the remote FIFO size can be written
>> and ADMA is counting back from there until it reaches the threshold (and
>> pushes/pulling again threshold amount of data) so it keeps the FIFO
>> filled with at least threshold amount of data?
>>
>> I think in both cases the threshold would be the maxburst.
>>
>> I suppose you have the patch for adma on how to use the fifo_size
>> parameter? That would help understand what you are trying to achieve better.
>
> Its quite simple, we would just use the FIFO size to set the fields
> TEGRAXXX_ADMA_CH_FIFO_CTRL_TXSIZE/RXSIZE in the
> TEGRAXXX_ADMA_CH_FIFO_CTRL register. That's all.
Hrm, it is still not clear how all of these fits together.
What happens if you configure ADMA side:
BURST = 10
TX/RXSIZE = 100 (100 * 64 bytes?) /* FIFO_SIZE? */
*THRES = 5
And if you change the *THRES to 10?
And if you change the TX/RXSIZE to 50 (50 * 64 bytes?)
And if you change the BURST to 5?
In other words what is the relation between all of these?
There must be a rule and constraints around these and if we do really
need a new parameter for ADMA's FIFO_SIZE I'd like it to be defined in a
generic way so others could benefit without 'misusing' a fifo_size
parameter for similar, but not quite fifo_size information.
- Péter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
next prev parent reply other threads:[~2019-06-07 5:50 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1556623828-21577-1-git-send-email-spujar@nvidia.com>
[not found] ` <20190502060446.GI3845@vkoul-mobl.Dlink>
[not found] ` <e852d576-9cc2-ed42-1a1a-d696112c88bf@nvidia.com>
[not found] ` <20190502122506.GP3845@vkoul-mobl.Dlink>
[not found] ` <3368d1e1-0d7f-f602-5b96-a978fcf4d91b@nvidia.com>
[not found] ` <20190504102304.GZ3845@vkoul-mobl.Dlink>
[not found] ` <ce0e9c0b-b909-54ae-9086-a1f0f6be903c@nvidia.com>
[not found] ` <20190506155046.GH3845@vkoul-mobl.Dlink>
[not found] ` <b7e28e73-7214-f1dc-866f-102410c88323@nvidia.com>
[not found] ` <ed95f03a-bbe7-ad62-f2e1-9bfe22ec733a@ti.com>
[not found] ` <4cab47d0-41c3-5a87-48e1-d7f085c2e091@nvidia.com>
[not found] ` <8a5b84db-c00b-fff4-543f-69d90c245660@nvidia.com>
[not found] ` <3f836a10-eaf3-f59b-7170-6fe937cf2e43@ti.com>
2019-06-06 10:49 ` [PATCH] [RFC] dmaengine: add fifo_size member Jon Hunter
2019-06-06 11:54 ` Peter Ujfalusi
2019-06-06 12:37 ` Jon Hunter
2019-06-06 13:45 ` Dmitry Osipenko
2019-06-06 13:55 ` Dmitry Osipenko
2019-06-06 14:26 ` Jon Hunter
2019-06-06 14:36 ` Jon Hunter
2019-06-06 14:36 ` Dmitry Osipenko
2019-06-06 14:47 ` Jon Hunter
2019-06-06 14:25 ` Jon Hunter
2019-06-06 15:18 ` Dmitry Osipenko
2019-06-06 16:32 ` Jon Hunter
2019-06-06 16:44 ` Dmitry Osipenko
2019-06-06 16:53 ` Jon Hunter
2019-06-06 17:25 ` Dmitry Osipenko
2019-06-06 17:56 ` Dmitry Osipenko
2019-06-07 9:24 ` Jon Hunter
2019-06-07 5:50 ` Peter Ujfalusi [this message]
2019-06-07 9:18 ` Jon Hunter
2019-06-07 10:27 ` Jon Hunter
2019-06-07 12:17 ` Peter Ujfalusi
2019-06-07 12:58 ` Jon Hunter
2019-06-07 13:35 ` Peter Ujfalusi
2019-06-07 20:53 ` Dmitry Osipenko
2019-06-10 8:01 ` Jon Hunter
2019-06-10 7:59 ` Jon Hunter
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