Linux Tegra architecture development
 help / color / mirror / Atom feed

* [PATCH 25/38] dt-bindings: gpio: tegra: Convert to json-schema
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Convert the NVIDIA Tegra GPIO controller device tree bindings from
free-form text format to json-schema.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/gpio/nvidia,tegra20-gpio.txt     |  40 -------
 .../bindings/gpio/nvidia,tegra20-gpio.yaml    | 111 ++++++++++++++++++
 2 files changed, 111 insertions(+), 40 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.yaml

diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt
deleted file mode 100644
index 023c9526e5f8..000000000000
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-NVIDIA Tegra GPIO controller
-
-Required properties:
-- compatible : "nvidia,tegra<chip>-gpio"
-- reg : Physical base address and length of the controller's registers.
-- interrupts : The interrupt outputs from the controller. For Tegra20,
-  there should be 7 interrupts specified, and for Tegra30, there should
-  be 8 interrupts specified.
-- #gpio-cells : Should be two. The first cell is the pin number and the
-  second cell is used to specify optional parameters:
-  - bit 0 specifies polarity (0 for normal, 1 for inverted)
-- gpio-controller : Marks the device node as a GPIO controller.
-- #interrupt-cells : Should be 2.
-  The first cell is the GPIO number.
-  The second cell is used to specify flags:
-    bits[3:0] trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-      Valid combinations are 1, 2, 3, 4, 8.
-- interrupt-controller : Marks the device node as an interrupt controller.
-
-Example:
-
-gpio: gpio@6000d000 {
-	compatible = "nvidia,tegra20-gpio";
-	reg = < 0x6000d000 0x1000 >;
-	interrupts = < 0 32 0x04
-		       0 33 0x04
-		       0 34 0x04
-		       0 35 0x04
-		       0 55 0x04
-		       0 87 0x04
-		       0 89 0x04 >;
-	#gpio-cells = <2>;
-	gpio-controller;
-	#interrupt-cells = <2>;
-	interrupt-controller;
-};
diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.yaml
new file mode 100644
index 000000000000..b2debdb0caff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
+
+maintainers:
+  - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+  - Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+
+properties:
+  compatible:
+    oneOf:
+      - const: nvidia,tegra20-gpio
+      - const: nvidia,tegra30-gpio
+      - items:
+          - enum:
+              - nvidia,tegra114-gpio
+              - nvidia,tegra124-gpio
+              - nvidia,tegra210-gpio
+          - const: nvidia,tegra30-gpio
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: The interrupt outputs from the controller. For Tegra20,
+      there should be 7 interrupts specified, and for Tegra30, there should
+      be 8 interrupts specified.
+
+  "#gpio-cells":
+    description: The first cell is the pin number and the second cell is used
+      to specify the GPIO polarity (0 = active high, 1 = active low).
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    const: 2
+
+  gpio-controller:
+    description: Marks the device node as a GPIO controller.
+    type: boolean
+
+  "#interrupt-cells":
+    description: |
+      Should be 2. The first cell is the GPIO number. The second cell is
+      used to specify flags:
+
+        bits[3:0] trigger type and level flags:
+          1 = low-to-high edge triggered.
+          2 = high-to-low edge triggered.
+          4 = active high level-sensitive.
+          8 = active low level-sensitive.
+
+      Valid combinations are 1, 2, 3, 4, 8.
+    const: 2
+
+  interrupt-controller:
+    description: Marks the device node as an interrupt controller.
+
+patternProperties:
+  # GPIO hogs; /schemas/gpio/gpio-hog.yaml will match
+  "^gpios(-[a-zA-Z0-9-]+)?$":
+    type: object
+    required:
+      - gpio-hog
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra30-gpio
+    then:
+      properties:
+        interrupts:
+          minItems: 8
+          maxItems: 8
+    else:
+      properties:
+        interrupts:
+          minItems: 7
+          maxItems: 7
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#gpio-cells"
+  - gpio-controller
+  - "#interrupt-cells"
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    gpio: gpio@6000d000 {
+        compatible = "nvidia,tegra20-gpio";
+        reg = <0x6000d000 0x1000>;
+        interrupts = <0 32 0x04>,
+                     <0 33 0x04>,
+                     <0 34 0x04>,
+                     <0 35 0x04>,
+                     <0 55 0x04>,
+                     <0 87 0x04>,
+                     <0 89 0x04>;
+        #gpio-cells = <2>;
+        gpio-controller;
+        #interrupt-cells = <2>;
+        interrupt-controller;
+    };
-- 
2.24.1

^ permalink raw reply related

* [PATCH 26/38] dt-bindings: pci: iommu: Convert to json-schema
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Convert the PCI IOMMU device tree bindings from free-form text format to
json-schema.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/pci/pci-iommu.txt     | 171 ------------------
 .../devicetree/bindings/pci/pci-iommu.yaml    | 168 +++++++++++++++++
 2 files changed, 168 insertions(+), 171 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-iommu.txt
 create mode 100644 Documentation/devicetree/bindings/pci/pci-iommu.yaml

diff --git a/Documentation/devicetree/bindings/pci/pci-iommu.txt b/Documentation/devicetree/bindings/pci/pci-iommu.txt
deleted file mode 100644
index 0def586fdcdf..000000000000
--- a/Documentation/devicetree/bindings/pci/pci-iommu.txt
+++ /dev/null
@@ -1,171 +0,0 @@
-This document describes the generic device tree binding for describing the
-relationship between PCI(e) devices and IOMMU(s).
-
-Each PCI(e) device under a root complex is uniquely identified by its Requester
-ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
-Function number.
-
-For the purpose of this document, when treated as a numeric value, a RID is
-formatted such that:
-
-* Bits [15:8] are the Bus number.
-* Bits [7:3] are the Device number.
-* Bits [2:0] are the Function number.
-* Any other bits required for padding must be zero.
-
-IOMMUs may distinguish PCI devices through sideband data derived from the
-Requester ID. While a given PCI device can only master through one IOMMU, a
-root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
-bus).
-
-The generic 'iommus' property is insufficient to describe this relationship,
-and a mechanism is required to map from a PCI device to its IOMMU and sideband
-data.
-
-For generic IOMMU bindings, see
-Documentation/devicetree/bindings/iommu/iommu.txt.
-
-
-PCI root complex
-================
-
-Optional properties
--------------------
-
-- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
-  data.
-
-  The property is an arbitrary number of tuples of
-  (rid-base,iommu,iommu-base,length).
-
-  Any RID r in the interval [rid-base, rid-base + length) is associated with
-  the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
-
-- iommu-map-mask: A mask to be applied to each Requester ID prior to being
-  mapped to an IOMMU specifier per the iommu-map property.
-
-
-Example (1)
-===========
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	iommu: iommu@a {
-		reg = <0xa 0x1>;
-		compatible = "vendor,some-iommu";
-		#iommu-cells = <1>;
-	};
-
-	pci: pci@f {
-		reg = <0xf 0x1>;
-		compatible = "vendor,pcie-root-complex";
-		device_type = "pci";
-
-		/*
-		 * The sideband data provided to the IOMMU is the RID,
-		 * identity-mapped.
-		 */
-		iommu-map = <0x0 &iommu 0x0 0x10000>;
-	};
-};
-
-
-Example (2)
-===========
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	iommu: iommu@a {
-		reg = <0xa 0x1>;
-		compatible = "vendor,some-iommu";
-		#iommu-cells = <1>;
-	};
-
-	pci: pci@f {
-		reg = <0xf 0x1>;
-		compatible = "vendor,pcie-root-complex";
-		device_type = "pci";
-
-		/*
-		 * The sideband data provided to the IOMMU is the RID with the
-		 * function bits masked out.
-		 */
-		iommu-map = <0x0 &iommu 0x0 0x10000>;
-		iommu-map-mask = <0xfff8>;
-	};
-};
-
-
-Example (3)
-===========
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	iommu: iommu@a {
-		reg = <0xa 0x1>;
-		compatible = "vendor,some-iommu";
-		#iommu-cells = <1>;
-	};
-
-	pci: pci@f {
-		reg = <0xf 0x1>;
-		compatible = "vendor,pcie-root-complex";
-		device_type = "pci";
-
-		/*
-		 * The sideband data provided to the IOMMU is the RID,
-		 * but the high bits of the bus number are flipped.
-		 */
-		iommu-map = <0x0000 &iommu 0x8000 0x8000>,
-			    <0x8000 &iommu 0x0000 0x8000>;
-	};
-};
-
-
-Example (4)
-===========
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	iommu_a: iommu@a {
-		reg = <0xa 0x1>;
-		compatible = "vendor,some-iommu";
-		#iommu-cells = <1>;
-	};
-
-	iommu_b: iommu@b {
-		reg = <0xb 0x1>;
-		compatible = "vendor,some-iommu";
-		#iommu-cells = <1>;
-	};
-
-	iommu_c: iommu@c {
-		reg = <0xc 0x1>;
-		compatible = "vendor,some-iommu";
-		#iommu-cells = <1>;
-	};
-
-	pci: pci@f {
-		reg = <0xf 0x1>;
-		compatible = "vendor,pcie-root-complex";
-		device_type = "pci";
-
-		/*
-		 * Devices with bus number 0-127 are mastered via IOMMU
-		 * a, with sideband data being RID[14:0].
-		 * Devices with bus number 128-255 are mastered via
-		 * IOMMU b, with sideband data being RID[14:0].
-		 * No devices master via IOMMU c.
-		 */
-		iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
-			    <0x8000 &iommu_b 0x0000 0x8000>;
-	};
-};
diff --git a/Documentation/devicetree/bindings/pci/pci-iommu.yaml b/Documentation/devicetree/bindings/pci/pci-iommu.yaml
new file mode 100644
index 000000000000..8aaa8e657559
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pci-iommu.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/pci-iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCI IOMMU bindings
+
+maintainers:
+  - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
+
+description: |
+  This document describes the generic device tree binding for describing the
+  relationship between PCI(e) devices and IOMMU(s).
+
+  Each PCI(e) device under a root complex is uniquely identified by its
+  Requester ID (AKA RID). A Requester ID is a triplet of a Bus number, Device
+  number, and Function number.
+
+  For the purpose of this document, when treated as a numeric value, a RID is
+  formatted such that:
+
+    * Bits [15:8] are the Bus number.
+    * Bits [7:3] are the Device number.
+    * Bits [2:0] are the Function number.
+    * Any other bits required for padding must be zero.
+
+  IOMMUs may distinguish PCI devices through sideband data derived from the
+  Requester ID. While a given PCI device can only master through one IOMMU, a
+  root complex may split masters across a set of IOMMUs (e.g. with one IOMMU
+  per bus).
+
+  The generic 'iommus' property is insufficient to describe this relationship,
+  and a mechanism is required to map from a PCI device to its IOMMU and
+  sideband data.
+
+  For generic IOMMU bindings, see
+  Documentation/devicetree/bindings/iommu/iommu.txt.
+
+properties:
+  iommu-map:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    description: |
+      Maps a Requester ID to an IOMMU and associated IOMMU specifier data.
+
+      The property is an arbitrary number of tuples of (rid-base, iommu,
+      iommu-base, length).
+
+      Any RID r in the interval [rid-base, rid-base + length) is associated
+      with the listed IOMMU, with the IOMMU specifier (r - rid-base +
+      iommu-base).
+
+  iommu-map-mask:
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    description:
+      A mask to be applied to each Requester ID prior to being mapped to an
+      IOMMU specifier per the iommu-map property.
+
+examples:
+  - |
+    iommu0: iommu@a {
+        reg = <0xa 0x1>;
+        compatible = "vendor,some-iommu";
+        #iommu-cells = <1>;
+    };
+
+    pci@f {
+        reg = <0xf 0x1>;
+        compatible = "vendor,pcie-root-complex";
+        device_type = "pci";
+
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00000000>;
+
+        /*
+         * The sideband data provided to the IOMMU is the RID,
+         * identity-mapped.
+         */
+        iommu-map = <0x0 &iommu0 0x0 0x10000>;
+    };
+
+  - |
+    iommu1: iommu@a {
+        reg = <0xa 0x1>;
+        compatible = "vendor,some-iommu";
+        #iommu-cells = <1>;
+    };
+
+    pci@f {
+        reg = <0xf 0x1>;
+        compatible = "vendor,pcie-root-complex";
+        device_type = "pci";
+
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00000000>;
+
+        /*
+         * The sideband data provided to the IOMMU is the RID with the
+         * function bits masked out.
+         */
+        iommu-map = <0x0 &iommu 0x0 0x10000>;
+        iommu-map-mask = <0xfff8>;
+    };
+
+  - |
+    iommu2: iommu@a {
+        reg = <0xa 0x1>;
+        compatible = "vendor,some-iommu";
+        #iommu-cells = <1>;
+    };
+
+    pci@f {
+        reg = <0xf 0x1>;
+        compatible = "vendor,pcie-root-complex";
+        device_type = "pci";
+
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00000000>;
+
+        /*
+         * The sideband data provided to the IOMMU is the RID,
+         * but the high bits of the bus number are flipped.
+         */
+        iommu-map = <0x0000 &iommu2 0x8000 0x8000>,
+                    <0x8000 &iommu2 0x0000 0x8000>;
+    };
+
+  - |
+    iommu_a: iommu@a {
+        reg = <0xa 0x1>;
+        compatible = "vendor,some-iommu";
+        #iommu-cells = <1>;
+    };
+
+    iommu_b: iommu@b {
+        reg = <0xb 0x1>;
+        compatible = "vendor,some-iommu";
+        #iommu-cells = <1>;
+    };
+
+    iommu_c: iommu@c {
+        reg = <0xc 0x1>;
+        compatible = "vendor,some-iommu";
+        #iommu-cells = <1>;
+    };
+
+    pci@f {
+        reg = <0xf 0x1>;
+        compatible = "vendor,pcie-root-complex";
+        device_type = "pci";
+
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00000000>;
+
+        /*
+         * Devices with bus number 0-127 are mastered via IOMMU
+         * a, with sideband data being RID[14:0].
+         * Devices with bus number 128-255 are mastered via
+         * IOMMU b, with sideband data being RID[14:0].
+         * No devices master via IOMMU c.
+         */
+        iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
+                    <0x8000 &iommu_b 0x0000 0x8000>;
+    };
-- 
2.24.1

^ permalink raw reply related

* [PATCH 27/38] dt-bindings: tegra: Add missing compatible strings
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The Nyan Blaze and Nyan Big, as well as Jetson Nano (P3450-0000), Darcy
(P2894-0050-A08) and Pixel C (Smaug) were never mentioned. Add them.

While at it, also fix a typo in the compatible string for Apalis Tegra30
v1.1 evaluation board.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/arm/tegra.yaml        | 46 ++++++++++++++++++-
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml
index 60b38eb5c61a..043ca543be8c 100644
--- a/Documentation/devicetree/bindings/arm/tegra.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra.yaml
@@ -49,7 +49,7 @@ properties:
           - const: toradex,apalis_t30
           - const: nvidia,tegra30
       - items:
-          - const: toradex,apalis_t30-eval-v1.1
+          - const: toradex,apalis_t30-v1.1-eval
           - const: toradex,apalis_t30-eval
           - const: toradex,apalis_t30-v1.1
           - const: toradex,apalis_t30
@@ -80,6 +80,33 @@ properties:
           - const: toradex,apalis-tk1-v1.2
           - const: toradex,apalis-tk1
           - const: nvidia,tegra124
+      - items:
+          - const: google,nyan-big-rev7
+          - const: google,nyan-big-rev6
+          - const: google,nyan-big-rev5
+          - const: google,nyan-big-rev4
+          - const: google,nyan-big-rev3
+          - const: google,nyan-big-rev2
+          - const: google,nyan-big-rev1
+          - const: google,nyan-big-rev0
+          - const: google,nyan-big
+          - const: google,nyan
+          - const: nvidia,tegra124
+      - items:
+          - const: google,nyan-blaze-rev10
+          - const: google,nyan-blaze-rev9
+          - const: google,nyan-blaze-rev8
+          - const: google,nyan-blaze-rev7
+          - const: google,nyan-blaze-rev6
+          - const: google,nyan-blaze-rev5
+          - const: google,nyan-blaze-rev4
+          - const: google,nyan-blaze-rev3
+          - const: google,nyan-blaze-rev2
+          - const: google,nyan-blaze-rev1
+          - const: google,nyan-blaze-rev0
+          - const: google,nyan-blaze
+          - const: google,nyan
+          - const: nvidia,tegra124
       - items:
           - enum:
               - nvidia,norrin
@@ -91,7 +118,22 @@ properties:
               - nvidia,p2371-0000
               - nvidia,p2371-2180
               - nvidia,p2571
-              - nvidia,p2894-0050-a08
+              - nvidia,p3450-0000
+          - const: nvidia,tegra210
+      - items:
+          - const: nvidia,p2894-0050-a08
+          - const: nvidia,darcy
+          - const: nvidia,tegra210
+      - items:
+          - const: google,smaug-rev8
+          - const: google,smaug-rev7
+          - const: google,smaug-rev6
+          - const: google,smaug-rev5
+          - const: google,smaug-rev4
+          - const: google,smaug-rev3
+          - const: google,smaug-rev2
+          - const: google,smaug-rev1
+          - const: google,smaug
           - const: nvidia,tegra210
       - items:
           - enum:
-- 
2.24.1

^ permalink raw reply related

* [PATCH 28/38] dt-bindings: phy: tegra-xusb: Convert to json-schema
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Convert the Tegra XUSB pad controller bindings from free-form text
format to json-schema.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../phy/nvidia,tegra124-xusb-padctl.txt       |  778 -----
 .../phy/nvidia,tegra124-xusb-padctl.yaml      | 2800 +++++++++++++++++
 2 files changed, 2800 insertions(+), 778 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
 create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml

diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
deleted file mode 100644
index 38c5fa21f435..000000000000
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
+++ /dev/null
@@ -1,778 +0,0 @@
-Device tree binding for NVIDIA Tegra XUSB pad controller
-========================================================
-
-The Tegra XUSB pad controller manages a set of I/O lanes (with differential
-signals) which connect directly to pins/pads on the SoC package. Each lane
-is controlled by a HW block referred to as a "pad" in the Tegra hardware
-documentation. Each such "pad" may control either one or multiple lanes,
-and thus contains any logic common to all its lanes. Each lane can be
-separately configured and powered up.
-
-Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
-super-speed USB. Other lanes are for various types of low-speed, full-speed
-or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
-contains a software-configurable mux that sits between the I/O controller
-ports (e.g. PCIe) and the lanes.
-
-In addition to per-lane configuration, USB 3.0 ports may require additional
-settings on a per-board basis.
-
-Pads will be represented as children of the top-level XUSB pad controller
-device tree node. Each lane exposed by the pad will be represented by its
-own subnode and can be referenced by users of the lane using the standard
-PHY bindings, as described by the phy-bindings.txt file in this directory.
-
-The Tegra hardware documentation refers to the connection between the XUSB
-pad controller and the XUSB controller as "ports". This is confusing since
-"port" is typically used to denote the physical USB receptacle. The device
-tree binding in this document uses the term "port" to refer to the logical
-abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
-for the USB signal, the VBUS power supply, the USB 2.0 companion port for
-USB 3.0 receptacles, ...).
-
-Required properties:
---------------------
-- compatible: Must be:
-  - Tegra124: "nvidia,tegra124-xusb-padctl"
-  - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
-  - Tegra210: "nvidia,tegra210-xusb-padctl"
-  - Tegra186: "nvidia,tegra186-xusb-padctl"
-  - Tegra194: "nvidia,tegra194-xusb-padctl"
-- reg: Physical base address and length of the controller's registers.
-- resets: Must contain an entry for each entry in reset-names.
-- reset-names: Must include the following entries:
-  - "padctl"
-
-For Tegra124:
-- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
-- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
-- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
-- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
-
-For Tegra210:
-- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
-- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
-- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
-- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
-
-For Tegra186:
-- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
-  power supply. Must supply 1.8 V.
-- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
-  3.3 V.
-- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
-- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
-
-For Tegra194:
-- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
-  3.3 V.
-- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
-
-Pad nodes:
-==========
-
-A required child node named "pads" contains a list of subnodes, one for each
-of the pads exposed by the XUSB pad controller. Each pad may need additional
-resources that can be referenced in its pad node.
-
-The "status" property is used to enable or disable the use of a pad. If set
-to "disabled", the pad will not be used on the given board. In order to use
-the pad and any of its lanes, this property must be set to "okay".
-
-For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
-and sata. No extra resources are required for operation of these pads.
-
-For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
-a description of the properties of each pad.
-
-UTMI pad:
----------
-
-Required properties:
-- clocks: Must contain an entry for each entry in clock-names.
-- clock-names: Must contain the following entries:
-  - "trk": phandle and specifier referring to the USB2 tracking clock
-
-HSIC pad:
----------
-
-Required properties:
-- clocks: Must contain an entry for each entry in clock-names.
-- clock-names: Must contain the following entries:
-  - "trk": phandle and specifier referring to the HSIC tracking clock
-
-PCIe pad:
----------
-
-Required properties:
-- clocks: Must contain an entry for each entry in clock-names.
-- clock-names: Must contain the following entries:
-  - "pll": phandle and specifier referring to the PLLE
-- resets: Must contain an entry for each entry in reset-names.
-- reset-names: Must contain the following entries:
-  - "phy": reset for the PCIe UPHY block
-
-SATA pad:
----------
-
-Required properties:
-- resets: Must contain an entry for each entry in reset-names.
-- reset-names: Must contain the following entries:
-  - "phy": reset for the SATA UPHY block
-
-
-PHY nodes:
-==========
-
-Each pad node has a child named "lanes" that contains one or more children of
-its own, each representing one of the lanes controlled by the pad.
-
-Required properties:
---------------------
-- status: Defines the operation status of the PHY. Valid values are:
-  - "disabled": the PHY is disabled
-  - "okay": the PHY is enabled
-- #phy-cells: Should be 0. Since each lane represents a single PHY, there is
-  no need for an additional specifier.
-- nvidia,function: The output function of the PHY. See below for a list of
-  valid functions per SoC generation.
-
-For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
-- usb2: usb2-0, usb2-1, usb2-2
-  - functions: "snps", "xusb", "uart"
-- ulpi: ulpi-0
-  - functions: "snps", "xusb"
-- hsic: hsic-0, hsic-1
-  - functions: "snps", "xusb"
-- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
-  - functions: "pcie", "usb3-ss"
-- sata: sata-0
-  - functions: "usb3-ss", "sata"
-
-For Tegra210, the list of valid PHY nodes is given below:
-- usb2: usb2-0, usb2-1, usb2-2, usb2-3
-  - functions: "snps", "xusb", "uart"
-- hsic: hsic-0, hsic-1
-  - functions: "snps", "xusb"
-- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
-  - functions: "pcie-x1", "usb3-ss", "pcie-x4"
-- sata: sata-0
-  - functions: "usb3-ss", "sata"
-
-For Tegra194, the list of valid PHY nodes is given below:
-- usb2: usb2-0, usb2-1, usb2-2, usb2-3
-  - functions: "xusb"
-- usb3: usb3-0, usb3-1, usb3-2, usb3-3
-  - functions: "xusb"
-
-Port nodes:
-===========
-
-A required child node named "ports" contains a list of all the ports exposed
-by the XUSB pad controller. Per-port configuration is only required for USB.
-
-USB2 ports:
------------
-
-Required properties:
-- status: Defines the operation status of the port. Valid values are:
-  - "disabled": the port is disabled
-  - "okay": the port is enabled
-- mode: A string that determines the mode in which to run the port. Valid
-  values are:
-  - "host": for USB host mode
-  - "device": for USB device mode
-  - "otg": for USB OTG mode
-
-Required properties for OTG/Peripheral capable USB2 ports:
-- usb-role-switch: Boolean property to indicate that the port support OTG or
-  peripheral mode. If present, the port supports switching between USB host
-  and peripheral roles. Connector should be added as subnode.
-  See usb/usb-conn-gpio.txt.
-
-Optional properties:
-- nvidia,internal: A boolean property whose presence determines that a port
-  is internal. In the absence of this property the port is considered to be
-  external.
-- vbus-supply: phandle to a regulator supplying the VBUS voltage.
-
-ULPI ports:
------------
-
-Optional properties:
-- status: Defines the operation status of the port. Valid values are:
-  - "disabled": the port is disabled
-  - "okay": the port is enabled
-- nvidia,internal: A boolean property whose presence determines that a port
-  is internal. In the absence of this property the port is considered to be
-  external.
-- vbus-supply: phandle to a regulator supplying the VBUS voltage.
-
-HSIC ports:
------------
-
-Required properties:
-- status: Defines the operation status of the port. Valid values are:
-  - "disabled": the port is disabled
-  - "okay": the port is enabled
-
-Optional properties:
-- vbus-supply: phandle to a regulator supplying the VBUS voltage.
-
-Super-speed USB ports:
-----------------------
-
-Required properties:
-- status: Defines the operation status of the port. Valid values are:
-  - "disabled": the port is disabled
-  - "okay": the port is enabled
-- nvidia,usb2-companion: A single cell that specifies the physical port number
-  to map this super-speed USB port to. The range of valid port numbers varies
-  with the SoC generation:
-  - 0-2: for Tegra124 and Tegra132
-  - 0-3: for Tegra210
-
-Optional properties:
-- nvidia,internal: A boolean property whose presence determines that a port
-  is internal. In the absence of this property the port is considered to be
-  external.
-
-- maximum-speed: Only for Tegra194. A string property that specifies maximum
-  supported speed of a usb3 port. Valid values are:
-  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
-  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
-
-For Tegra124 and Tegra132, the XUSB pad controller exposes the following
-ports:
-- 3x USB2: usb2-0, usb2-1, usb2-2
-- 1x ULPI: ulpi-0
-- 2x HSIC: hsic-0, hsic-1
-- 2x super-speed USB: usb3-0, usb3-1
-
-For Tegra210, the XUSB pad controller exposes the following ports:
-- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
-- 2x HSIC: hsic-0, hsic-1
-- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
-
-For Tegra194, the XUSB pad controller exposes the following ports:
-- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
-- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
-
-Examples:
-=========
-
-Tegra124 and Tegra132:
-----------------------
-
-SoC include:
-
-	padctl@7009f000 {
-		/* for Tegra124 */
-		compatible = "nvidia,tegra124-xusb-padctl";
-		/* for Tegra132 */
-		compatible = "nvidia,tegra132-xusb-padctl",
-			     "nvidia,tegra124-xusb-padctl";
-		reg = <0x0 0x7009f000 0x0 0x1000>;
-		resets = <&tegra_car 142>;
-		reset-names = "padctl";
-
-		pads {
-			usb2 {
-				status = "disabled";
-
-				lanes {
-					usb2-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					usb2-1 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					usb2-2 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-
-			ulpi {
-				status = "disabled";
-
-				lanes {
-					ulpi-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-
-			hsic {
-				status = "disabled";
-
-				lanes {
-					hsic-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					hsic-1 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-
-			pcie {
-				status = "disabled";
-
-				lanes {
-					pcie-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-1 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-2 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-3 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-4 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-
-			sata {
-				status = "disabled";
-
-				lanes {
-					sata-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-		};
-
-		ports {
-			usb2-0 {
-				status = "disabled";
-			};
-
-			usb2-1 {
-				status = "disabled";
-			};
-
-			usb2-2 {
-				status = "disabled";
-			};
-
-			ulpi-0 {
-				status = "disabled";
-			};
-
-			hsic-0 {
-				status = "disabled";
-			};
-
-			hsic-1 {
-				status = "disabled";
-			};
-
-			usb3-0 {
-				status = "disabled";
-			};
-
-			usb3-1 {
-				status = "disabled";
-			};
-		};
-	};
-
-Board file:
-
-	padctl@7009f000 {
-		status = "okay";
-
-		pads {
-			usb2 {
-				status = "okay";
-
-				lanes {
-					usb2-0 {
-						nvidia,function = "xusb";
-						status = "okay";
-					};
-
-					usb2-1 {
-						nvidia,function = "xusb";
-						status = "okay";
-					};
-
-					usb2-2 {
-						nvidia,function = "xusb";
-						status = "okay";
-					};
-				};
-			};
-
-			pcie {
-				status = "okay";
-
-				lanes {
-					pcie-0 {
-						nvidia,function = "usb3-ss";
-						status = "okay";
-					};
-
-					pcie-2 {
-						nvidia,function = "pcie";
-						status = "okay";
-					};
-
-					pcie-4 {
-						nvidia,function = "pcie";
-						status = "okay";
-					};
-				};
-			};
-
-			sata {
-				status = "okay";
-
-				lanes {
-					sata-0 {
-						nvidia,function = "sata";
-						status = "okay";
-					};
-				};
-			};
-		};
-
-		ports {
-			/* Micro A/B */
-			usb2-0 {
-				status = "okay";
-				mode = "otg";
-			};
-
-			/* Mini PCIe */
-			usb2-1 {
-				status = "okay";
-				mode = "host";
-			};
-
-			/* USB3 */
-			usb2-2 {
-				status = "okay";
-				mode = "host";
-
-				vbus-supply = <&vdd_usb3_vbus>;
-			};
-
-			usb3-0 {
-				nvidia,port = <2>;
-				status = "okay";
-			};
-		};
-	};
-
-Tegra210:
----------
-
-SoC include:
-
-	padctl@7009f000 {
-		compatible = "nvidia,tegra210-xusb-padctl";
-		reg = <0x0 0x7009f000 0x0 0x1000>;
-		resets = <&tegra_car 142>;
-		reset-names = "padctl";
-
-		status = "disabled";
-
-		pads {
-			usb2 {
-				clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
-				clock-names = "trk";
-				status = "disabled";
-
-				lanes {
-					usb2-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					usb2-1 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					usb2-2 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					usb2-3 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-
-			hsic {
-				clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
-				clock-names = "trk";
-				status = "disabled";
-
-				lanes {
-					hsic-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					hsic-1 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-
-			pcie {
-				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
-				clock-names = "pll";
-				resets = <&tegra_car 205>;
-				reset-names = "phy";
-				status = "disabled";
-
-				lanes {
-					pcie-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-1 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-2 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-3 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-4 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-5 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-
-					pcie-6 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-
-			sata {
-				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
-				clock-names = "pll";
-				resets = <&tegra_car 204>;
-				reset-names = "phy";
-				status = "disabled";
-
-				lanes {
-					sata-0 {
-						status = "disabled";
-						#phy-cells = <0>;
-					};
-				};
-			};
-		};
-
-		ports {
-			usb2-0 {
-				status = "disabled";
-			};
-
-			usb2-1 {
-				status = "disabled";
-			};
-
-			usb2-2 {
-				status = "disabled";
-			};
-
-			usb2-3 {
-				status = "disabled";
-			};
-
-			hsic-0 {
-				status = "disabled";
-			};
-
-			hsic-1 {
-				status = "disabled";
-			};
-
-			usb3-0 {
-				status = "disabled";
-			};
-
-			usb3-1 {
-				status = "disabled";
-			};
-
-			usb3-2 {
-				status = "disabled";
-			};
-
-			usb3-3 {
-				status = "disabled";
-			};
-		};
-	};
-
-Board file:
-
-	padctl@7009f000 {
-		status = "okay";
-
-		pads {
-			usb2 {
-				status = "okay";
-
-				lanes {
-					usb2-0 {
-						nvidia,function = "xusb";
-						status = "okay";
-					};
-
-					usb2-1 {
-						nvidia,function = "xusb";
-						status = "okay";
-					};
-
-					usb2-2 {
-						nvidia,function = "xusb";
-						status = "okay";
-					};
-
-					usb2-3 {
-						nvidia,function = "xusb";
-						status = "okay";
-					};
-				};
-			};
-
-			pcie {
-				status = "okay";
-
-				lanes {
-					pcie-0 {
-						nvidia,function = "pcie-x1";
-						status = "okay";
-					};
-
-					pcie-1 {
-						nvidia,function = "pcie-x4";
-						status = "okay";
-					};
-
-					pcie-2 {
-						nvidia,function = "pcie-x4";
-						status = "okay";
-					};
-
-					pcie-3 {
-						nvidia,function = "pcie-x4";
-						status = "okay";
-					};
-
-					pcie-4 {
-						nvidia,function = "pcie-x4";
-						status = "okay";
-					};
-
-					pcie-5 {
-						nvidia,function = "usb3-ss";
-						status = "okay";
-					};
-
-					pcie-6 {
-						nvidia,function = "usb3-ss";
-						status = "okay";
-					};
-				};
-			};
-
-			sata {
-				status = "okay";
-
-				lanes {
-					sata-0 {
-						nvidia,function = "sata";
-						status = "okay";
-					};
-				};
-			};
-		};
-
-		ports {
-			usb2-0 {
-				status = "okay";
-				mode = "otg";
-			};
-
-			usb2-1 {
-				status = "okay";
-				vbus-supply = <&vdd_5v0_rtl>;
-				mode = "host";
-			};
-
-			usb2-2 {
-				status = "okay";
-				vbus-supply = <&vdd_usb_vbus>;
-				mode = "host";
-			};
-
-			usb2-3 {
-				status = "okay";
-				mode = "host";
-			};
-
-			usb3-0 {
-				status = "okay";
-				nvidia,lanes = "pcie-6";
-				nvidia,port = <1>;
-			};
-
-			usb3-1 {
-				status = "okay";
-				nvidia,lanes = "pcie-5";
-				nvidia,port = <2>;
-			};
-		};
-	};
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml
new file mode 100644
index 000000000000..8c647fd4a340
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml
@@ -0,0 +1,2800 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra XUSB pad controller
+
+maintainers:
+  - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+  - Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+
+description:
+  The Tegra XUSB pad controller manages a set of I/O lanes (with differential
+  signals) which connect directly to pins/pads on the SoC package. Each lane
+  is controlled by a HW block referred to as a "pad" in the Tegra hardware
+  documentation. Each such "pad" may control either one or multiple lanes,
+  and thus contains any logic common to all its lanes. Each lane can be
+  separately configured and powered up.
+
+  Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
+  super-speed USB. Other lanes are for various types of low-speed, full-speed
+  or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
+  contains a software-configurable mux that sits between the I/O controller
+  ports (e.g. PCIe) and the lanes.
+
+  In addition to per-lane configuration, USB 3.0 ports may require additional
+  settings on a per-board basis.
+
+  Pads will be represented as children of the top-level XUSB pad controller
+  device tree node. Each lane exposed by the pad will be represented by its
+  own subnode and can be referenced by users of the lane using the standard
+  PHY bindings, as described by the phy-bindings.txt file in this directory.
+
+  The Tegra hardware documentation refers to the connection between the XUSB
+  pad controller and the XUSB controller as "ports". This is confusing since
+  "port" is typically used to denote the physical USB receptacle. The device
+  tree binding in this document uses the term "port" to refer to the logical
+  abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
+  for the USB signal, the VBUS power supply, the USB 2.0 companion port for
+  USB 3.0 receptacles, ...).
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: nvidia,tegra124-xusb-padctl
+
+      - items:
+          - const: nvidia,tegra132-xusb-padctl
+          - const: nvidia,tegra124-xusb-padctl
+
+      - items:
+          - const: nvidia,tegra210-xusb-padctl
+
+      - items:
+          - const: nvidia,tegra186-xusb-padctl
+
+      - items:
+          - const: nvidia,tegra194-xusb-padctl
+
+  resets:
+    items:
+      - description: pad controller reset
+
+  reset-names:
+    items:
+      - const: padctl
+
+  pads:
+    description: A required child node named "pads" contains a list of
+      subnodes, one for each of the pads exposed by the XUSB pad controller.
+      Each pad may need additional resources that can be referenced in its
+      pad node.
+
+      The "status" property is used to enable or disable the use of a pad.
+      If set to "disabled", the pad will not be used on the given board. In
+      order to use the pad and any of its lanes, this property must be set
+      to "okay".
+    type: object
+
+  ports:
+    type: object
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra124-xusb-padctl
+    then:
+      properties:
+        reg:
+          maxItems: 1
+
+        avdd-pll-utmip-supply:
+          description: UTMI PLL power supply. Must supply 1.8 V.
+
+        avdd-pll-erefe-supply:
+          description: PLLE reference PLL power supply. Must supply 1.05 V.
+
+        avdd-pex-pll-supply:
+          description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
+
+        hvdd-pex-pll-e-supply:
+          description: High-voltage PLLE power supply. Must supply 3.3 V.
+
+        pads:
+          properties:
+            usb2:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: USB2 tracking clock
+
+                clock-names:
+                  items:
+                    - const: trk
+
+                lanes:
+                  type: object
+                  properties:
+                    usb2-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb, uart ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb, uart ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb, uart ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            ulpi:
+              type: object
+              properties:
+                lanes:
+                  type: object
+                  properties:
+                    ulpi-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            hsic:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: HSIC tracking clock
+
+                clock-names:
+                  items:
+                    - const: trk
+
+                lanes:
+                  type: object
+                  properties:
+                    hsic-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    hsic-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            pcie:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: PLLE clock
+
+                clock-names:
+                  items:
+                    - const: pll
+
+                resets:
+                  items:
+                    - description: reset for the PCIe UPHY block
+
+                reset-names:
+                  items:
+                    - const: phy
+
+                lanes:
+                  type: object
+                  properties:
+                    pcie-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie, usb3-ss ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie, usb3-ss ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie, usb3-ss ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-3:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie, usb3-ss ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-4:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie, usb3-ss ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            sata:
+              type: object
+              properties:
+                resets:
+                  items:
+                    - description: reset for the SATA UPHY block
+
+                reset-names:
+                  items:
+                    - const: phy
+
+                lanes:
+                  type: object
+                  properties:
+                    sata-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ sata, usb3-ss ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+          additionalProperties: false
+
+        ports:
+          properties:
+            usb2-0:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-1:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-2:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            ulpi-0:
+              type: object
+              properties:
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            hsic-0:
+              type: object
+              properties:
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            hsic-1:
+              type: object
+              properties:
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-0:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-1:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+          additionalProperties: false
+
+      required:
+        - avdd-pll-utmip-supply
+        - avdd-pll-erefe-supply
+        - avdd-pex-pll-supply
+        - hvdd-pex-pll-e-supply
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra210-xusb-padctl
+    then:
+      properties:
+        reg:
+          maxItems: 1
+
+        avdd-pll-utmip-supply:
+          description: UTMI PLL power supply. Must supply 1.8 V.
+
+        avdd-pll-uerefe-supply:
+          description: PLLE reference PLL power supply. Must supply 1.05 V.
+
+        dvdd-pex-pll-supply:
+          description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
+
+        hvdd-pex-pll-e-supply:
+          description: High-voltage PLLE power supply. Must supply 1.8 V.
+
+        pads:
+          properties:
+            usb2:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: USB2 tracking clock
+
+                clock-names:
+                  items:
+                    - const: trk
+
+                lanes:
+                  type: object
+                  properties:
+                    usb2-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb, uart ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb, uart ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb, uart ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-3:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb, uart ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            hsic:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: HSIC tracking clock
+
+                clock-names:
+                  items:
+                    - const: trk
+
+                lanes:
+                  type: object
+                  properties:
+                    hsic-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    hsic-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ snps, xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            pcie:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: PCIe PLL clock source
+
+                clock-names:
+                  items:
+                    - const: pll
+
+                resets:
+                  items:
+                    - description: PCIe PHY reset
+
+                reset-names:
+                  items:
+                    - const: phy
+
+                lanes:
+                  type: object
+                  properties:
+                    pcie-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie-x1, usb3-ss, pcie-x4 ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie-x1, usb3-ss, pcie-x4 ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie-x1, usb3-ss, pcie-x4 ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-3:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie-x1, usb3-ss, pcie-x4 ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-4:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie-x1, usb3-ss, pcie-x4 ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-5:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie-x1, usb3-ss, pcie-x4 ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    pcie-6:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ pcie-x1, usb3-ss, pcie-x4 ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            sata:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: SATA PLL clock source
+
+                clock-names:
+                  items:
+                    - const: pll
+
+                resets:
+                  items:
+                    - description: SATA PHY reset
+
+                reset-names:
+                  items:
+                    - const: phy
+
+                lanes:
+                  type: object
+                  properties:
+                    sata-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ usb3-ss, sata ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+          additionalProperties: false
+
+        ports:
+          properties:
+            usb2-0:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-1:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-2:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-3:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            hsic-0:
+              type: object
+              properties:
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            hsic-1:
+              type: object
+              properties:
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-0:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-1:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-2:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-3:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+          additionalProperties: false
+
+      required:
+        - avdd-pll-utmip-supply
+        - avdd-pll-uerefe-supply
+        - dvdd-pex-pll-supply
+        - hvdd-pex-pll-e-supply
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra186-xusb-padctl
+    then:
+      properties:
+        reg:
+          items:
+            - description: pad controller registers
+            - description: AO registers
+          maxItems: 2
+
+        reg-names:
+          items:
+            - const: padctl
+            - const: ao
+
+        avdd-pll-erefeut-supply:
+          description: UPHY brick and reference clock as well as UTMI PHY
+            power supply. Must supply 1.8 V.
+
+        avdd-usb-supply:
+          description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
+            supply 3.3 V.
+
+        vclamp-usb-supply:
+          description: Bias rail for USB pad. Must supply 1.8 V.
+
+        vddio-hsic-supply:
+          description: HSIC PHY power supply. Must supply 1.2 V.
+
+        pads:
+          properties:
+            usb2:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: USB2 tracking clock
+
+                clock-names:
+                  items:
+                    - const: trk
+
+                lanes:
+                  type: object
+                  properties:
+                    usb2-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            hsic:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: HSIC tracking clock
+
+                clock-names:
+                  items:
+                    - const: trk
+
+                lanes:
+                  type: object
+                  properties:
+                    hsic-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            usb3:
+              type: object
+              properties:
+                lanes:
+                  type: object
+                  properties:
+                    usb3-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb3-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb3-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+          additionalProperties: false
+
+        ports:
+          type: object
+          properties:
+            usb2-0:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-1:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-2:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            hsic-0:
+              type: object
+              properties:
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            usb3-0:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+            usb3-1:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+            usb3-2:
+              type: object
+              properties:
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+          additionalProperties: false
+
+      required:
+        - avdd-pll-erefeut-supply
+        - avdd-usb-supply
+        - vclamp-usb-supply
+        - vddio-hsic-supply
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra194-xusb-padctl
+    then:
+      properties:
+        reg:
+          items:
+            - description: pad controller registers
+            - description: AO registers
+          maxItems: 2
+
+        reg-names:
+          items:
+            - const: padctl
+            - const: ao
+
+        avdd-usb-supply:
+          description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
+            supply 3.3 V.
+
+        vclamp-usb-supply:
+          description: Bias rail for USB pad. Must supply 1.8 V.
+
+        pads:
+          properties:
+            usb2:
+              type: object
+              properties:
+                clocks:
+                  items:
+                    - description: USB2 tracking clock
+
+                clock-names:
+                  items:
+                    - const: trk
+
+                lanes:
+                  type: object
+                  properties:
+                    usb2-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+
+                    usb2-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb2-3:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+            usb3:
+              type: object
+              properties:
+                lanes:
+                  type: object
+                  properties:
+                    usb3-0:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb3-1:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb3-2:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                    usb3-3:
+                      type: object
+                      properties:
+                        "#phy-cells":
+                          const: 0
+
+                        nvidia,function:
+                          enum: [ xusb ]
+
+                        phandle:
+                          $ref: "/schemas/dt-core.yaml#/properties/phandle"
+
+                        status:
+                          $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                      additionalProperties: false
+
+                  additionalProperties: false
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+              additionalProperties: false
+
+          additionalProperties: false
+
+        ports:
+          properties:
+            usb2-0:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-1:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-2:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb2-3:
+              type: object
+              properties:
+                # no need to further describe this because the connector will
+                # match on gpio-usb-b-connector or usb-b-connector and cause
+                # that binding to be selected for the subnode
+                connector:
+                  type: object
+
+                mode:
+                  description: A string that determines the mode in which to
+                    run the port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  enum: [ host, peripheral, otg ]
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                usb-role-switch:
+                  description: |
+                    A boolean property whole presence indicates that the port
+                    supports OTG or peripheral mode. If present, the port
+                    supports switching between USB host and peripheral roles.
+                    A connector must be added as a subnode in that case.
+
+                    See ../connector/usb-connector.yaml.
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              dependencies:
+                usb-role-switch: [ connector ]
+
+              additionalProperties: false
+
+            usb3-0:
+              type: object
+              properties:
+                maximum-speed:
+                  description: A string property that specifies the maximum
+                    supported speed of a USB3 port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  oneOf:
+                    - description: The USB3 port supports USB 3.1 Gen 2 speed.
+                        This is the default.
+                      const: super-speed-plus
+                    - description: The USB3 port supports USB 3.1 Gen 1 speed
+                        only.
+                      const: super-speed
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-1:
+              type: object
+              properties:
+                maximum-speed:
+                  description: A string property that specifies the maximum
+                    supported speed of a USB3 port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  oneOf:
+                    - description: The USB3 port supports USB 3.1 Gen 2 speed.
+                        This is the default.
+                      const: super-speed-plus
+                    - description: The USB3 port supports USB 3.1 Gen 1 speed
+                        only.
+                      const: super-speed
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-2:
+              type: object
+              properties:
+                maximum-speed:
+                  description: A string property that specifies the maximum
+                    supported speed of a USB3 port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  oneOf:
+                    - description: The USB3 port supports USB 3.1 Gen 2 speed.
+                        This is the default.
+                      const: super-speed-plus
+                    - description: The USB3 port supports USB 3.1 Gen 1 speed
+                        only.
+                      const: super-speed
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+            usb3-3:
+              type: object
+              properties:
+                maximum-speed:
+                  description: A string property that specifies the maximum
+                    supported speed of a USB3 port.
+                  $ref: "/schemas/types.yaml#/definitions/string"
+                  oneOf:
+                    - description: The USB3 port supports USB 3.1 Gen 2 speed.
+                        This is the default.
+                      const: super-speed-plus
+                    - description: The USB3 port supports USB 3.1 Gen 1 speed
+                        only.
+                      const: super-speed
+
+                nvidia,internal:
+                  description: A boolean property whose presence determines
+                    that a port is internal. In the absence of this property
+                    the port is considered to be external.
+                  $ref: "/schemas/types.yaml#/definitions/flag"
+
+                nvidia,usb2-companion:
+                  description: A single cell that specifies the physical port
+                    number to map this super-speed USB port to. The range of
+                    valid port numbers varies with the SoC generation.
+                  enum: [ 0, 1, 2, 3 ]
+
+                status:
+                  $ref: "/schemas/dt-core.yaml#/properties/status"
+
+                vbus-supply:
+                  description: A phandle to the regulator supplying the VBUS
+                    voltage.
+
+              additionalProperties: false
+
+          additionalProperties: false
+
+      required:
+        - avdd-usb-supply
+        - vclamp-usb-supply
+
+unevaluatedProperties: false
+
+examples:
+  # Tegra124 and Tegra132
+  - |
+    padctl@7009f000 {
+        compatible = "nvidia,tegra124-xusb-padctl";
+        reg = <0x7009f000 0x1000>;
+        resets = <&tegra_car 142>;
+        reset-names = "padctl";
+
+        avdd-pll-utmip-supply = <&vddio_1v8>;
+        avdd-pll-erefe-supply = <&avdd_1v05_run>;
+        avdd-pex-pll-supply = <&vdd_1v05_run>;
+        hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+
+        pads {
+            usb2 {
+                lanes {
+                    usb2-0 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-1 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-2 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            ulpi {
+                lanes {
+                    ulpi-0 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            hsic {
+                lanes {
+                    hsic-0 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    hsic-1 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            pcie {
+                lanes {
+                    pcie-0 {
+                        nvidia,function = "usb3-ss";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-1 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-2 {
+                        nvidia,function = "pcie";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-3 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-4 {
+                        nvidia,function = "pcie";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            sata {
+                lanes {
+                    sata-0 {
+                        nvidia,function = "sata";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+        };
+
+        ports {
+            /* Micro A/B */
+            usb2-0 {
+                mode = "otg";
+            };
+
+            /* Mini PCIe */
+            usb2-1 {
+                mode = "host";
+            };
+
+            /* USB3 */
+            usb2-2 {
+                vbus-supply = <&vdd_usb3_vbus>;
+                mode = "host";
+            };
+
+            ulpi-0 {
+                status = "disabled";
+            };
+
+            hsic-0 {
+                status = "disabled";
+            };
+
+            hsic-1 {
+                status = "disabled";
+            };
+
+            usb3-0 {
+                nvidia,usb2-companion = <2>;
+            };
+
+            usb3-1 {
+                status = "disabled";
+            };
+        };
+    };
+
+  # Tegra210
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+
+    padctl@7009f000 {
+        compatible = "nvidia,tegra210-xusb-padctl";
+        reg = <0x7009f000 0x1000>;
+        resets = <&tegra_car 142>;
+        reset-names = "padctl";
+
+        avdd-pll-utmip-supply = <&vdd_1v8>;
+        avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
+        dvdd-pex-pll-supply = <&vdd_pex_1v05>;
+        hvdd-pex-pll-e-supply = <&vdd_1v8>;
+
+        pads {
+            usb2 {
+                clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
+                clock-names = "trk";
+
+                lanes {
+                    usb2-0 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-1 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-2 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-3 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            hsic {
+                clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
+                clock-names = "trk";
+                status = "disabled";
+
+                lanes {
+                    hsic-0 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    hsic-1 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            pcie {
+                clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
+                clock-names = "pll";
+                resets = <&tegra_car 205>;
+                reset-names = "phy";
+
+                lanes {
+                    pcie-0 {
+                        nvidia,function = "pcie-x1";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-1 {
+                        nvidia,function = "pcie-x4";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-2 {
+                        nvidia,function = "pcie-x4";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-3 {
+                        nvidia,function = "pcie-x4";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-4 {
+                        nvidia,function = "pcie-x4";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-5 {
+                        nvidia,function = "usb3-ss";
+                        #phy-cells = <0>;
+                    };
+
+                    pcie-6 {
+                        nvidia,function = "usb3-ss";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            sata {
+                clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
+                clock-names = "pll";
+                resets = <&tegra_car 204>;
+                reset-names = "phy";
+
+                lanes {
+                    sata-0 {
+                        nvidia,function = "sata";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+        };
+
+        ports {
+            usb2-0 {
+                mode = "peripheral";
+                usb-role-switch;
+
+                connector {
+                    compatible = "gpio-usb-b-connector",
+                                 "usb-b-connector";
+                    label = "micro-USB";
+                    type = "micro";
+                    vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
+                };
+            };
+
+            usb2-1 {
+                vbus-supply = <&vdd_5v0_rtl>;
+                mode = "host";
+            };
+
+            usb2-2 {
+                vbus-supply = <&vdd_usb_vbus>;
+                mode = "host";
+            };
+
+            usb2-3 {
+                mode = "host";
+            };
+
+            hsic-0 {
+                status = "disabled";
+            };
+
+            hsic-1 {
+                status = "disabled";
+            };
+
+            usb3-0 {
+                nvidia,usb2-companion = <1>;
+            };
+
+            usb3-1 {
+                nvidia,usb2-companion = <2>;
+            };
+
+            usb3-2 {
+                status = "disabled";
+            };
+
+            usb3-3 {
+                status = "disabled";
+            };
+        };
+    };
+
+  # Tegra186
+  - |
+    #include <dt-bindings/clock/tegra186-clock.h>
+    #include <dt-bindings/gpio/tegra186-gpio.h>
+    #include <dt-bindings/reset/tegra186-reset.h>
+
+    padctl@3520000 {
+        compatible = "nvidia,tegra186-xusb-padctl";
+        reg = <0x03520000 0x1000>,
+              <0x03540000 0x1000>;
+        reg-names = "padctl", "ao";
+
+        resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
+        reset-names = "padctl";
+
+        avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
+        avdd-usb-supply = <&vdd_3v3_sys>;
+        vclamp-usb-supply = <&vdd_1v8>;
+        vddio-hsic-supply = <&gnd>;
+
+        pads {
+            usb2 {
+                clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
+                clock-names = "trk";
+
+                lanes {
+                    usb2-0 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-1 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-2 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            hsic {
+                clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
+                clock-names = "trk";
+                status = "disabled";
+
+                lanes {
+                    hsic-0 {
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            usb3 {
+                lanes {
+                    usb3-0 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb3-1 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb3-2 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+        };
+
+        ports {
+            usb2-0 {
+                mode = "otg";
+                vbus-supply = <&vdd_usb0>;
+                usb-role-switch;
+
+                connector {
+                    compatible = "gpio-usb-b-connector",
+                                 "usb-b-connector";
+                    label = "micro-USB";
+                    type = "micro";
+                    vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(X, 7) GPIO_ACTIVE_LOW>;
+                    id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
+                };
+            };
+
+            usb2-1 {
+                vbus-supply = <&vdd_usb1>;
+                mode = "host";
+            };
+
+            usb2-2 {
+                status = "disabled";
+            };
+
+            hsic-0 {
+                status = "disabled";
+            };
+
+            usb3-0 {
+                nvidia,usb2-companion = <1>;
+            };
+
+            usb3-1 {
+                status = "disabled";
+            };
+
+            usb3-2 {
+                status = "disabled";
+            };
+        };
+    };
+
+  # Tegra194
+  - |
+    #include <dt-bindings/clock/tegra194-clock.h>
+    #include <dt-bindings/gpio/tegra194-gpio.h>
+    #include <dt-bindings/reset/tegra194-reset.h>
+
+    padctl@3520000 {
+        compatible = "nvidia,tegra194-xusb-padctl";
+        reg = <0x03520000 0x1000>,
+              <0x03540000 0x1000>;
+        reg-names = "padctl", "ao";
+
+        resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
+        reset-names = "padctl";
+
+        avdd-usb-supply = <&vdd_usb_3v3>;
+        vclamp-usb-supply = <&vdd_1v8ao>;
+
+        pads {
+            usb2 {
+                clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
+                clock-names = "trk";
+
+                lanes {
+                    usb2-0 {
+                        nvidia,function = "xusb";
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-1 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-2 {
+                        nvidia,function = "xusb";
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    usb2-3 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+
+            usb3 {
+                lanes {
+                    usb3-0 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+
+                    usb3-1 {
+                        nvidia,function = "xusb";
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    usb3-2 {
+                        nvidia,function = "xusb";
+                        status = "disabled";
+                        #phy-cells = <0>;
+                    };
+
+                    usb3-3 {
+                        nvidia,function = "xusb";
+                        #phy-cells = <0>;
+                    };
+                };
+            };
+        };
+
+        ports {
+            usb2-0 {
+                status = "disabled";
+            };
+
+            usb2-1 {
+                vbus-supply = <&vdd_5v0_sys>;
+                mode = "host";
+            };
+
+            usb2-2 {
+                status = "disabled";
+            };
+
+            usb2-3 {
+                vbus-supply = <&vdd_5v_sata>;
+                mode = "host";
+            };
+
+            usb3-0 {
+                vbus-supply = <&vdd_5v0_sys>;
+                nvidia,usb2-companion = <1>;
+            };
+
+            usb3-1 {
+                status = "disabled";
+            };
+
+            usb3-2 {
+                status = "disabled";
+            };
+
+            usb3-3 {
+                maximum-speed = "super-speed";
+                vbus-supply = <&vdd_5v0_sys>;
+                nvidia,usb2-companion = <3>;
+            };
+        };
+    };
-- 
2.24.1

^ permalink raw reply related

* [PATCH 29/38] dt-bindings: tegra: pmc: Increase clock limit for power domains
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Power domains (such as the SOR domain) can have more than 8 clocks. Bump
the limit to 10 which is enough as of now.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 81534d04094b..881bfc6154e2 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -213,7 +213,7 @@ properties:
         patternProperties:
           clocks:
             minItems: 1
-            maxItems: 8
+            maxItems: 10
             description:
               Must contain an entry for each clock required by the PMC
               for controlling a power-gate.
-- 
2.24.1

^ permalink raw reply related

* [PATCH 30/38] dt-bindings: panel: Allow reg property for DSI panels
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

For DSI panels the "reg" property is needed to represent the virtual
channel of the given panel.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/display/panel/panel-simple.yaml        | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
index d6cca1479633..34fe3d42b829 100644
--- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
@@ -267,6 +267,9 @@ properties:
         # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
       - winstar,wf35ltiacd
 
+  reg:
+    description: virtual channel for DSI panels
+
   backlight: true
   enable-gpios: true
   port: true
-- 
2.24.1

^ permalink raw reply related

* [PATCH 31/38] dt-bindings: panel: simple: Use unevaluatedProperties
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Using "additionalProperties: false" results in rejecting any of the
properties defined in panel-common.yaml, whereas the intent is to
inherit the common properties defined in that file.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/display/panel/panel-simple.yaml         | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
index 34fe3d42b829..c58bc90ffd43 100644
--- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
@@ -275,7 +275,7 @@ properties:
   port: true
   power-supply: true
 
-additionalProperties: false
+unevaluatedProperties: false
 
 required:
   - compatible
-- 
2.24.1

^ permalink raw reply related

* [PATCH 32/38] dt-bindings: leds: Document rfkill* trigger
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

LEDs can use rfkill events as a trigger source, so document these in the
device tree bindings.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/leds/common.yaml        | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml
index a2a541bca73c..6619d1ff1031 100644
--- a/Documentation/devicetree/bindings/leds/common.yaml
+++ b/Documentation/devicetree/bindings/leds/common.yaml
@@ -79,24 +79,25 @@ properties:
       the LED.
     $ref: /schemas/types.yaml#definitions/string
 
-    enum:
+    oneOf:
         # LED will act as a back-light, controlled by the framebuffer system
-      - backlight
+      - const: backlight
         # LED will turn on (but for leds-gpio see "default-state" property in
         # Documentation/devicetree/bindings/leds/leds-gpio.yaml)
-      - default-on
+      - const: default-on
         # LED "double" flashes at a load average based rate
-      - heartbeat
+      - const: heartbeat
         # LED indicates disk activity
-      - disk-activity
+      - const: disk-activity
         # LED indicates IDE disk activity (deprecated), in new implementations
         # use "disk-activity"
-      - ide-disk
+      - const: ide-disk
         # LED flashes at a fixed, configurable rate
-      - timer
+      - const: timer
         # LED alters the brightness for the specified duration with one software
         # timer (requires "led-pattern" property)
-      - pattern
+      - const: pattern
+      - pattern: "^rfkill[0-9]+$"
 
   led-pattern:
     description: |
-- 
2.24.1

^ permalink raw reply related

* [PATCH 33/38] dt-bindings: memory-controller: Document Tegra132 EMC
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Document the compatible string for the Tegra132 variant of the external
memory controller.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/memory-controllers/nvidia,tegra124-emc.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
index 278549f9e051..122134f0a08b 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
@@ -16,7 +16,9 @@ description: |
 
 properties:
   compatible:
-    const: nvidia,tegra124-emc
+    enum:
+      - nvidia,tegra124-emc
+      - nvidia,tegra132-emc
 
   reg:
     maxItems: 1
-- 
2.24.1

^ permalink raw reply related

* [PATCH 34/38] dt-bindings: memory-controller: Fix "reg" entries on Tegra194
From: Thierry Reding @ 2020-06-12 14:18 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The Tegra194 memory controller needs a couple more "reg" entries.
Document this properly so that device trees can be validated.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../nvidia,tegra186-mc.yaml                   | 39 ++++++++++++++-----
 1 file changed, 29 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 774b04d0da0d..b04485c5cf5f 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -27,13 +27,15 @@ properties:
     pattern: "^memory-controller@[0-9a-f]+$"
 
   compatible:
-    items:
-      - enum:
-          - nvidia,tegra186-mc
-          - nvidia,tegra194-mc
+    oneOf:
+      - description: NVIDIA Tegra186 memory controller
+        const: nvidia,tegra186-mc
+      - description: NVIDIA Tegra194 memory controller
+        const: nvidia,tegra194-mc
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
 
   interrupts:
     maxItems: 1
@@ -74,12 +76,13 @@ patternProperties:
               - nvidia,tegra186-emc
               - nvidia,tegra194-emc
 
-      reg:
-        maxItems: 1
-
       interrupts:
         maxItems: 1
 
+      reg:
+        minItems: 1
+        maxItems: 2
+
       clocks:
         items:
           - description: external memory clock
@@ -107,11 +110,18 @@ allOf:
       properties:
         compatible:
           contains:
-            const: nvidia,tegra194-mc
+            anyOf:
+              - const: nvidia,tegra194-mc
     then:
       properties:
         reg:
+          minItems: 3
           maxItems: 3
+    else:
+      properties:
+        reg:
+          minItems: 1
+          maxItems: 1
 
   - if:
       patternProperties:
@@ -119,13 +129,22 @@ allOf:
           properties:
             compatible:
               contains:
-                const: nvidia,tegra194-emc
+                anyOf:
+                  - const: nvidia,tegra194-emc
     then:
       patternProperties:
         "^external-memory-controller@[0-9a-f]+$":
           properties:
             reg:
+              minItems: 2
               maxItems: 2
+    else:
+      patternProperties:
+        "^external-memory-controller@[0-9a-f]+$":
+          properties:
+            reg:
+              minItems: 1
+              maxItems: 1
 
 examples:
   - |
-- 
2.24.1

^ permalink raw reply related

* [PATCH 35/38] dt-bindings: memory: Update Tegra210 EMC bindings
From: Thierry Reding @ 2020-06-12 14:19 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The Tegra210 EMC is a cooling device because it can throttle the EMC
frequency if the chip gets too hot. The device tree node therefore needs
to contain the "#cooling-cells" property. Furthermore, multiple reserved
memory regions can now be attached to the EMC device tree node, and the
new memory-region-names property can be used to differentiate between
them.

While at it, update the example to make it more fully-featured.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../nvidia,tegra210-emc.yaml                  | 34 ++++++++++++++-----
 1 file changed, 26 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
index 49ab09252e52..4e8f659f1a7c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
@@ -34,16 +34,25 @@ properties:
       - description: EMC general interrupt
 
   memory-region:
-    $ref: /schemas/types.yaml#/definitions/phandle
-    description:
-      phandle to a reserved memory region describing the table of EMC
-      frequencies trained by the firmware
+    description: List of phandles to reserved memory regions describing the
+      nominal and derated tables of EMC frequencies trained by the firmware.
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+  memory-region-names:
+    $ref: "/schemas/types.yaml#/definitions/string-array"
+    items:
+      - const: nominal
+      - const: derated
 
   nvidia,memory-controller:
-    $ref: /schemas/types.yaml#/definitions/phandle
+    $ref: "/schemas/types.yaml#/definitions/phandle"
     description:
       phandle of the memory controller node
 
+  "#cooling-cells":
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    const: 2
+
 required:
   - compatible
   - reg
@@ -51,7 +60,10 @@ required:
   - clock-names
   - nvidia,memory-controller
 
-additionalProperties: false
+dependencies:
+  memory-region-names: [ memory-region ]
+
+unevaluatedProperties: false
 
 examples:
   - |
@@ -63,10 +75,15 @@ examples:
         #size-cells = <1>;
         ranges;
 
-        emc_table: emc-table@83400000 {
+        nominal: emc-table@83400000 {
             compatible = "nvidia,tegra210-emc-table";
             reg = <0x83400000 0x10000>;
         };
+
+        derated: emc-table@83410000 {
+            compatible = "nvidia,tegar210-emc-table";
+            reg = <0x83410000 0x10000>;
+        };
     };
 
     external-memory-controller@7001b000 {
@@ -77,6 +94,7 @@ examples:
         clocks = <&tegra_car TEGRA210_CLK_EMC>;
         clock-names = "emc";
         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-        memory-region = <&emc_table>;
+        memory-region-names = "nominal", "derated";
+        memory-region = <&nominal>, <&derated>;
         nvidia,memory-controller = <&mc>;
     };
-- 
2.24.1

^ permalink raw reply related

* [PATCH 36/38] dt-bindings: power: supply: sbs-battery: Document TI BQ20Z45 compatible
From: Thierry Reding @ 2020-06-12 14:19 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The TI BQ20Z45 battery is used for example on Tegra114 Dalmore but was
never documented. Add the missing compatible string.

While at it, also pull in the power-supply.yaml core bindings so that
the standard power-supplies property is properly validated. Also switch
to unevaluatedProperties to make sure the power-supply.yaml snippet is
properly validated against (additionalProperties doesn't have visibility
across a $ref).

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/power/supply/sbs,sbs-battery.yaml   | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/power/supply/sbs,sbs-battery.yaml b/Documentation/devicetree/bindings/power/supply/sbs,sbs-battery.yaml
index 205bc826bd20..bb2803850ea6 100644
--- a/Documentation/devicetree/bindings/power/supply/sbs,sbs-battery.yaml
+++ b/Documentation/devicetree/bindings/power/supply/sbs,sbs-battery.yaml
@@ -18,6 +18,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - ti,bq20z45
               - ti,bq20z65
               - ti,bq20z75
           - enum:
@@ -62,7 +63,10 @@ required:
   - compatible
   - reg
 
-additionalProperties: false
+allOf:
+  - $ref: power-supply.yaml#
+
+unevaluatedProperties: false
 
 examples:
   - |
-- 
2.24.1

^ permalink raw reply related

* [PATCH 37/38] dt-bindings: pwm: Explicitly include pwm.yaml
From: Thierry Reding @ 2020-06-12 14:19 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

For PWM controller device tree bindings, make sure that they include the
pwm.yaml controller core bindings explicitly. This prevents the tooling
from matching on the $nodename pattern, which can falsely match things
like pinmux nodes, etc.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 51 ++++++++++---------
 .../bindings/pwm/google,cros-ec-pwm.yaml      |  4 +-
 .../devicetree/bindings/pwm/iqs620a-pwm.yaml  |  4 +-
 .../devicetree/bindings/pwm/pwm-samsung.yaml  |  1 -
 .../devicetree/bindings/pwm/pwm.yaml          |  2 +
 .../bindings/pwm/renesas,pwm-rcar.yaml        |  4 +-
 .../bindings/pwm/renesas,tpu-pwm.yaml         |  4 +-
 7 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 7dcab2bf8128..0a7e70114af0 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -50,33 +50,34 @@ properties:
   resets:
     maxItems: 1
 
-if:
-  properties:
-    compatible:
-      contains:
-        const: allwinner,sun50i-h6-pwm
-
-then:
-  properties:
-    clocks:
-      maxItems: 2
-
-    clock-names:
-      items:
-        - const: mod
-        - const: bus
-
-  required:
-    - clock-names
-    - resets
-
-else:
-  properties:
-    clocks:
-      maxItems: 1
+allOf:
+  - $ref: pwm.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: allwinner,sun50i-h6-pwm
+
+    then:
+      properties:
+        clocks:
+          maxItems: 2
+
+        clock-names:
+          items:
+            - const: mod
+            - const: bus
+
+      required:
+        - clock-names
+        - resets
+
+    else:
+      properties:
+        clocks:
+          maxItems: 1
 
 required:
-  - "#pwm-cells"
   - compatible
   - reg
   - clocks
diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml
index 41ece1d85315..a5a1e4f3df48 100644
--- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml
@@ -25,7 +25,9 @@ properties:
 
 required:
   - compatible
-  - '#pwm-cells'
+
+allOf:
+  - $ref: pwm.yaml#
 
 additionalProperties: false
 
diff --git a/Documentation/devicetree/bindings/pwm/iqs620a-pwm.yaml b/Documentation/devicetree/bindings/pwm/iqs620a-pwm.yaml
index 1d7c27be50da..a375cc9e8fd0 100644
--- a/Documentation/devicetree/bindings/pwm/iqs620a-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/iqs620a-pwm.yaml
@@ -25,7 +25,9 @@ properties:
 
 required:
   - compatible
-  - "#pwm-cells"
+
+allOf:
+  - $ref: pwm.yaml#
 
 additionalProperties: false
 
diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
index fc799b0577d4..e1487194d9a7 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
@@ -89,7 +89,6 @@ required:
   - clock-names
   - compatible
   - interrupts
-  - "#pwm-cells"
   - reg
 
 additionalProperties: false
diff --git a/Documentation/devicetree/bindings/pwm/pwm.yaml b/Documentation/devicetree/bindings/pwm/pwm.yaml
index fa4f9de92090..b0ebd2881a91 100644
--- a/Documentation/devicetree/bindings/pwm/pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm.yaml
@@ -9,6 +9,8 @@ title: PWM controllers (providers)
 maintainers:
   - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
 
+select: false
+
 properties:
   $nodename:
     pattern: "^pwm(@.*|-[0-9a-f])*$"
diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
index daadde9ff9c4..d2cc1226f309 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
@@ -57,9 +57,11 @@ properties:
 required:
   - compatible
   - reg
-  - '#pwm-cells'
   - clocks
 
+allOf:
+  - $ref: pwm.yaml#
+
 additionalProperties: false
 
 examples:
diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
index 4bf62a3d5bba..0db96f38ab0a 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
@@ -56,7 +56,9 @@ properties:
 required:
   - compatible
   - reg
-  - '#pwm-cells'
+
+allOf:
+  - $ref: pwm.yaml#
 
 additionalProperties: false
 
-- 
2.24.1

^ permalink raw reply related

* [PATCH 38/38] dt-bindings: serial: Document Tegra-specific properties
From: Thierry Reding @ 2020-06-12 14:19 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

On Tegra the UART is described using additional properties, such as
clock-names, reset-names, dmas and dma-names. Document them in the
bindings so that Tegra device trees are properly validated.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/serial/8250.yaml      | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index c1d4c196f005..9c8fad27c3f3 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -28,6 +28,32 @@ allOf:
           const: 2
       required:
         - reg-shift
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-uart
+    then:
+      properties:
+        clock-names:
+          $ref: "/schemas/types.yaml#/definitions/string-array"
+          items:
+            - const: serial
+
+        dmas:
+          $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+        dma-names:
+          $ref: "/schemas/types.yaml#/definitions/string-array"
+          items:
+            - const: rx
+            - const: tx
+
+        reset-names:
+          $ref: "/schemas/types.yaml#/definitions/string-array"
+          items:
+            - const: serial
   - if:
       not:
         properties:
-- 
2.24.1

^ permalink raw reply related

* Re: [PATCH 31/38] dt-bindings: panel: simple: Use unevaluatedProperties
From: Rob Herring @ 2020-06-12 14:28 UTC (permalink / raw)
  To: Thierry Reding; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-tegra
In-Reply-To: <20200612141903.2391044-32-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On Fri, Jun 12, 2020 at 8:20 AM Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Using "additionalProperties: false" results in rejecting any of the
> properties defined in panel-common.yaml, whereas the intent is to
> inherit the common properties defined in that file.
>
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../devicetree/bindings/display/panel/panel-simple.yaml         | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> index 34fe3d42b829..c58bc90ffd43 100644
> --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> @@ -275,7 +275,7 @@ properties:
>    port: true
>    power-supply: true
>
> -additionalProperties: false
> +unevaluatedProperties: false

But we've listed the properties we use here. Some of the common ones
may not be applicable. Maybe they are and if so, then you should drop
all the ones listed with 'true' with this change.

Rob

^ permalink raw reply

* Re: [PATCH 30/38] dt-bindings: panel: Allow reg property for DSI panels
From: Rob Herring @ 2020-06-12 14:29 UTC (permalink / raw)
  To: Thierry Reding; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-tegra
In-Reply-To: <20200612141903.2391044-31-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On Fri, Jun 12, 2020 at 8:20 AM Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> For DSI panels the "reg" property is needed to represent the virtual
> channel of the given panel.
>
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../devicetree/bindings/display/panel/panel-simple.yaml        | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> index d6cca1479633..34fe3d42b829 100644
> --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> @@ -267,6 +267,9 @@ properties:
>          # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
>        - winstar,wf35ltiacd
>
> +  reg:
> +    description: virtual channel for DSI panels
> +

panel-simple-dsi.yaml?

>    backlight: true
>    enable-gpios: true
>    port: true
> --
> 2.24.1
>

^ permalink raw reply

* [PATCH 1/2] gpu: host1x: Register child devices
From: Thierry Reding @ 2020-06-12 15:00 UTC (permalink / raw)
  To: Thierry Reding
  Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

In order to remove the dependency on the simple-bus compatible string,
which causes the OF driver core to register all child devices, make the
host1x driver explicitly register its children.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/gpu/host1x/dev.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 3c0f151847ba..d0ebb70e2fdd 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -470,8 +470,14 @@ static int host1x_probe(struct platform_device *pdev)
 	if (err < 0)
 		goto deinit_debugfs;
 
+	err = devm_of_platform_populate(&pdev->dev);
+	if (err < 0)
+		goto unregister;
+
 	return 0;
 
+unregister:
+	host1x_unregister(host);
 deinit_debugfs:
 	host1x_debug_deinit(host);
 	host1x_intr_deinit(host);
-- 
2.24.1

^ permalink raw reply related

* [PATCH 2/2] drm/tegra: hub: Register child devices
From: Thierry Reding @ 2020-06-12 15:01 UTC (permalink / raw)
  To: Thierry Reding
  Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612150100.2419935-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

In order to remove the dependency on the simple-bus compatible string,
which causes the OF driver core to register all child devices, make the
display-hub driver explicitly register the display controller children.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/gpu/drm/tegra/hub.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c
index a2ef8f218d4e..22a03f7ffdc1 100644
--- a/drivers/gpu/drm/tegra/hub.c
+++ b/drivers/gpu/drm/tegra/hub.c
@@ -948,6 +948,15 @@ static int tegra_display_hub_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "failed to register host1x client: %d\n",
 			err);
 
+	err = devm_of_platform_populate(&pdev->dev);
+	if (err < 0)
+		goto unregister;
+
+	return err;
+
+unregister:
+	host1x_client_unregister(&hub->client);
+	pm_runtime_disable(&pdev->dev);
 	return err;
 }
 
-- 
2.24.1

^ permalink raw reply related

* Re: [PATCH] ARM: tegra: Fix restoration of PLLM when exiting suspend
From: Dmitry Osipenko @ 2020-06-12 15:20 UTC (permalink / raw)
  To: Jon Hunter, Thierry Reding
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA, stable-u79uwXL29TY76Z2rM5mHXA,
	Peter De Schrijver
In-Reply-To: <57264acd-2623-9e9f-53c6-3b4cd3991315-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

17.12.2019 17:28, Dmitry Osipenko пишет:
> 17.12.2019 17:19, Jon Hunter пишет:
>>
>> On 10/12/2019 20:29, Dmitry Osipenko wrote:
>>> 10.12.2019 22:28, Dmitry Osipenko пишет:
>>>> Hello Jon,
>>>>
>>>> 10.12.2019 13:37, Jon Hunter пишет:
>>>>> The suspend entry and exit code for 32-bit Tegra devices assumes that
>>>>> the PLLM (which is used to provide the clock for external memory)
>>>>> is always enabled on entry to suspend. Hence, the current code always
>>>>> disables the PLLM on entry to suspend and re-enables the PLLM on exit
>>>>> from suspend.
>>>>>
>>>>> Since the introduction of the Tegra124 EMC driver by commit 73a7f0a90641
>>>>> ("memory: tegra: Add EMC (external memory controller) driver"), which is
>>>>> used to scale the EMC frequency, PLLM may not be the current clock
>>>>> source for the EMC on entry to suspend and hence may not be enabled.
>>>>> Always enabling the PLLM on exit from suspend can cause the actual
>>>>> status on the PLL to be different from that reported by the common clock
>>>>> framework.
>>>>>
>>>>> On kernels prior to v4.5, the code to set the rate of the PLLM had a
>>>>> test to verify if the PLL was enabled and if the PLL was enabled,
>>>>> setting the rate would fail. Since commit 267b62a96951
>>>>> ("clk: tegra: pll: Update PLLM handling") the test to see if PLLM is
>>>>> enabled was removed.
>>>>>
>>>>> With these earlier kernels, if the PLLM is disabled on entering suspend
>>>>> and the EMC driver attempts to set the parent of the EMC clock to the
>>>>> PLLM on exiting suspend, then the set rate for the PLLM will fail and in
>>>>> turn cause the resume to fail.
>>>>>
>>>>> We should not be re-enabling the PLLM on resume from suspend unless it
>>>>> was enabled on entry to suspend. Therefore, fix this by saving the state
>>>>> of PLLM on entry to suspend and only re-enable it, if it was already
>>>>> enabled.
>>>>>
>>>>> Fixes: 73a7f0a90641 ("memory: tegra: Add EMC (external memory controller) driver")
>>>>> Cc: stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>>>>
>>>>> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>>>> ---
>>>>>  arch/arm/mach-tegra/sleep-tegra30.S | 33 +++++++++++++++++++++++------
>>>>>  1 file changed, 27 insertions(+), 6 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
>>>>> index 3341a12bbb9c..c2f0793a424f 100644
>>>>> --- a/arch/arm/mach-tegra/sleep-tegra30.S
>>>>> +++ b/arch/arm/mach-tegra/sleep-tegra30.S
>>>>> @@ -337,26 +337,42 @@ ENTRY(tegra30_lp1_reset)
>>>>>  	add	r1, r1, #2
>>>>>  	wait_until r1, r7, r3
>>>>>  
>>>>> -	/* enable PLLM via PMC */
>>>>> +	/* restore PLLM state */
>>>>>  	mov32	r2, TEGRA_PMC_BASE
>>>>> +	adr	r7, tegra_pllm_status
>>>>> +	ldr	r1, [r7]
>>>>> +	cmp	r2, #(1 << 12)
>>>>> +	bne	_skip_pllm
>>>>> +
>>>>>  	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
>>>>>  	orr	r1, r1, #(1 << 12)
>>>>>  	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
>>>>>  
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
>>>>> +	pll_locked r1, r0, CLK_RESET_PLLM_BASE
>>>>> +
>>>>> +_skip_pllm:
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
>>>>>  
>>>>>  	b	_pll_m_c_x_done
>>>>>  
>>>>>  _no_pll_iddq_exit:
>>>>> -	/* enable PLLM via PMC */
>>>>> +	/* restore PLLM state */
>>>>>  	mov32	r2, TEGRA_PMC_BASE
>>>>> +	adr	r7, tegra_pllm_status
>>>>> +	ldr	r1, [r7]
>>>>> +	cmp	r2, #(1 << 12)
>>>>> +	bne	_skip_pllm_no_iddq
>>>>> +
>>>>>  	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
>>>>>  	orr	r1, r1, #(1 << 12)
>>>>>  	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
>>>>>  
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
>>>>> +	pll_locked r1, r0, CLK_RESET_PLLM_BASE
>>>>> +
>>>>> +_skip_pllm_no_iddq:
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
>>>>>  
>>>>> @@ -364,7 +380,6 @@ _pll_m_c_x_done:
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
>>>>>  	pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
>>>>>  
>>>>> -	pll_locked r1, r0, CLK_RESET_PLLM_BASE
>>>>>  	pll_locked r1, r0, CLK_RESET_PLLP_BASE
>>>>>  	pll_locked r1, r0, CLK_RESET_PLLA_BASE
>>>>>  	pll_locked r1, r0, CLK_RESET_PLLC_BASE
>>>>> @@ -526,6 +541,8 @@ __no_dual_emc_chanl:
>>>>>  ENDPROC(tegra30_lp1_reset)
>>>>>  
>>>>>  	.align	L1_CACHE_SHIFT
>>>>> +tegra_pllm_status:
>>>>> +	.word	0
>>>>>  tegra30_sdram_pad_address:
>>>>>  	.word	TEGRA_EMC_BASE + EMC_CFG				@0x0
>>>>>  	.word	TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
>>>>> @@ -624,10 +641,14 @@ tegra30_switch_cpu_to_clk32k:
>>>>>  	add	r1, r1, #2
>>>>>  	wait_until r1, r7, r9
>>>>
>>>>
>>>>> -	/* disable PLLM via PMC in LP1 */
>>>>> +	/* disable PLLM, if enabled, via PMC in LP1 */
>>>>> +	adr	r1, tegra_pllm_status
>>>>>  	ldr	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
>>>>> -	bic	r0, r0, #(1 << 12)
>>>>> -	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
>>>>> +	and	r2, r0, #(1 << 12)
>>>>> +	str     r2, [r1]
>>>>> +	cmp	r2, #(1 << 12)
>>>>> +	biceq	r0, r0, #(1 << 12)
>>>>> +	streq	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
>>>>>  
>>>>>  	/* disable PLLP, PLLA, PLLC and PLLX */
>>>>>  	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
>>>>
>>>> PLLM's enable-status could be defined either by PMC or CaR. Thus at
>>>> first you need to check whether PMC overrides CaR's enable and then
>>>> judge the enable state based on PMC or CaR state respectively.
>>>>
>>>
>>> Actually, now I think that it doesn't make sense to check PMC WB0 state
>>> at all. IIUC, PLLM's state of the WB0 register defines whether Boot ROM
>>> should enable PLLM on resume from suspend. Thus it will be correct to
>>> check only the CaR's enable-state of PLLM.
>>
>> Thanks for pointing this out and sorry for the delay. However, I am not
>> sure I agree that we should not check this at all. If the override bit
>> is set, then we do want to check the state from the PMC register and if
>> it is not then we should just use the PLLM register itself.
> 
> Sorry if I wasn't clear.. my point is that the PMC's override register
> bit doesn't reflect the PLLM's enable-state. The PLLM could be disabled
> while PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE bit is set.
> 
> The CaR's PLLM enable-state reflects the actual hardware state. At least
> that's what I see on T30.
> 
>>> Looks like it is a bit of nonsense that clk_pll_is_enabled() checks
>>> PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE for judging of the enable-state. This
>>> is not the first time I'm getting confused by it, perhaps will be
>>> worthwhile to clean up that part of the clk driver's code (if I'm not
>>> missing something).
>>
>> That code looks fine to me. I just think this code entering and exiting
>> suspend needs to be fixed. I will re-work this fix.

Hello, Jon! Do you have any plans to continue working on this patch? A
day ago I sent out patch that improves PLLM handling within the clk
driver [1], will be great if the resume from suspend could be improved
as well! :)

[1]
https://patchwork.ozlabs.org/project/linux-tegra/patch/20200610163738.29304-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org/

^ permalink raw reply

* Re: [PATCH 08/38] dt-bindings: display: tegra: Document interconnect paths
From: Dmitry Osipenko @ 2020-06-12 15:52 UTC (permalink / raw)
  To: Thierry Reding, Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-9-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Hello Thierry,

12.06.2020 17:18, Thierry Reding пишет:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Commit description is missing, checkpatch should warn about it.

> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../display/tegra/nvidia,tegra20-host1x.yaml  | 52 ++++++++++++++++---
>  1 file changed, 46 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
> index 3347e1b3c8f0..684fe25641f1 100644
> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
> @@ -97,8 +97,17 @@ properties:
>    iommus:
>      $ref: "/schemas/iommu/iommu.yaml#/properties/iommus"
>  
> -  memory-controllers:
> -    $ref: /schemas/types.yaml#/definitions/phandle-array

Why memory-controllers property is removed?

> +  interconnects:
> +    description: Description of the interconnect paths for the host1x
> +      controller; see ../interconnect/interconnect.txt for details.
> +    items:
> +      - description: memory read client for host1x
> +
> +  interconnect-names:
> +    description: A list of names identifying each entry listed in the
> +      "interconnects" property.
> +    items:
> +      - const: dma-mem # read

Please notice that Host1x has two memory clients: one for DMA engine and
second I don't know what's for, maybe for indirect memory accesses. Why
you skipped the second path?

>  required:
>    - compatible
> @@ -489,6 +498,26 @@ allOf:
>              iommus:
>                $ref: "/schemas/types.yaml#/definitions/phandle-array"
>  
> +            #interconnects:
> +            #  items:
> +            #    - description: memory read client for window A
> +            #    - description: memory read client for window B
> +            #    - description: memory read client for window C
> +            #    - description: memory read client for cursor
> +            #    # disp only
> +            #    - description: memory read client for window T
> +            #    - description: memory read client for window D
> +
> +            #interconnect-names:
> +            #  items:
> +            #    - const: wina
> +            #    - const: winb
> +            #    - const: winc
> +            #    - const: cursor
> +            #    # disp only
> +            #    - const: wint
> +            #    - const: wind

Is this really intended to be commented out? Looks like this is an
unfinished patch.

In the patch [1] I used memory client names for the interconnect paths.
I like yours variant of the naming, it is more intuitive.

[1]
https://patchwork.ozlabs.org/project/linux-tegra/patch/20200609131404.17523-23-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org/

I'll rebase my series on top of yours patches once you'll get them into
linux-next. Looking forward to v2!

^ permalink raw reply

* Re: [PATCH 07/38] dt-bindings: display: tegra: Convert to json-schema
From: Dmitry Osipenko @ 2020-06-12 15:54 UTC (permalink / raw)
  To: Thierry Reding, Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200612141903.2391044-8-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

12.06.2020 17:18, Thierry Reding пишет:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Convert the Tegra host1x controller bindings from the free-form text
> format to json-schema.
> 
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
...
> +  memory-controllers:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> +required:
> +  - compatible
> +  - interrupts
> +  - interrupt-names
> +  - '#address-cells'
> +  - '#size-cells'
> +  - ranges
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names

This memory-controllers property didn't exist before the conversion. So
this is not a pure conversion, which makes it a bit difficult to review
the changes. Could you please factor out the addition of new properties
into a separate patch?

^ permalink raw reply

* [PATCH 1/8] drm/atomic-helper: reset vblank on crtc reset
From: Daniel Vetter @ 2020-06-12 16:00 UTC (permalink / raw)
  To: DRI Development
  Cc: Intel Graphics Development, Daniel Vetter, Laurent Pinchart,
	Boris Brezillon, Liviu Dudau, Thierry Reding, Tetsuo Handa,
	syzbot+0871b14ca2e2fb64f6e3, James (Qian) Wang, Mihail Atanassov,
	Brian Starkey, Sam Ravnborg, Boris Brezillon, Nicolas Ferre,
	Alexandre Belloni, Ludovic Desroches,
	Maarten Lankhorst <maarten.lank>

Only when vblanks are supported ofc.

Some drivers do this already, but most unfortunately missed it. This
opens up bugs after driver load, before the crtc is enabled for the
first time. syzbot spotted this when loading vkms as a secondary
output. Given how many drivers are buggy it's best to solve this once
and for all in shared helper code.

Aside from moving the few existing calls to drm_crtc_vblank_reset into
helpers (i915 doesn't use helpers, so keeps its own) I think the
regression risk is minimal: atomic helpers already rely on drivers
calling drm_crtc_vblank_on/off correctly in their hooks when they
support vblanks. And driver that's failing to handle vblanks after
this is missing those calls already, and vblanks could only work by
accident when enabling a CRTC for the first time right after boot.

Big thanks to Tetsuo for helping track down what's going wrong here.

There's only a few drivers which already had the necessary call and
needed some updating:
- komeda, atmel and tidss also needed to be changed to call
  __drm_atomic_helper_crtc_reset() intead of open coding it
- tegra and msm even had it in the same place already, just code
  motion, and malidp already uses __drm_atomic_helper_crtc_reset().

Only call left is in i915, which doesn't use drm_mode_config_reset,
but has its own fastboot infrastructure. So that's the only case where
we actually want this in the driver still.

I've also reviewed all other drivers which set up vblank support with
drm_vblank_init. After the previous patch fixing mxsfb all atomic
drivers do call drm_crtc_vblank_on/off as they should, the remaining
drivers are either legacy kms or legacy dri1 drivers, so not affected
by this change to atomic helpers.

v2: Use the drm_dev_has_vblank() helper.

v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off
instead of drm_crtc_vblank_reset. Adjust them too.

v4: Laurent noticed that rcar-du and omap open-code their crtc reset
and hence would actually be broken by this patch now. So fix them up
by reusing the helpers, which brings the drm_crtc_vblank_reset() back.

Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb
Reported-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Reported-by: syzbot+0871b14ca2e2fb64f6e3@syzkaller.appspotmail.com
Cc: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Cc: "James (Qian) Wang" <james.qian.wang@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mihail Atanassov <mihail.atanassov@arm.com>
Cc: Brian Starkey <brian.starkey@arm.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Jyri Sarha <jsarha@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Brian Masney <masneyb@onstation.org>
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: zhengbin <zhengbin13@huawei.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-tegra@vger.kernel.org
Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++-----
 drivers/gpu/drm/arm/malidp_drv.c                 | 1 -
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c   | 7 ++-----
 drivers/gpu/drm/drm_atomic_state_helper.c        | 4 ++++
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c        | 2 --
 drivers/gpu/drm/omapdrm/omap_crtc.c              | 8 +++++---
 drivers/gpu/drm/omapdrm/omap_drv.c               | 4 ----
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c           | 6 +-----
 drivers/gpu/drm/tegra/dc.c                       | 1 -
 drivers/gpu/drm/tidss/tidss_crtc.c               | 3 +--
 drivers/gpu/drm/tidss/tidss_kms.c                | 4 ----
 11 files changed, 15 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index 56bd938961ee..f33418d6e1a0 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -492,10 +492,8 @@ static void komeda_crtc_reset(struct drm_crtc *crtc)
 	crtc->state = NULL;
 
 	state = kzalloc(sizeof(*state), GFP_KERNEL);
-	if (state) {
-		crtc->state = &state->base;
-		crtc->state->crtc = crtc;
-	}
+	if (state)
+		__drm_atomic_helper_crtc_reset(crtc, &state->base);
 }
 
 static struct drm_crtc_state *
@@ -616,7 +614,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms,
 		return err;
 
 	drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs);
-	drm_crtc_vblank_reset(crtc);
 
 	crtc->port = kcrtc->master->of_output_port;
 
diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c
index 6feda7cb37a6..c9e1ee84b4e8 100644
--- a/drivers/gpu/drm/arm/malidp_drv.c
+++ b/drivers/gpu/drm/arm/malidp_drv.c
@@ -861,7 +861,6 @@ static int malidp_bind(struct device *dev)
 	drm->irq_enabled = true;
 
 	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
-	drm_crtc_vblank_reset(&malidp->crtc);
 	if (ret < 0) {
 		DRM_ERROR("failed to initialise vblank\n");
 		goto vblank_fail;
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index 10985134ce0b..ce246b96330b 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -411,10 +411,8 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
 	}
 
 	state = kzalloc(sizeof(*state), GFP_KERNEL);
-	if (state) {
-		crtc->state = &state->base;
-		crtc->state->crtc = crtc;
-	}
+	if (state)
+		__drm_atomic_helper_crtc_reset(crtc, &state->base);
 }
 
 static struct drm_crtc_state *
@@ -528,7 +526,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev)
 	}
 
 	drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
-	drm_crtc_vblank_reset(&crtc->base);
 
 	drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE);
 	drm_crtc_enable_color_mgmt(&crtc->base, 0, false,
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c
index 8fce6a115dfe..9ad74045158e 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -32,6 +32,7 @@
 #include <drm/drm_device.h>
 #include <drm/drm_plane.h>
 #include <drm/drm_print.h>
+#include <drm/drm_vblank.h>
 #include <drm/drm_writeback.h>
 
 #include <linux/slab.h>
@@ -93,6 +94,9 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
 	if (crtc_state)
 		__drm_atomic_helper_crtc_state_reset(crtc_state, crtc);
 
+	if (drm_dev_has_vblank(crtc->dev))
+		drm_crtc_vblank_reset(crtc);
+
 	crtc->state = crtc_state;
 }
 EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index e152016a6a7d..c39dad151bb6 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1117,8 +1117,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc)
 		mdp5_crtc_destroy_state(crtc, crtc->state);
 
 	__drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base);
-
-	drm_crtc_vblank_reset(crtc);
 }
 
 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index fce7e944a280..6d40914675da 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -697,14 +697,16 @@ static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 
 static void omap_crtc_reset(struct drm_crtc *crtc)
 {
+	struct omap_crtc_state *state;
+
 	if (crtc->state)
 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
 
 	kfree(crtc->state);
-	crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL);
 
-	if (crtc->state)
-		crtc->state->crtc = crtc;
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (state)
+		__drm_atomic_helper_crtc_reset(crtc, &state->base);
 }
 
 static struct drm_crtc_state *
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 242d28281784..4526967978b7 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -595,7 +595,6 @@ static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
 {
 	const struct soc_device_attribute *soc;
 	struct drm_device *ddev;
-	unsigned int i;
 	int ret;
 
 	DBG("%s", dev_name(dev));
@@ -642,9 +641,6 @@ static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
 		goto err_cleanup_modeset;
 	}
 
-	for (i = 0; i < priv->num_pipes; i++)
-		drm_crtc_vblank_off(priv->pipes[i].crtc);
-
 	omap_fbdev_init(ddev);
 
 	drm_kms_helper_poll_init(ddev);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index d73e88ddecd0..fe86a3e67757 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -975,8 +975,7 @@ static void rcar_du_crtc_reset(struct drm_crtc *crtc)
 	state->crc.source = VSP1_DU_CRC_NONE;
 	state->crc.index = 0;
 
-	crtc->state = &state->state;
-	crtc->state->crtc = crtc;
+	__drm_atomic_helper_crtc_reset(crtc, &state->state);
 }
 
 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
@@ -1271,9 +1270,6 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
 
 	drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 
-	/* Start with vertical blanking interrupt reporting disabled. */
-	drm_crtc_vblank_off(crtc);
-
 	/* Register the interrupt handler. */
 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 		/* The IRQ's are associated with the CRTC (sw)index. */
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 83f31c6e891c..9b308b572eac 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1168,7 +1168,6 @@ static void tegra_crtc_reset(struct drm_crtc *crtc)
 		tegra_crtc_atomic_destroy_state(crtc, crtc->state);
 
 	__drm_atomic_helper_crtc_reset(crtc, &state->base);
-	drm_crtc_vblank_reset(crtc);
 }
 
 static struct drm_crtc_state *
diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c
index 89a226912de8..4d01c4af61cd 100644
--- a/drivers/gpu/drm/tidss/tidss_crtc.c
+++ b/drivers/gpu/drm/tidss/tidss_crtc.c
@@ -352,8 +352,7 @@ static void tidss_crtc_reset(struct drm_crtc *crtc)
 		return;
 	}
 
-	crtc->state = &tcrtc->base;
-	crtc->state->crtc = crtc;
+	__drm_atomic_helper_crtc_reset(crtc, &tcrtc->base);
 }
 
 static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c
index 4b99e9fa84a5..e6ab59eed259 100644
--- a/drivers/gpu/drm/tidss/tidss_kms.c
+++ b/drivers/gpu/drm/tidss/tidss_kms.c
@@ -278,10 +278,6 @@ int tidss_modeset_init(struct tidss_device *tidss)
 	if (ret)
 		return ret;
 
-	/* Start with vertical blanking interrupt reporting disabled. */
-	for (i = 0; i < tidss->num_crtcs; ++i)
-		drm_crtc_vblank_reset(tidss->crtcs[i]);
-
 	drm_mode_config_reset(ddev);
 
 	dev_dbg(tidss->dev, "%s done\n", __func__);
-- 
2.26.2

^ permalink raw reply related

* Re: [PATCH v10 0/2] Panel rotation patches
From: Dmitry Osipenko @ 2020-06-12 16:32 UTC (permalink / raw)
  To: Sean Paul, dbasehore ., Thierry Reding
  Cc: Daniel Vetter, linux-kernel, Maarten Lankhorst, Maxime Ripard,
	Thomas Zimmermann, Sam Ravnborg, David Airlie, dri-devel,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <fa443308-7610-9060-68eb-e14e446dd4bf-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

18.05.2020 10:36, Dmitry Osipenko пишет:
> 12.05.2020 23:59, Sean Paul пишет:
>> On Thu, Apr 16, 2020 at 7:03 PM Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>>
>>> 15.04.2020 00:32, dbasehore . пишет:
>>>> On Tue, Apr 14, 2020 at 2:18 PM Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>>>>
>>>>> 14.04.2020 22:32, dbasehore . пишет:
>>>>>> Hi Dmitry, sorry for the late reply.
>>>>>>
>>>>>> On Sun, Mar 8, 2020 at 12:25 PM Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>>>>>>
>>>>>>> 06.03.2020 03:21, Derek Basehore пишет:
>>>>>>>> This adds the plumbing for reading panel rotation from the devicetree
>>>>>>>> and sets up adding a panel property for the panel orientation on
>>>>>>>> Mediatek SoCs when a rotation is present.
>>>>>>>
>>>>>>> Hello Derek and everyone,
>>>>>>>
>>>>>>> I'm looking at adding display rotation support to NVIDIA Tegra DRM
>>>>>>> driver because some devices have display panel physically mounted
>>>>>>> upside-down, and thus, display controller's scan-out needs to be rotated
>>>>>>> by 180° in this case.
>>>>>>>
>>>>>>> Derek, yours panel-rotation patches add support for assigning panel's
>>>>>>> orientation to the connector, but then only primary display plane
>>>>>>> receives rotation value in [1], while rotation needs to be applied to
>>>>>>> all available overlay/cursor planes and this should happen in other
>>>>>>> places than [1] as well.
>>>>>>
>>>>>> This is intended. We don't correct the output in the kernel. We
>>>>>> instead rely on notifying userspace that the panel is rotated, then we
>>>>>> handle it there.
>>>>>>
>>>>>>>
>>>>>>> [1] drm_client_modeset_commit_atomic()
>>>>>>>
>>>>>>> Please also note that in a case of the scan-out rotation, plane's
>>>>>>> coordinates need to be changed in accordance to the display's rotation.
>>>>>>>
>>>>>>> I looked briefly through the DRM code and my understanding that the DRM
>>>>>>> core currently doesn't support use-case where scan-out needs to rotated
>>>>>>> based on a panel's orientation, correct? Is it the use-case you're
>>>>>>> working on for the Mediatek driver?
>>>>>>
>>>>>> Yes, we rely on userspace to rotate the output. The major reason for
>>>>>> this is because there may not be a "free" hardware rotation that can
>>>>>> be applied to the overlay. Sean Paul and others also preferred that
>>>>>> userspace control what is output to the screen instead of the kernel
>>>>>> taking care of it. This code just adds the drm property to the panel.
>>>>>>
>>>>>
>>>>> Could you please explain what that userspace is?
>>>>
>>>> This was added for Chrome OS, which uses its own graphics stack,
>>>> Ozone, instead of Xorg.
>>>>
>>>
>>> Thank you very much for the clarification.
>>>
>>> It's probably not a big problem for something monolithic and customized
>>> like ChromeOS to issue a software update in order to take into account
>>> all specifics of a particular device, but this doesn't work nicely for a
>>> generic software, like a usual Linux distro.
>>>
>>>>> AFAIK, things like Xorg modesetting don't support that orientation property.
>>>
>>> In my case it's not only the display panel which is upside-down, but
>>> also the touchscreen. Hence both display output and touchscreen input
>>> need to be rotated at once, otherwise you'll end up with either display
>>> or input being upside-down.
>>>
>>> The 180° rotation should be free on NVIDIA Tegra. There are no known
>>> limitations for the planes and BSP kernel video driver handles the
>>> plane's coordinates/framebuffer rotation within the driver.
>>>
>>> The kernel's input subsystem allows us to transparently (for userspace)
>>> remap the touchscreen input (by specifying generic touchscreen
>>> device-tree properties), while this is not the case for the DRM subsystem.
>>>
>>> @Thierry, @Sean, @Daniel, could you please help me to understand how a
>>> coordinated display / input rotation could be implemented, making the
>>> rotation transparent to the user (i.e. avoiding xorg.conf hacking and
>>> etc)? It should be nice if display's output could be flipped within the
>>> DRM driver, hiding this fact from userspace.
>>
>> I think the right thing to do is to fix userspace to respect this
>> property, since that has the most communal benefit.
> 
> Hello Sean,
> 
> This will be ideal, but it's difficult to achieve in a loosely
> controlled userspace environment.
> 
>> However(!!) if you don't want to do that, how about inspecting the
>> info->panel_orientation value after drm_panel_attach in tegra driver
>> and then adjusting rotation values in the driver. Of course, you
>> wouldn't want to expose the panel orientation property since you don't
>> want userspaces to be double-rotating on you, but it's optional so
>> you'd be fine.
> 
> Thank you very much for the suggestion, I'll be trying it out soon.
> 
>>>
>>> Will it be okay if we'll add a transparent-rotation support specifically
>>> to the Tegra DRM driver? For example if device-tree contains
>>> nvidia,display-flip-y property, then the Tegra DRM driver will take care
>>> of rotating coordinates/framebuffer of the display planes.
>>
>> I don't think this is necessary, but it also wouldn't really be
>> appropriate to put software attributes into devicetree anyways.
> 
> Yes, I'm also not feeling very excited about this variant.
> 

After some consideration, I decided that it will be better to start easy
by supporting the minimum needed for the rotation property to work on
Tegra, i.e. having userspace to take care of the rotation. It will be
possible to change it later on if will be necessary.

@dbasehore, I'll prepare Tegra DRM patchset around Monday and will
include yours two patches that add DT reading helper and set the display
info, since these patches haven't been applied yet.

^ permalink raw reply

* Re: [PATCH v6 6/6] drm/tegra: output: rgb: Wrap directly-connected panel into DRM bridge
From: kernel test robot @ 2020-06-12 21:23 UTC (permalink / raw)
  To: Dmitry Osipenko, Thierry Reding, Sam Ravnborg, Laurent Pinchart,
	Rob Herring, Frank Rowand
  Cc: kbuild-all-hn68Rpc1hR1g9hUCZPvPmw,
	clang-built-linux-/JYPxA39Uh5TLH3MbocFFw,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20200609132855.20975-7-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 2673 bytes --]

Hi Dmitry,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on next-20200612]
[cannot apply to tegra/for-next robh/for-next v5.7]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Dmitry-Osipenko/Support-DRM-bridges-on-NVIDIA-Tegra/20200609-213026
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git abfbb29297c27e3f101f348dc9e467b0fe70f919
config: arm64-randconfig-r026-20200612 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 3b43f006294971b8049d4807110032169780e5b8)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> drivers/gpu/drm/tegra/rgb.c:100:48: warning: unused variable 'tegra_rgb_connector_helper_funcs' [-Wunused-const-variable]
static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
^
1 warning generated.

vim +/tegra_rgb_connector_helper_funcs +100 drivers/gpu/drm/tegra/rgb.c

3b0e58554873d1 Thierry Reding 2014-12-16   99  
3b0e58554873d1 Thierry Reding 2014-12-16 @100  static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
3b0e58554873d1 Thierry Reding 2014-12-16  101  	.get_modes = tegra_output_connector_get_modes,
3b0e58554873d1 Thierry Reding 2014-12-16  102  	.mode_valid = tegra_rgb_connector_mode_valid,
3b0e58554873d1 Thierry Reding 2014-12-16  103  };
3b0e58554873d1 Thierry Reding 2014-12-16  104  

:::::: The code at line 100 was first introduced by commit
:::::: 3b0e58554873d1034beef737f15c7aa46492ff98 drm/tegra: rgb: Demidlayer

:::::: TO: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
:::::: CC: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 43294 bytes --]

^ permalink raw reply

* Re: [PATCH v6 6/6] drm/tegra: output: rgb: Wrap directly-connected panel into DRM bridge
From: Dmitry Osipenko @ 2020-06-12 21:53 UTC (permalink / raw)
  To: kernel test robot, Thierry Reding, Sam Ravnborg, Laurent Pinchart,
	Rob Herring, Frank Rowand
  Cc: kbuild-all-hn68Rpc1hR1g9hUCZPvPmw,
	clang-built-linux-/JYPxA39Uh5TLH3MbocFFw,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <202006130511.AE6Kvrjm%lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>

13.06.2020 00:23, kernel test robot пишет:
> Hi Dmitry,
> 
> I love your patch! Perhaps something to improve:
> 
> [auto build test WARNING on linus/master]
> [also build test WARNING on next-20200612]
> [cannot apply to tegra/for-next robh/for-next v5.7]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system. BTW, we also suggest to use '--base' option to specify the
> base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
> 
> url:    https://github.com/0day-ci/linux/commits/Dmitry-Osipenko/Support-DRM-bridges-on-NVIDIA-Tegra/20200609-213026
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git abfbb29297c27e3f101f348dc9e467b0fe70f919
> config: arm64-randconfig-r026-20200612 (attached as .config)
> compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 3b43f006294971b8049d4807110032169780e5b8)

Interestingly, GCC doesn't report this warning.

> reproduce (this is a W=1 build):
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm64 cross compiling tool for clang build
>         # apt-get install binutils-aarch64-linux-gnu
>         # save the attached .config to linux build tree
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> 
> All warnings (new ones prefixed by >>, old ones prefixed by <<):
> 
>>> drivers/gpu/drm/tegra/rgb.c:100:48: warning: unused variable 'tegra_rgb_connector_helper_funcs' [-Wunused-const-variable]
> static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
> ^
> 1 warning generated.


There are two unused structs in the code and one is referenced by the
other, I'll remove the unused structs in v7.

^ permalink raw reply

page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox