From: Jeff Dike <jdike@addtoit.com>
To: BlaisorBlade <blaisorblade_spam@yahoo.it>
Cc: user-mode-linux-devel@lists.sourceforge.net
Subject: Re: [uml-devel] Re: The SKAS4 patch?? + ideas for 0 context-switch
Date: Wed, 09 Jun 2004 21:52:05 -0400 [thread overview]
Message-ID: <200406100152.i5A1q5is009173@ccure.user-mode-linux.org> (raw)
In-Reply-To: Your message of "Wed, 09 Jun 2004 23:05:24 +0200." <200406092305.24447.blaisorblade_spam@yahoo.it>
blaisorblade_spam@yahoo.it said:
> I don't think that a flush of fewer TLBs would be faster; what (In My
> Ignorant Opinion) slows things down is not clearing a buffer (it will
> probably cost 1 cycle, if they put a RESET pin in the TLBs), but
> reloading its content when memory is read;
> Well, actually it comes to changing 2 segments descriptors (the ones
> for USER_CS and USER_DS)
> Well, using segments here means that the CS and DS descriptor limit
> are lowered, not that I increase base_addr - are you sure that this
> would have a cost? Currently the check is not "disabled" - just the
> check value is MAX_PTR (0xffff....). Yes, the CPUs could be smart
> enough to optimize the check out...
You are being way too casual and hard-waving about all this. I've heard
scary numbers for all of these.
> I'll try to see if Intel manuals say anything about this.
Yes, spend some quality time with the Intel manuals, and see what they say.
> Well, this is the most important one... I'll try to investigate on
> this.
Actually, the most important factor to me is virtual address space.
Jeff
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next prev parent reply other threads:[~2004-06-10 1:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-06-07 17:49 [uml-devel] The SKAS4 patch?? + ideas for 0 context-switch BlaisorBlade
2004-06-08 4:55 ` [uml-devel] " Jeff Dike
2004-06-09 21:05 ` BlaisorBlade
2004-06-10 1:52 ` Jeff Dike [this message]
2004-06-14 18:17 ` BlaisorBlade
2004-06-14 18:10 ` BlaisorBlade
[not found] ` <200406121601.35801.blaisorblade_spam@yahoo.it>
2004-06-15 3:39 ` Jeff Dike
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