Re: [uml-devel] Re: The SKAS4 patch?? + ideas for 0 context-switch

[Jeff Dike <jdike@addtoit.com>]

blaisorblade_spam@yahoo.it said:
> Or better, if "tagged TLBs" means that the processor knows with which
> process  a TLB is associated, then I understand what you mean and
> agree with you. 

Yes.  Tagged TLBs don't require a full flush on a memory switch, and some
process memory context can survive a switch out and back, so the process doesn't
need to start from a context switch with a cold cache.

> I.e. they (Andrea Arcangeli and Ingo Molnar) agree that the cost of a
> TLB  flush changes depending on the number of filled TLBs. And they
> seem to also  agree that there is a "secondary cost", the cost of the
> TLB misses (which is  IMHO the one which changes depending on how much
> entries you flush). 

I didn't really see a clear statement of that in there.  You need to look
at the manuals to be sure.

> The Intel Manual 3 (Intel System Programming Guide - 253668 -15.pdf)
> says, at  page 4-1 (page 107 in the PDF), that limit checking has no
> performance cost,  

I don't see any discussion of performance there.  My copy of the spec dates
from Jan 2002.  Page 107 in the pdf is page 4-3 for me.  Section 4.3 on page
4-4 talks about limit checking, but nothing about performance.

				Jeff



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