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From: "Tiwei Bie" <tiwei.btw@antgroup.com>
To: benjamin@sipsolutions.net, linux-um@lists.infradead.org
Cc: Benjamin Berg <benjamin.berg@intel.com>
Subject: Re: [PATCH 5/5] um: Add 4 level page table support
Date: Thu, 30 May 2024 11:07:11 +0800	[thread overview]
Message-ID: <64fc3b3f-50c7-42c1-a30d-c3eb90c76286@antgroup.com> (raw)
In-Reply-To: <20240528085419.1964424-6-benjamin@sipsolutions.net>

On 5/28/24 4:54 PM, benjamin@sipsolutions.net wrote:
[...]
> diff --git a/arch/um/Kconfig b/arch/um/Kconfig
> index 93a5a8999b07..5d111fc8ccb7 100644
> --- a/arch/um/Kconfig
> +++ b/arch/um/Kconfig
> @@ -208,6 +208,7 @@ config MMAPPER
>  
>  config PGTABLE_LEVELS
>  	int
> +	default 4 if 4_LEVEL_PGTABLES
>  	default 3 if 3_LEVEL_PGTABLES
>  	default 2
>  
[...]
> diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig
> index 186f13268401..72dc7b0b3a33 100644
> --- a/arch/x86/um/Kconfig
> +++ b/arch/x86/um/Kconfig
> @@ -28,16 +28,34 @@ config X86_64
>  	def_bool 64BIT
>  	select MODULES_USE_ELF_RELA
>  
> -config 3_LEVEL_PGTABLES
> -	bool "Three-level pagetables" if !64BIT
> -	default 64BIT
> -	help
> -	  Three-level pagetables will let UML have more than 4G of physical
> -	  memory.  All the memory that can't be mapped directly will be treated
> -	  as high memory.
> -
> -	  However, this it experimental on 32-bit architectures, so if unsure say
> -	  N (on x86-64 it's automatically enabled, instead, as it's safe there).
> +choice
> +	prompt "Pagetable levels" if EXPERT
> +	default 2_LEVEL_PGTABLES if !64BIT
> +	default 4_LEVEL_PGTABLES if 64BIT
> +
> +	config 2_LEVEL_PGTABLES
> +		bool "Three-level pagetables" if !64BIT

Nit: s/Three-level/Two-level/

> +		depends on !64BIT
> +		help
> +		  Two-level page table for 32-bit architectures.
> +
> +	config 3_LEVEL_PGTABLES
> +		bool "Three-level pagetables" if 64BIT
> +		help
> +		  Three-level pagetables will let UML have more than 4G of physical
> +		  memory.  All the memory that can't be mapped directly will be treated
> +		  as high memory.
> +
> +		  However, this it experimental on 32-bit architectures, so if unsure say
> +		  N (on x86-64 it's automatically enabled, instead, as it's safe there).
> +
> +	config 4_LEVEL_PGTABLES
> +		bool "Four-level pagetables" if 64BIT
> +		depends on 64BIT
> +		help
> +		  Four-level pagetables, gives a bigger address space which can be
> +		  useful for some applications (e.g. ASAN).

On 64bit, it appears that 4_LEVEL_PGTABLES won't be selected by running
"make ARCH=um defconfig", and PGTABLE_LEVELS will be 2.

I got the following search result in "make ARCH=um menuconfig":

  │ Symbol: 4_LEVEL_PGTABLES [=n]
  │ Type  : bool
  │ Defined at arch/x86/um/Kconfig:51
  │   Prompt: Four-level pagetables
  │   Depends on: <choice> && 64BIT [=y]
  │   Location:
  │ (1) -> UML-specific options
  │       -> Pagetable levels (<choice> [=n])
  │         -> Four-level pagetables (4_LEVEL_PGTABLES [=n])

And 4_LEVEL_PGTABLES will be selected if I turn on EXPERT manually.

Regards,
Tiwei

> +endchoice
>  
>  config ARCH_HAS_SC_SIGNALS
>  	def_bool !64BIT



      reply	other threads:[~2024-05-30  3:07 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-28  8:54 [PATCH 0/5] Increased address space for 64 bit benjamin
2024-05-28  8:54 ` [PATCH 1/5] um: Fix stub_start address calculation benjamin
2024-05-28  8:54 ` [PATCH 2/5] um: Limit TASK_SIZE to the addressable range benjamin
2024-05-28  8:54 ` [PATCH 3/5] um: Do a double clone to disable rseq benjamin
2024-05-28 10:16   ` Tiwei Bie
2024-05-28 10:30     ` Benjamin Berg
2024-05-28 11:03       ` Tiwei Bie
2024-05-28 11:57     ` Johannes Berg
2024-05-28 14:13       ` Tiwei Bie
2024-05-30  2:54         ` Tiwei Bie
2024-05-30  8:54           ` Benjamin Berg
2024-05-30 14:05             ` Tiwei Bie
2024-05-28  8:54 ` [PATCH 4/5] um: Discover host_task_size from envp benjamin
2024-05-28  8:54 ` [PATCH 5/5] um: Add 4 level page table support benjamin
2024-05-30  3:07   ` Tiwei Bie [this message]

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