[PATCH] usb: xhci-pci: Disable 64-bit DMA for VIA VL805

[PATCH] usb: xhci-pci: Disable 64-bit DMA for VIA VL805

[Xincheng Zhang]

The VIA VL805 XHCI controller (Device ID 0x3483) fails to handle DMA
addresses correctly when they exceed 0x1000000000 (64GB). On systems
with large amounts of RAM, this hardware limitation causes device failures.

Add the XHCI_NO_64BIT_SUPPORT quirk to restrict DMA addressing to 32-bit,
preventing the controller from receiving addresses beyond its hardware
limit.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
---
 drivers/usb/host/xhci-pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 039c26b241d0..99c2dc3cebfe 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -448,6 +448,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 	if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) {
 		xhci->quirks |= XHCI_LPM_SUPPORT;
 		xhci->quirks |= XHCI_TRB_OVERFETCH;
+		xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 	}
 
 	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&

---
base-commit: 502d801f0ab03e4f32f9a33d203154ce84887921
change-id: 20260623-xhci-via-dma-fix-c563b889ea54

Best regards,
--  
Xincheng Zhang <zhangxincheng@ultrarisc.com>

Re: [PATCH] usb: xhci-pci: Disable 64-bit DMA for VIA VL805

[Michal Pecio]

On Tue, 23 Jun 2026 15:32:02 +0800, Xincheng Zhang wrote:
> The VIA VL805 XHCI controller (Device ID 0x3483) fails to handle DMA
> addresses correctly when they exceed 0x1000000000 (64GB). On systems
> with large amounts of RAM, this hardware limitation causes device
> failures.
> 
> Add the XHCI_NO_64BIT_SUPPORT quirk to restrict DMA addressing to
> 32-bit, preventing the controller from receiving addresses beyond its
> hardware limit.
> 
> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>

It could make sense to put a fix for this in stable too.

But I don't like this abuse of the quirk. Firstly, it causes
unnecessary bouncing on systems with >4GB RAM and no IOMMU.
I found other drivers that use DMA_BIT_MASK(36) or even weirder
numbers, so it seems that we too could request 64 gigs exactly
with a bit of driver refactoring.

Secondly, it makes the driver pretend that AC64 capability is absent.
Differences go beyond address bits, notably including register width
and whether QWORD or only DWORD writes cane be used. For example, if
we want to improve command abort on AC64 chips using QWORD writes, we
will need to know the true state of this capability, regarless of
whether the chip really implements all 64 address bits or not.

Forest, you have added a number of similar quirks for ASMedia chips.
Do you happen to know what is their real address width? I think it
might prove useful to have this on record.

Regards,
Michal