[PATCH 00/10] ARM: qcom: msm8974: enable HSIC controller

[PATCH 00/10] ARM: qcom: msm8974: enable HSIC controller

[Dmitry Baryshkov]

Qualcomm MSM8974 incorporates a special version of the ChipIdea
controller, HSIC. Enabling it requires some quirks, which were not
present in the kernel tree up to now. Wire up the controller on MSM8974
and enable it on APQ8074 Dragonboard.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Dmitry Baryshkov (10):
      dt-bindings: pinctrl: qcom,tlmm-common: allow functions on the HSIC pins
      dt-bindings: usb: ci-hdrc-usb2: allow the HSIC PHY as the ULPI child
      phy: qcom-usb-hsic: do not run the sleep calibration clock
      phy: qcom-usb-hsic: engage HSIC mode from phy_calibrate()
      usb: chipidea: msm: support the HSIC asynchronous wakeup interrupt
      usb: chipidea: msm: keep the glue device runtime-active
      usb: chipidea: msm: do not force the TX FIFO idle on HSIC instances
      usb: chipidea: host: calibrate the PHY after starting the host
      ARM: dts: qcom: msm8974: add the HSIC USB controller
      ARM: dts: qcom: apq8074-dragonboard: enable the HSIC host

 .../bindings/pinctrl/qcom,msm8974-pinctrl.yaml     |  1 +
 .../bindings/pinctrl/qcom,tlmm-common.yaml         |  2 +-
 .../devicetree/bindings/usb/ci-hdrc-usb2.yaml      |  4 +-
 .../arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts | 27 ++++++++
 arch/arm/boot/dts/qcom/qcom-msm8974.dtsi           | 71 ++++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-usb-hsic.c           | 50 ++++++++-------
 drivers/usb/chipidea/ci_hdrc_msm.c                 | 28 ++++++++-
 drivers/usb/chipidea/host.c                        |  4 ++
 8 files changed, 161 insertions(+), 26 deletions(-)
---
base-commit: 6b8c8af514d739d0335f5579b585e02babe8a727
change-id: 20260810-msm8974-usb-hsic-561bc9dfd757
prerequisite-change-id: 20260810-msm8974-usb3-8591395891b9:v1
prerequisite-patch-id: c26539fbb2d694a92439cb1e726212918553475c
prerequisite-patch-id: 4ad3db6c6ac190b38705ed8876802392c8d7d339
prerequisite-patch-id: 3478affb2dfff9e7ab10d3021889e8b18457533f
prerequisite-patch-id: b646868cd0435307c98f9f5befcc6b19f21ec0d7
prerequisite-patch-id: b98cf68875fdf3b81fdc383e1b69a3fcc35bf986
prerequisite-patch-id: 4af06591492ba21e53d415f18de59488bfc3c2d4
prerequisite-patch-id: 5177cabe40273cd97110295567ff2cccbaad02df
prerequisite-patch-id: 1d2ed9fb3f5d99c6ea828eb5aec1412f4b46467a
prerequisite-patch-id: 246d719fc20ff640d41bd295fb97061dfa979250
prerequisite-patch-id: 21c3534b93d76f2902f08fff2e5d922402c0b8a3
prerequisite-patch-id: 8e31a3323407f373d791f26edccb7a0aa6c51628
prerequisite-patch-id: b50af8d10a33e4383d7d4baf76d710a91d0d6c6e
prerequisite-patch-id: aa0ddfa89a9b0d7f11fc835846a5566df50f94f5
prerequisite-patch-id: 109ff819c0c46ed02dac52641e7b9f4b254d09ed
prerequisite-patch-id: a3059aa8be37e0b32e0eadbb964b0aff6547e563
prerequisite-patch-id: bc77eb17f857d18e1076597a662951a10ada9535
prerequisite-patch-id: 19f3ffb7fd87e270623c8a605a9250b3f886553a
prerequisite-patch-id: fd5725234a661c4284ec4804bf3da6479452c5c2
prerequisite-patch-id: 80439f9121f3cb7d269caa0d2f117f30599611a7
prerequisite-change-id: 20260810-msm8974-onboard-usb-98d293645270:v1
prerequisite-patch-id: c26539fbb2d694a92439cb1e726212918553475c
prerequisite-patch-id: 4ad3db6c6ac190b38705ed8876802392c8d7d339
prerequisite-patch-id: 3478affb2dfff9e7ab10d3021889e8b18457533f
prerequisite-patch-id: b646868cd0435307c98f9f5befcc6b19f21ec0d7
prerequisite-patch-id: b98cf68875fdf3b81fdc383e1b69a3fcc35bf986
prerequisite-patch-id: 4af06591492ba21e53d415f18de59488bfc3c2d4
prerequisite-patch-id: 5177cabe40273cd97110295567ff2cccbaad02df
prerequisite-patch-id: 1d2ed9fb3f5d99c6ea828eb5aec1412f4b46467a

Best regards,
--  
With best wishes
Dmitry

[PATCH 01/10] dt-bindings: pinctrl: qcom,tlmm-common: allow functions on the HSIC pins

[Dmitry Baryshkov]

The common TLMM state schema requires the function property for GPIO
pins and forbids it for all special pins. That rule is wrong for the
MSM8974 HSIC pads: unlike the SDC pads, hsic_data and hsic_strobe are
muxable pin groups (between the gpio and hsic_ctl functions, see
HSIC_PINGROUP in pinctrl-msm8x74.c), and the msm8974 schema already
lists hsic_ctl in its function enum. As a result any valid HSIC
pinctrl state fails validation.

Extend the function-required conditional to cover the HSIC pins and add
the now-required function to the msm8974 example.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml | 1 +
 Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml     | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml
index a9aff442824c..d9178b265268 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml
@@ -161,5 +161,6 @@ examples:
 
         hsic-state {
             pins = "hsic_data", "hsic_strobe";
+            function = "hsic_ctl";
         };
     };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
index aec72e8c0621..e10aff02be89 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
@@ -95,7 +95,7 @@ $defs:
           properties:
             pins:
               items:
-                pattern: "^gpio"
+                pattern: "^(gpio|hsic)"
         then:
           required:
             - function

-- 
2.47.3

[PATCH 02/10] dt-bindings: usb: ci-hdrc-usb2: allow the HSIC PHY as the ULPI child

[Dmitry Baryshkov]

The Qualcomm HSIC USB PHY (qcom,usb-hsic-phy.yaml) is a ULPI device: its
driver is a ulpi_driver, so the PHY node must be a child of the chipidea
controller's ulpi node. The ci-hdrc-usb2 schema however hard-codes the
ULPI phy child to the qcom,usb-hs-phy.yaml schema, so any HSIC
controller instance fails validation with bogus clock/reset/compatible
errors.

Allow the ULPI phy child node to match either the HS PHY or the HSIC
PHY schema.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml
index 620b564914d4..97ebf9e031dd 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml
@@ -83,7 +83,9 @@ properties:
       "^phy(-[0-9])?$":
         description: The phy child node for Qcom chips.
         type: object
-        $ref: /schemas/phy/qcom,usb-hs-phy.yaml
+        oneOf:
+          - $ref: /schemas/phy/qcom,usb-hs-phy.yaml
+          - $ref: /schemas/phy/qcom,usb-hsic-phy.yaml
 
 required:
   - compatible

-- 
2.47.3

[PATCH 03/10] phy: qcom-usb-hsic: do not run the sleep calibration clock

[Dmitry Baryshkov]

With the cal_sleep (32 kHz IO calibration sleep) clock running, the
HSIC PHY engages its sleep calibration: the strobe/data pad
calibration converges to different values than with the active
calibration alone, HSIC_CFG reports the sleep calibration state, and
the port no longer detects a device connect - an onboard HSIC hub
signalling its attach after reset is never seen (observed on the
APQ8074 Dragonboard against its USB4604 hub, by comparing the ULPI
register state against the vendor kernel, which never enables this
clock: with cal_sleep enabled ULPI HSIC_CFG reads 0xab and the pad
registers 0x0f/0x0d, without it 0xa9 and 0x10/0x10, matching the
working vendor configuration).

Stop requesting and enabling the cal_sleep clock.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
index 20f6dd37c7c1..b670ec364a2d 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
@@ -20,7 +20,6 @@ struct qcom_usb_hsic_phy {
 	struct pinctrl *pctl;
 	struct clk *phy_clk;
 	struct clk *cal_clk;
-	struct clk *cal_sleep_clk;
 };
 
 static int qcom_usb_hsic_phy_power_on(struct phy *phy)
@@ -38,9 +37,13 @@ static int qcom_usb_hsic_phy_power_on(struct phy *phy)
 	if (ret)
 		goto err_cal;
 
-	ret = clk_prepare_enable(uphy->cal_sleep_clk);
-	if (ret)
-		goto err_sleep;
+	/*
+	 * The sleep calibration clock must not run: with it enabled the PHY
+	 * engages sleep calibration (the strobe/data pad calibration
+	 * converges to different values and HSIC_CFG reports the sleep
+	 * calibration state), and the port does not detect a device connect.
+	 * The vendor driver never enables this clock.
+	 */
 
 	/* Set periodic calibration interval to ~2.048sec in HSIC_IO_CAL_REG */
 	ret = ulpi_write(ulpi, ULPI_HSIC_IO_CAL, 0xff);
@@ -76,8 +79,6 @@ static int qcom_usb_hsic_phy_power_on(struct phy *phy)
 
 	return ret;
 err_ulpi:
-	clk_disable_unprepare(uphy->cal_sleep_clk);
-err_sleep:
 	clk_disable_unprepare(uphy->cal_clk);
 err_cal:
 	clk_disable_unprepare(uphy->phy_clk);
@@ -88,7 +89,6 @@ static int qcom_usb_hsic_phy_power_off(struct phy *phy)
 {
 	struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy);
 
-	clk_disable_unprepare(uphy->cal_sleep_clk);
 	clk_disable_unprepare(uphy->cal_clk);
 	clk_disable_unprepare(uphy->phy_clk);
 
@@ -125,10 +125,6 @@ static int qcom_usb_hsic_phy_probe(struct ulpi *ulpi)
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
 
-	uphy->cal_sleep_clk = clk = devm_clk_get(&ulpi->dev, "cal_sleep");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
 	uphy->phy = devm_phy_create(&ulpi->dev, ulpi->dev.of_node,
 				    &qcom_usb_hsic_phy_ops);
 	if (IS_ERR(uphy->phy))

-- 
2.47.3

[PATCH 04/10] phy: qcom-usb-hsic: engage HSIC mode from phy_calibrate()

[Dmitry Baryshkov]

The PHY power-on sequence ends by engaging HSIC mode. With chipidea,
power-on runs before the host is started, and the HSIC connect of an
already-present device is latched at the moment HSIC mode is engaged:
performed before the host runs (and before an onboard hub is taken out
of reset), the connect is lost and the device is never seen. This is
why the APQ8074 dragonboard USB4604 hub never enumerated on mainline
while the vendor kernel - which performs the whole PHY sequence after
usb_add_hcd() - sees it on every boot.

Keep the calibration setup and the pad mux in power-on, and move the
HSIC mode enable (and the auto-resume disable) into the calibrate op,
which the chipidea host now invokes after the host is up and the
onboard device reset has been released.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 32 +++++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
index b670ec364a2d..e0637522eb82 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
@@ -63,17 +63,6 @@ static int qcom_usb_hsic_phy_power_on(struct phy *phy)
 	}
 
 	ret = pinctrl_select_state(uphy->pctl, pins_default);
-	if (ret)
-		goto err_ulpi;
-
-	 /* Enable HSIC mode in HSIC_CFG register */
-	ret = ulpi_write(ulpi, ULPI_SET(ULPI_HSIC_CFG), 0x01);
-	if (ret)
-		goto err_ulpi;
-
-	/* Disable auto-resume */
-	ret = ulpi_write(ulpi, ULPI_CLR(ULPI_IFC_CTRL),
-			 ULPI_IFC_CTRL_AUTORESUME);
 	if (ret)
 		goto err_ulpi;
 
@@ -85,6 +74,26 @@ static int qcom_usb_hsic_phy_power_on(struct phy *phy)
 	return ret;
 }
 
+static int qcom_usb_hsic_phy_calibrate(struct phy *phy)
+{
+	struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy);
+	struct ulpi *ulpi = uphy->ulpi;
+	int ret;
+
+	/*
+	 * Engage HSIC mode only now, with the host running and the
+	 * downstream device out of reset: the connect is latched at this
+	 * point, and a hub that has already booted asserts it right away.
+	 */
+	ret = ulpi_write(ulpi, ULPI_SET(ULPI_HSIC_CFG), 0x01);
+	if (ret)
+		return ret;
+
+	/* Disable auto-resume */
+	return ulpi_write(ulpi, ULPI_CLR(ULPI_IFC_CTRL),
+			  ULPI_IFC_CTRL_AUTORESUME);
+}
+
 static int qcom_usb_hsic_phy_power_off(struct phy *phy)
 {
 	struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy);
@@ -97,6 +106,7 @@ static int qcom_usb_hsic_phy_power_off(struct phy *phy)
 
 static const struct phy_ops qcom_usb_hsic_phy_ops = {
 	.power_on = qcom_usb_hsic_phy_power_on,
+	.calibrate = qcom_usb_hsic_phy_calibrate,
 	.power_off = qcom_usb_hsic_phy_power_off,
 	.owner = THIS_MODULE,
 };

-- 
2.47.3

[PATCH 05/10] usb: chipidea: msm: support the HSIC asynchronous wakeup interrupt

[Dmitry Baryshkov]

The HSIC instances of the chipidea controller runtime-suspend with
their clocks gated whenever the bus is empty. HSIC has no VBUS-style
connect detection: a device (such as an onboard hub coming out of
reset) signals a single connect event, and if the controller is
suspended at that moment the connect is never noticed and the device
never enumerates.

The hardware provides an asynchronous wakeup interrupt that fires on
HSIC bus activity while the controller is in low power mode. Pick it
up as an optional second interrupt and attach it as a dedicated wake
irq of the core device, so the PM core arms it over runtime suspend
and resumes the controller when the bus reports activity.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/usb/chipidea/ci_hdrc_msm.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c b/drivers/usb/chipidea/ci_hdrc_msm.c
index 3ab3daa78e34..e28ea87f9898 100644
--- a/drivers/usb/chipidea/ci_hdrc_msm.c
+++ b/drivers/usb/chipidea/ci_hdrc_msm.c
@@ -4,6 +4,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/pm_wakeirq.h>
 #include <linux/usb/chipidea.h>
 #include <linux/clk.h>
 #include <linux/reset.h>
@@ -173,6 +174,7 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev)
 {
 	struct ci_hdrc_msm *ci;
 	struct platform_device *plat_ci;
+	int wake_irq;
 	struct clk *clk;
 	struct reset_control *reset;
 	int ret;
@@ -261,6 +263,19 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev)
 
 	ci->ci = plat_ci;
 
+	/*
+	 * The optional second interrupt is the asynchronous wakeup interrupt
+	 * of the HSIC instances: without it a bus connect arriving while the
+	 * runtime-suspended controller has its clocks gated is never seen.
+	 */
+	wake_irq = platform_get_irq_optional(pdev, 1);
+	if (wake_irq > 0) {
+		device_init_wakeup(&plat_ci->dev, true);
+		ret = dev_pm_set_dedicated_wake_irq(&plat_ci->dev, wake_irq);
+		if (ret)
+			dev_warn(&pdev->dev, "no wakeup interrupt: %d\n", ret);
+	}
+
 	pm_runtime_set_active(&pdev->dev);
 	pm_runtime_no_callbacks(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
@@ -279,6 +294,7 @@ static void ci_hdrc_msm_remove(struct platform_device *pdev)
 	struct ci_hdrc_msm *ci = platform_get_drvdata(pdev);
 
 	pm_runtime_disable(&pdev->dev);
+	dev_pm_clear_wake_irq(&ci->ci->dev);
 	ci_hdrc_remove_device(ci->ci);
 	clk_disable_unprepare(ci->iface_clk);
 	clk_disable_unprepare(ci->core_clk);

-- 
2.47.3

[PATCH 06/10] usb: chipidea: msm: keep the glue device runtime-active

[Dmitry Baryshkov]

The msm chipidea glue enables runtime PM with pm_runtime_no_callbacks()
and nothing pinning it active. Right after a successful probe the
driver core's pm_request_idle() runtime-suspends the glue (the ci core
child has runtime PM disabled, so it does not hold its parent), and
when the glue sits in a power domain - the HSIC instances live in the
USB_HS_HSIC GDSC on msm8974 - genpd then powers the domain off
underneath the running controller. The EHCI register file reads back
zeroes, an onboard hub's connect is never seen, and subsequent bus
accesses into the unpowered block wedge the interconnect, eventually
taking the whole SoC down.

Pin the glue runtime-active so the domain stays powered for the
lifetime of the controller. Proper low-power handling can later be
built on the child's runtime PM together with the HSIC wakeup
interrupt.

Fixes: 2d0cdcc5a0e4 ("USB: gadget: Implement runtime PM for MSM bus glue driver")
Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/usb/chipidea/ci_hdrc_msm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c b/drivers/usb/chipidea/ci_hdrc_msm.c
index e28ea87f9898..9a9410a814e5 100644
--- a/drivers/usb/chipidea/ci_hdrc_msm.c
+++ b/drivers/usb/chipidea/ci_hdrc_msm.c
@@ -276,7 +276,13 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev)
 			dev_warn(&pdev->dev, "no wakeup interrupt: %d\n", ret);
 	}
 
+	/*
+	 * The glue owns the controller's power domain (the HSIC instances sit
+	 * in a GDSC): if it runtime-suspends, the domain is powered off
+	 * underneath the running controller. Pin it active.
+	 */
 	pm_runtime_set_active(&pdev->dev);
+	pm_runtime_get_noresume(&pdev->dev);
 	pm_runtime_no_callbacks(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 
@@ -294,6 +300,7 @@ static void ci_hdrc_msm_remove(struct platform_device *pdev)
 	struct ci_hdrc_msm *ci = platform_get_drvdata(pdev);
 
 	pm_runtime_disable(&pdev->dev);
+	pm_runtime_put_noidle(&pdev->dev);
 	dev_pm_clear_wake_irq(&ci->ci->dev);
 	ci_hdrc_remove_device(ci->ci);
 	clk_disable_unprepare(ci->iface_clk);

-- 
2.47.3

[PATCH 07/10] usb: chipidea: msm: do not force the TX FIFO idle on HSIC instances

[Dmitry Baryshkov]

The controller reset handler unconditionally clears
GENCONFIG[TXFIFO_IDLE_FORCE_DIS] as a workaround for an RX buffer
collision issue. The vendor HSIC host driver never applies this
workaround on the HSIC instances and leaves the bit at its power-on
default (set), so clearing it makes the HSIC instance diverge from the
known-working configuration.

Skip the workaround for HSIC instances, like the neighbouring
GENCONFIG_2 write already does.

Fixes: 47654a162081 ("usb: chipidea: msm: Restore wrapper settings after reset")
Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/usb/chipidea/ci_hdrc_msm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c b/drivers/usb/chipidea/ci_hdrc_msm.c
index 9a9410a814e5..69be194f8e27 100644
--- a/drivers/usb/chipidea/ci_hdrc_msm.c
+++ b/drivers/usb/chipidea/ci_hdrc_msm.c
@@ -108,8 +108,9 @@ static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
 		hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8);
 
 		/* workaround for rx buffer collision issue */
-		hw_write_id_reg(ci, HS_PHY_GENCONFIG,
-				HS_PHY_TXFIFO_IDLE_FORCE_DIS, 0);
+		if (!msm_ci->hsic)
+			hw_write_id_reg(ci, HS_PHY_GENCONFIG,
+					HS_PHY_TXFIFO_IDLE_FORCE_DIS, 0);
 
 		if (!msm_ci->hsic)
 			hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,

-- 
2.47.3

[PATCH 08/10] usb: chipidea: host: calibrate the PHY after starting the host

[Dmitry Baryshkov]

Some PHYs need a final programming step after the host controller is
up: the Qualcomm HSIC PHY latches the device connect at the moment
HSIC mode is engaged, so that write must happen with the root port
already running, or an already-connected HSIC device (the strobe/data
lines have no hotplug) is never seen. The generic PHY framework
provides phy_calibrate() for exactly this kind of post-init fixup and
dwc3 already calls it; the chipidea host does not, leaving no place
for such PHY work.

Call phy_calibrate() once the HCD has been added, next to the existing
i.MX HSIC active-event hook which serves the same purpose. PHYs
without a calibrate op are unaffected.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/usb/chipidea/host.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c
index ced6076a8248..62bb2999edb6 100644
--- a/drivers/usb/chipidea/host.c
+++ b/drivers/usb/chipidea/host.c
@@ -15,6 +15,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/string_choices.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/phy/phy.h>
 
 #include "../host/ehci.h"
 
@@ -192,6 +193,9 @@ static int host_start(struct ci_hdrc *ci)
 			(ci->platdata->flags & CI_HDRC_IMX_IS_HSIC))
 			ci->platdata->notify_event
 				(ci, CI_HDRC_IMX_HSIC_ACTIVE_EVENT);
+
+		if (ci->phy)
+			phy_calibrate(ci->phy);
 	}
 
 	return ret;

-- 
2.47.3

[PATCH 09/10] ARM: dts: qcom: msm8974: add the HSIC USB controller

[Dmitry Baryshkov]

The MSM8974 HSIC USB host - a third Chipidea controller with a
dedicated HSIC PHY on the special hsic_strobe/hsic_data pads - is not
described, leaving boards with HSIC-attached hubs or modems without
upstream support.

Add the controller and PHY nodes. The PHY is a ULPI bus driver present
inside the ulpi subnode.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 71 ++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index bac3c8772e0a..72cd369927b2 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -760,6 +760,49 @@ usb3_ss_phy: phy@f92f8830 {
 			status = "disabled";
 		};
 
+		usb_hsic: usb@f9a00000 {
+			compatible = "qcom,ci-hdrc";
+			reg = <0xf9a00000 0x200>,
+			      <0xf9a00200 0x200>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
+			assigned-clocks = <&gcc GCC_USB_HSIC_SYSTEM_CLK>,
+					  <&gcc GCC_USB_HSIC_CLK>,
+					  <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
+			assigned-clock-rates = <75000000>,
+					       <480000000>,
+					       <9600000>;
+			clocks = <&gcc GCC_USB_HSIC_AHB_CLK>,
+				 <&gcc GCC_USB_HSIC_SYSTEM_CLK>;
+			clock-names = "iface", "core";
+			resets = <&gcc GCC_USB_HS_HSIC_BCR>;
+			reset-names = "core";
+			power-domains = <&gcc USB_HS_HSIC_GDSC>;
+			phys = <&usb_hsic_phy>;
+			phy-names = "usb-phy";
+			phy_type = "ulpi";
+			dr_mode = "host";
+			ahb-burst-config = <0>;
+
+			status = "disabled";
+
+			ulpi {
+				usb_hsic_phy: phy {
+					compatible = "qcom,usb-hsic-phy-msm8974",
+						     "qcom,usb-hsic-phy";
+					clocks = <&gcc GCC_USB_HSIC_CLK>,
+						 <&gcc GCC_USB_HSIC_IO_CAL_CLK>,
+						 <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
+					clock-names = "phy", "cal", "cal_sleep";
+					#phy-cells = <0>;
+
+					pinctrl-names = "init", "default";
+					pinctrl-0 = <&hsic_gpio_state>;
+					pinctrl-1 = <&hsic_state>;
+				};
+			};
+		};
+
 		usb: usb@f9a55000 {
 			compatible = "qcom,ci-hdrc";
 			reg = <0xf9a55000 0x200>,
@@ -1677,6 +1720,34 @@ tlmm: pinctrl@fd510000 {
 			#interrupt-cells = <2>;
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 
+			hsic_gpio_state: hsic-gpio-state {
+				data-strobe-pins {
+					pins = "gpio144", "gpio145";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				ctl-pins {
+					pins = "hsic_data", "hsic_strobe";
+					function = "gpio";
+				};
+			};
+
+			hsic_state: hsic-state {
+				data-strobe-pins {
+					pins = "gpio144", "gpio145";
+					function = "hsic";
+					drive-strength = <12>;
+					bias-disable;
+				};
+
+				ctl-pins {
+					pins = "hsic_data", "hsic_strobe";
+					function = "hsic_ctl";
+				};
+			};
+
 			sdc1_off: sdc1-off-state {
 				clk-pins {
 					pins = "sdc1_clk";

-- 
2.47.3

[PATCH 10/10] ARM: dts: qcom: apq8074-dragonboard: enable the HSIC host

[Dmitry Baryshkov]

The dragonboard carries an SMSC USB4604 HSIC hub, but with the HSIC
controller undescribed the whole HSIC-attached part of the board is
dead.

Enable the HSIC controller. The USB4604 hub isn't controllable through
the I2C because of the board design issues, so reference it as a simple
USB device, describing the reset line.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 .../arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts
index 083fd8fa0aea..02183b37ddbe 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts
@@ -158,6 +158,14 @@ &mdss {
 };
 
 &pm8941_gpios {
+	hsic_hub_rst_default: hsic-hub-rst-state {
+		pins = "gpio8";
+		function = "normal";
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+		power-source = <PM8941_GPIO_VPH>;
+	};
+
 	msm_keys_default: pm8941-gpio-keys-state {
 		pins = "gpio5", "gpio23";
 		function = "normal";
@@ -487,6 +495,25 @@ &usb_hs2_phy {
 	qcom,init-seq = /bits/ 8 <0x1 0x63>;
 };
 
+&usb_hsic {
+	pinctrl-0 = <&hsic_hub_rst_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* SMSC USB4604 hub, standalone mode (SMBus config not usable) */
+	hub@1 {
+		compatible = "usb424,4604";
+		reg = <1>;
+		clocks = <&rpmcc RPM_SMD_CXO_D1>;
+		reset-gpios = <&pm8941_gpios 8 GPIO_ACTIVE_LOW>;
+		vdd-supply = <&pm8941_s3>;
+	};
+};
+
 &usb3 {
 	dr_mode = "host";
 

-- 
2.47.3