From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Sanjay R Mehta <Sanju.Mehta@amd.com>
Cc: andreas.noever@gmail.com, michael.jamet@intel.com,
YehezkelShB@gmail.com, Basavaraj.Natikar@amd.com,
linux-usb@vger.kernel.org
Subject: Re: [PATCH v5] thunderbolt: Add quirk to disable CLx
Date: Wed, 15 Feb 2023 07:49:59 +0200 [thread overview]
Message-ID: <Y+xyh44lGEzwuOj/@black.fi.intel.com> (raw)
In-Reply-To: <1676404912-7048-1-git-send-email-Sanju.Mehta@amd.com>
On Tue, Feb 14, 2023 at 02:01:52PM -0600, Sanjay R Mehta wrote:
> void tb_check_quirks(struct tb_switch *sw)
> {
> + struct tb_switch *root_sw = sw->tb->root_switch;
> int i;
>
> for (i = 0; i < ARRAY_SIZE(tb_quirks); i++) {
> const struct tb_quirk *q = &tb_quirks[i];
>
> - if (q->hw_vendor_id && q->hw_vendor_id != sw->config.vendor_id)
> + if (q->hw_vendor_id && (q->hw_vendor_id != sw->config.vendor_id &&
> + q->hw_vendor_id != root_sw->config.vendor_id))
Again, why you need to change this?
If you have the AMD host router device ID in the list the quirk applies
and that makes the driver skip enabling CL states for that link. It
should not matter if we enable CL states in the deeper parts of the
topology (even if we actually do not at the moment) because that's
completely different link, right.
next prev parent reply other threads:[~2023-02-15 5:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 20:01 [PATCH v5] thunderbolt: Add quirk to disable CLx Sanjay R Mehta
2023-02-15 5:49 ` Mika Westerberg [this message]
2023-02-15 5:59 ` Basavaraj Natikar
2023-02-15 6:16 ` Mika Westerberg
2023-02-15 6:23 ` Basavaraj Natikar
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