* [PATCH v4 02/11] dt-bindings: net: btusb: change reference file name
From: Chunfeng Yun @ 2020-12-16 9:30 UTC (permalink / raw)
To: Rob Herring
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
David S . Miller, Jakub Kicinski, Chunfeng Yun,
Kishon Vijay Abraham I, Vinod Koul, Matthias Brugger,
Greg Kroah-Hartman, Stanley Chu, Min Guo, dri-devel, devicetree,
linux-kernel, netdev, linux-arm-kernel, linux-mediatek, linux-usb,
Serge Semin
In-Reply-To: <20201216093012.24406-1-chunfeng.yun@mediatek.com>
Due to usb-device.txt is converted into usb-device.yaml,
so modify reference file names at the same time.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2~v4: no changes
---
Documentation/devicetree/bindings/net/btusb.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/btusb.txt b/Documentation/devicetree/bindings/net/btusb.txt
index b1ad6ee68e90..a9c3f4277f69 100644
--- a/Documentation/devicetree/bindings/net/btusb.txt
+++ b/Documentation/devicetree/bindings/net/btusb.txt
@@ -4,7 +4,7 @@ Generic Bluetooth controller over USB (btusb driver)
Required properties:
- compatible : should comply with the format "usbVID,PID" specified in
- Documentation/devicetree/bindings/usb/usb-device.txt
+ Documentation/devicetree/bindings/usb/usb-device.yaml
At the time of writing, the only OF supported devices
(more may be added later) are:
--
2.18.0
^ permalink raw reply related
* [PATCH v4 05/11] dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema
From: Chunfeng Yun @ 2020-12-16 9:30 UTC (permalink / raw)
To: Rob Herring
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
David S . Miller, Jakub Kicinski, Chunfeng Yun,
Kishon Vijay Abraham I, Vinod Koul, Matthias Brugger,
Greg Kroah-Hartman, Stanley Chu, Min Guo, dri-devel, devicetree,
linux-kernel, netdev, linux-arm-kernel, linux-mediatek, linux-usb,
Serge Semin
In-Reply-To: <20201216093012.24406-1-chunfeng.yun@mediatek.com>
Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml
Cc: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
---
v4: add Reviewed-by Stanley
v3: add Reviewed-by Rob
v2: fix binding check warning of reg in example
---
.../bindings/phy/mediatek,ufs-phy.yaml | 64 +++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-ufs.txt | 38 -----------
2 files changed, 64 insertions(+), 38 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
new file mode 100644
index 000000000000..3a9be82e7f13
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Universal Flash Storage (UFS) M-PHY binding
+
+maintainers:
+ - Stanley Chu <stanley.chu@mediatek.com>
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
+ Each UFS M-PHY node should have its own node.
+ To bind UFS M-PHY with UFS host controller, the controller node should
+ contain a phandle reference to UFS M-PHY node.
+
+properties:
+ $nodename:
+ pattern: "^ufs-phy@[0-9a-f]+$"
+
+ compatible:
+ const: mediatek,mt8183-ufsphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Unipro core control clock.
+ - description: M-PHY core control clock.
+
+ clock-names:
+ items:
+ - const: unipro
+ - const: mp
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ ufsphy: ufs-phy@11fa0000 {
+ compatible = "mediatek,mt8183-ufsphy";
+ reg = <0x11fa0000 0xc000>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt b/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
deleted file mode 100644
index 5789029a1d42..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-MediaTek Universal Flash Storage (UFS) M-PHY binding
---------------------------------------------------------
-
-UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
-Each UFS M-PHY node should have its own node.
-
-To bind UFS M-PHY with UFS host controller, the controller node should
-contain a phandle reference to UFS M-PHY node.
-
-Required properties for UFS M-PHY nodes:
-- compatible : Compatible list, contains the following controller:
- "mediatek,mt8183-ufsphy" for ufs phy
- persent on MT81xx chipsets.
-- reg : Address and length of the UFS M-PHY register set.
-- #phy-cells : This property shall be set to 0.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. Following clocks are
- mandatory.
- "unipro": Unipro core control clock.
- "mp": M-PHY core control clock.
-
-Example:
-
- ufsphy: phy@11fa0000 {
- compatible = "mediatek,mt8183-ufsphy";
- reg = <0 0x11fa0000 0 0xc000>;
- #phy-cells = <0>;
-
- clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
- <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>;
- clock-names = "unipro", "mp";
- };
-
- ufshci@11270000 {
- ...
- phys = <&ufsphy>;
- };
--
2.18.0
^ permalink raw reply related
* [PATCH v4 11/11] MAINTAINERS: update MediaTek PHY/USB entry
From: Chunfeng Yun @ 2020-12-16 9:30 UTC (permalink / raw)
To: Rob Herring
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
David S . Miller, Jakub Kicinski, Chunfeng Yun,
Kishon Vijay Abraham I, Vinod Koul, Matthias Brugger,
Greg Kroah-Hartman, Stanley Chu, Min Guo, dri-devel, devicetree,
linux-kernel, netdev, linux-arm-kernel, linux-mediatek, linux-usb,
Serge Semin
In-Reply-To: <20201216093012.24406-1-chunfeng.yun@mediatek.com>
Due to the phy/usb bindings are converted into YAML schema and
also renamed, update entries.
Meanwhile add drivers/usb/host/mtk-xhci* files.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v3~v4: no changes
v2: new patch
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..360c6131b866 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2084,7 +2084,7 @@ M: Chunfeng Yun <chunfeng.yun@mediatek.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
-F: Documentation/devicetree/bindings/phy/phy-mtk-*
+F: Documentation/devicetree/bindings/phy/mediatek,*
F: drivers/phy/mediatek/
ARM/Microchip (AT91) SoC support
@@ -11139,6 +11139,8 @@ L: linux-usb@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
+F: Documentation/devicetree/bindings/usb/mediatek,*
+F: drivers/usb/host/xhci-mtk*
F: drivers/usb/mtu3/
MEGACHIPS STDPXXXX-GE-B850V3-FW LVDS/DP++ BRIDGES
--
2.18.0
^ permalink raw reply related
* [PATCH v4 03/11] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
From: Chunfeng Yun @ 2020-12-16 9:30 UTC (permalink / raw)
To: Rob Herring
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
David S . Miller, Jakub Kicinski, Chunfeng Yun,
Kishon Vijay Abraham I, Vinod Koul, Matthias Brugger,
Greg Kroah-Hartman, Stanley Chu, Min Guo, dri-devel, devicetree,
linux-kernel, netdev, linux-arm-kernel, linux-mediatek, linux-usb,
Serge Semin
In-Reply-To: <20201216093012.24406-1-chunfeng.yun@mediatek.com>
Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v4: add Reviewed-by Rob
v3:
1. remove type for property with standard unit suffix suggested by Rob
2. remove '|' for descritpion
3. fix yamllint warning
v2:
1. modify description and compatible definition suggested by Rob
---
.../bindings/phy/mediatek,xsphy.yaml | 199 ++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
2 files changed, 199 insertions(+), 109 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
new file mode 100644
index 000000000000..598fd2b95c29
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek XS-PHY Controller Device Tree Bindings
+
+maintainers:
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The XS-PHY controller supports physical layer functionality for USB3.1
+ GEN2 controller on MediaTek SoCs.
+
+ Banks layout of xsphy
+ ----------------------------------
+ port offset bank
+ u2 port0 0x0000 MISC
+ 0x0100 FMREG
+ 0x0300 U2PHY_COM
+ u2 port1 0x1000 MISC
+ 0x1100 FMREG
+ 0x1300 U2PHY_COM
+ u2 port2 0x2000 MISC
+ ...
+ u31 common 0x3000 DIG_GLB
+ 0x3100 PHYA_GLB
+ u31 port0 0x3400 DIG_LN_TOP
+ 0x3500 DIG_LN_TX0
+ 0x3600 DIG_LN_RX0
+ 0x3700 DIG_LN_DAIF
+ 0x3800 PHYA_LN
+ u31 port1 0x3a00 DIG_LN_TOP
+ 0x3b00 DIG_LN_TX0
+ 0x3c00 DIG_LN_RX0
+ 0x3d00 DIG_LN_DAIF
+ 0x3e00 PHYA_LN
+ ...
+ DIG_GLB & PHYA_GLB are shared by U31 ports.
+
+properties:
+ $nodename:
+ pattern: "^xs-phy@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt3611-xsphy
+ - mediatek,mt3612-xsphy
+ - const: mediatek,xsphy
+
+ reg:
+ description:
+ Register shared by multiple U3 ports, exclude port's private register,
+ if only U2 ports provided, shouldn't use the property.
+ maxItems: 1
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+ ranges: true
+
+ mediatek,src-ref-clk-mhz:
+ description:
+ Frequency of reference clock for slew rate calibrate
+ default: 26
+
+ mediatek,src-coef:
+ description:
+ Coefficient for slew rate calibrate, depends on SoC process
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 17
+
+# Required child node:
+patternProperties:
+ "^usb-phy@[0-9a-f]+$":
+ type: object
+ description:
+ A sub-node is required for each port the controller provides.
+ Address range information including the usual 'reg' property
+ is used inside these nodes to describe the controller's topology.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
+
+ clock-names:
+ items:
+ - const: ref
+
+ "#phy-cells":
+ const: 1
+ description: |
+ The cells contain the following arguments.
+
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+
+ # The following optional vendor properties are only for debug or HQA test
+ mediatek,eye-src:
+ description:
+ The value of slew rate calibrate (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-vrt:
+ description:
+ The selection of VRT reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-term:
+ description:
+ The selection of HS_TX TERM reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,efuse-intr:
+ description:
+ The selection of Internal Resistor (U2/U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 63
+
+ mediatek,efuse-tx-imp:
+ description:
+ The selection of TX Impedance (U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ mediatek,efuse-rx-imp:
+ description:
+ The selection of RX Impedance (U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ u3phy: xs-phy@11c40000 {
+ compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
+ reg = <0x11c43000 0x0200>;
+ mediatek,src-ref-clk-mhz = <26>;
+ mediatek,src-coef = <17>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ u2port0: usb-phy@11c40000 {
+ reg = <0x11c40000 0x0400>;
+ clocks = <&clk48m>;
+ clock-names = "ref";
+ mediatek,eye-src = <4>;
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@11c43000 {
+ reg = <0x11c43400 0x0500>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ mediatek,efuse-intr = <28>;
+ #phy-cells = <1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
deleted file mode 100644
index e7caefa0b9c2..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
+++ /dev/null
@@ -1,109 +0,0 @@
-MediaTek XS-PHY binding
---------------------------
-
-The XS-PHY controller supports physical layer functionality for USB3.1
-GEN2 controller on MediaTek SoCs.
-
-Required properties (controller (parent) node):
- - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
- soc-model is the name of SoC, such as mt3611 etc;
- when using "mediatek,xsphy" compatible string, you need SoC specific
- ones in addition, one of:
- - "mediatek,mt3611-xsphy"
-
- - #address-cells, #size-cells : should use the same values as the root node
- - ranges: must be present
-
-Optional properties (controller (parent) node):
- - reg : offset and length of register shared by multiple U3 ports,
- exclude port's private register, if only U2 ports provided,
- shouldn't use the property.
- - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
- calibrate
- - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
- SoC process
-
-Required nodes : a sub-node is required for each port the controller
- provides. Address range information including the usual
- 'reg' property is used inside these nodes to describe
- the controller's topology.
-
-Required properties (port (child) node):
-- reg : address and length of the register set for the port.
-- clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
-- clock-names : must contain
- "ref": 48M reference clock for HighSpeed analog phy; and 26M
- reference clock for SuperSpeedPlus analog phy, sometimes is
- 24M, 25M or 27M, depended on platform.
-- #phy-cells : should be 1
- cell after port phandle is phy type from:
- - PHY_TYPE_USB2
- - PHY_TYPE_USB3
-
-The following optional properties are only for debug or HQA test
-Optional properties (PHY_TYPE_USB2 port (child) node):
-- mediatek,eye-src : u32, the value of slew rate calibrate
-- mediatek,eye-vrt : u32, the selection of VRT reference voltage
-- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
-- mediatek,efuse-intr : u32, the selection of Internal Resistor
-
-Optional properties (PHY_TYPE_USB3 port (child) node):
-- mediatek,efuse-intr : u32, the selection of Internal Resistor
-- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
-- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
-
-Banks layout of xsphy
--------------------------------------------------------------
-port offset bank
-u2 port0 0x0000 MISC
- 0x0100 FMREG
- 0x0300 U2PHY_COM
-u2 port1 0x1000 MISC
- 0x1100 FMREG
- 0x1300 U2PHY_COM
-u2 port2 0x2000 MISC
- ...
-u31 common 0x3000 DIG_GLB
- 0x3100 PHYA_GLB
-u31 port0 0x3400 DIG_LN_TOP
- 0x3500 DIG_LN_TX0
- 0x3600 DIG_LN_RX0
- 0x3700 DIG_LN_DAIF
- 0x3800 PHYA_LN
-u31 port1 0x3a00 DIG_LN_TOP
- 0x3b00 DIG_LN_TX0
- 0x3c00 DIG_LN_RX0
- 0x3d00 DIG_LN_DAIF
- 0x3e00 PHYA_LN
- ...
-
-DIG_GLB & PHYA_GLB are shared by U31 ports.
-
-Example:
-
-u3phy: usb-phy@11c40000 {
- compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
- reg = <0 0x11c43000 0 0x0200>;
- mediatek,src-ref-clk-mhz = <26>;
- mediatek,src-coef = <17>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- u2port0: usb-phy@11c40000 {
- reg = <0 0x11c40000 0 0x0400>;
- clocks = <&clk48m>;
- clock-names = "ref";
- mediatek,eye-src = <4>;
- #phy-cells = <1>;
- };
-
- u3port0: usb-phy@11c43000 {
- reg = <0 0x11c43400 0 0x0500>;
- clocks = <&clk26m>;
- clock-names = "ref";
- mediatek,efuse-intr = <28>;
- #phy-cells = <1>;
- };
-};
--
2.18.0
^ permalink raw reply related
* [PATCH v4 08/11] dt-bindings: usb: convert mediatek,musb.txt to YAML schema
From: Chunfeng Yun @ 2020-12-16 9:30 UTC (permalink / raw)
To: Rob Herring
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
David S . Miller, Jakub Kicinski, Chunfeng Yun,
Kishon Vijay Abraham I, Vinod Koul, Matthias Brugger,
Greg Kroah-Hartman, Stanley Chu, Min Guo, dri-devel, devicetree,
linux-kernel, netdev, linux-arm-kernel, linux-mediatek, linux-usb,
Serge Semin
In-Reply-To: <20201216093012.24406-1-chunfeng.yun@mediatek.com>
Convert mediatek,musb.txt to YAML schema mediatek,musb.yaml
Cc: Min Guo <min.guo@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v4: no changes
v3: add Reviewed-by Rob
v2: new patch
---
.../devicetree/bindings/usb/mediatek,musb.txt | 57 ---------
.../bindings/usb/mediatek,musb.yaml | 113 ++++++++++++++++++
2 files changed, 113 insertions(+), 57 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt
create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.yaml
diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.txt b/Documentation/devicetree/bindings/usb/mediatek,musb.txt
deleted file mode 100644
index 5eedb0296562..000000000000
--- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-MediaTek musb DRD/OTG controller
--------------------------------------------
-
-Required properties:
- - compatible : should be one of:
- "mediatek,mt2701-musb"
- ...
- followed by "mediatek,mtk-musb"
- - reg : specifies physical base address and size of
- the registers
- - interrupts : interrupt used by musb controller
- - interrupt-names : must be "mc"
- - phys : PHY specifier for the OTG phy
- - dr_mode : should be one of "host", "peripheral" or "otg",
- refer to usb/generic.txt
- - clocks : a list of phandle + clock-specifier pairs, one for
- each entry in clock-names
- - clock-names : must contain "main", "mcu", "univpll"
- for clocks of controller
-
-Optional properties:
- - power-domains : a phandle to USB power domain node to control USB's
- MTCMOS
-
-Required child nodes:
- usb connector node as defined in bindings/connector/usb-connector.yaml
-Optional properties:
- - id-gpios : input GPIO for USB ID pin.
- - vbus-gpios : input GPIO for USB VBUS pin.
- - vbus-supply : reference to the VBUS regulator, needed when supports
- dual-role mode
- - usb-role-switch : use USB Role Switch to support dual-role switch, see
- usb/generic.txt.
-
-Example:
-
-usb2: usb@11200000 {
- compatible = "mediatek,mt2701-musb",
- "mediatek,mtk-musb";
- reg = <0 0x11200000 0 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "mc";
- phys = <&u2port2 PHY_TYPE_USB2>;
- dr_mode = "otg";
- clocks = <&pericfg CLK_PERI_USB0>,
- <&pericfg CLK_PERI_USB0_MCU>,
- <&pericfg CLK_PERI_USB_SLV>;
- clock-names = "main","mcu","univpll";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
- usb-role-switch;
- connector{
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
- vbus-supply = <&usb_vbus>;
- };
-};
diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
new file mode 100644
index 000000000000..790efe8b6274
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/mediatek,musb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings
+
+maintainers:
+ - Min Guo <min.guo@mediatek.com>
+
+properties:
+ $nodename:
+ pattern: '^usb@[0-9a-f]+$'
+
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt2701-musb
+ - const: mediatek,mtk-musb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: mc
+
+ clocks:
+ items:
+ - description: The main/core clock
+ - description: The system bus clock
+ - description: The 48Mhz clock
+
+ clock-names:
+ items:
+ - const: main
+ - const: mcu
+ - const: univpll
+
+ phys:
+ maxItems: 1
+
+ usb-role-switch:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Support role switch. See usb/generic.txt
+ type: boolean
+
+ dr_mode:
+ enum:
+ - host
+ - otg
+ - peripheral
+
+ power-domains:
+ description: A phandle to USB power domain node to control USB's MTCMOS
+ maxItems: 1
+
+ connector:
+ $ref: /connector/usb-connector.yaml#
+ description: Connector for dual role switch
+ type: object
+
+dependencies:
+ usb-role-switch: [ 'connector' ]
+ connector: [ 'usb-role-switch' ]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - phys
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt2701-clk.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/mt2701-power.h>
+
+ usb@11200000 {
+ compatible = "mediatek,mt2701-musb", "mediatek,mtk-musb";
+ reg = <0x11200000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "mc";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ dr_mode = "otg";
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB0_MCU>,
+ <&pericfg CLK_PERI_USB_SLV>;
+ clock-names = "main","mcu","univpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ usb-role-switch;
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
+ vbus-supply = <&usb_vbus>;
+ };
+ };
+...
--
2.18.0
^ permalink raw reply related
* [PATCH v4 07/11] dt-bindings: phy: convert MIPI DSI PHY binding to YAML schema
From: Chunfeng Yun @ 2020-12-16 9:30 UTC (permalink / raw)
To: Rob Herring
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
David S . Miller, Jakub Kicinski, Chunfeng Yun,
Kishon Vijay Abraham I, Vinod Koul, Matthias Brugger,
Greg Kroah-Hartman, Stanley Chu, Min Guo, dri-devel, devicetree,
linux-kernel, netdev, linux-arm-kernel, linux-mediatek, linux-usb,
Serge Semin
In-Reply-To: <20201216093012.24406-1-chunfeng.yun@mediatek.com>
Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v4:
1. add maintainer Philipp add support mt8183 suggested by Chun-Kuang
2. use keyword multipleOf suggested by Rob
3. fix typo of 'MIPI' in title
v3: new patch
---
.../display/mediatek/mediatek,dsi.txt | 18 +---
.../bindings/phy/mediatek,dsi-phy.yaml | 85 +++++++++++++++++++
2 files changed, 86 insertions(+), 17 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..8238a86686be 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -22,23 +22,7 @@ Required properties:
MIPI TX Configuration Module
============================
-The MIPI TX configuration module controls the MIPI D-PHY.
-
-Required properties:
-- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- clocks: PLL reference clock
-- clock-output-names: name of the output clock line to the DSI encoder
-- #clock-cells: must be <0>;
-- #phy-cells: must be <0>.
-
-Optional properties:
-- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
- the step is 200.
-- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
- unspecified default values shall be used.
-- nvmem-cell-names: Should be "calibration-data"
+See phy/mediatek,dsi-phy.yaml
Example:
diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
new file mode 100644
index 000000000000..71d4acea1f66
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: The MIPI DSI PHY supports up to 4-lane output.
+
+properties:
+ $nodename:
+ pattern: "^dsi-phy@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - mediatek,mt2701-mipi-tx
+ - mediatek,mt7623-mipi-tx
+ - mediatek,mt8173-mipi-tx
+ - mediatek,mt8183-mipi-tx
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL reference clock
+
+ clock-output-names:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ nvmem-cells:
+ maxItems: 1
+ description: A phandle to the calibration data provided by a nvmem device,
+ if unspecified, default values shall be used.
+
+ nvmem-cell-names:
+ items:
+ - const: calibration-data
+
+ drive-strength-microamp:
+ description: adjust driving current
+ multipleOf: 200
+ minimum: 2000
+ maximum: 6000
+ default: 4600
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-output-names
+ - "#phy-cells"
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ dsi-phy@10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0x10215000 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ drive-strength-microamp = <4000>;
+ nvmem-cells= <&mipi_tx_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+...
--
2.18.0
^ permalink raw reply related
* Re: [PATCH v1 5/8] usb: chipidea: tegra: Support host mode
From: Dmitry Osipenko @ 2020-12-16 9:22 UTC (permalink / raw)
To: Peter Chen
Cc: Thierry Reding, Jonathan Hunter, Greg Kroah-Hartman, Alan Stern,
Felipe Balbi, Matt Merhar, Nicolas Chauvet, Peter Geis,
linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <bb617167-e6a4-221e-5e3b-c9d7a1b50c87@gmail.com>
16.12.2020 12:07, Dmitry Osipenko пишет:
>>> static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
>>> {
>>> struct ehci_hcd *ehci = hcd_to_ehci(hcd);
>>> @@ -160,14 +166,14 @@ static int host_start(struct ci_hdrc *ci)
>>> pinctrl_select_state(ci->platdata->pctl,
>>> ci->platdata->pins_host);
>>>
>>> + ci->hcd = hcd;
>>> +
>>> ret = usb_add_hcd(hcd, 0, 0);
>>> if (ret) {
>>> goto disable_reg;
>>> } else {
>>> struct usb_otg *otg = &ci->otg;
>>>
>>> - ci->hcd = hcd;
>>> -
>> Why this changed?
> The ci->hcd is used by tegra_usb_notify_event() to handle reset event
> and the reset happens once usb_add_hcd() is invoked. Hence we need to
> pre-assign the hcd pointer, otherwise there will be a NULL dereference.
Actually, not a NULL dereference, but the reset will be skipped since we
check whether ci->hcd is NULL in the tegra's reset handler.
^ permalink raw reply
* Re: [PATCH v1 1/8] usb: phy: tegra: Add delay after power up
From: Dmitry Osipenko @ 2020-12-16 9:09 UTC (permalink / raw)
To: Sergei Shtylyov, Thierry Reding, Jonathan Hunter, Peter Chen,
Greg Kroah-Hartman, Alan Stern, Felipe Balbi, Matt Merhar,
Nicolas Chauvet, Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <ce6b80f9-986d-b293-fd33-e4ee4fe1458e@gmail.com>
16.12.2020 11:51, Sergei Shtylyov пишет:
> Hello!
>
> On 15.12.2020 23:21, Dmitry Osipenko wrote:
>
>> The PHY hardware needs the delay of 2ms after power up, otherwise initial
>> interrupt may be lost if USB controller is accessed before PHY is settled
>> down. Previously this issue was masked by implicit delays, but now it
>> pops
>> up after squashing the older ehci-tegra driver into the ChipIdea driver.
>>
>> Tested-by: Matt Merhar <mattmerhar@protonmail.com>
>> Tested-by: Nicolas Chauvet <kwizart@gmail.com>
>> Tested-by: Peter Geis <pgwipeout@gmail.com>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>> drivers/usb/phy/phy-tegra-usb.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/usb/phy/phy-tegra-usb.c
>> b/drivers/usb/phy/phy-tegra-usb.c
>> index 03a333797382..cee9c9dbb775 100644
>> --- a/drivers/usb/phy/phy-tegra-usb.c
>> +++ b/drivers/usb/phy/phy-tegra-usb.c
>> @@ -784,6 +784,9 @@ static int tegra_usb_phy_power_on(struct
>> tegra_usb_phy *phy)
>> phy->powered_on = true;
>> + /* let PHY to settle down */
>
> Let the PHY settle down.
Hi,
I'll improve the comments in v2, thanks.
^ permalink raw reply
* Re: [PATCH v1 5/8] usb: chipidea: tegra: Support host mode
From: Dmitry Osipenko @ 2020-12-16 9:07 UTC (permalink / raw)
To: Peter Chen
Cc: Thierry Reding, Jonathan Hunter, Greg Kroah-Hartman, Alan Stern,
Felipe Balbi, Matt Merhar, Nicolas Chauvet, Peter Geis,
linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20201216060732.GB5595@b29397-desktop>
16.12.2020 09:08, Peter Chen пишет:
> On 20-12-15 23:21:10, Dmitry Osipenko wrote:
>> From: Peter Geis <pgwipeout@gmail.com>
>>
>> struct tegra_usb_soc_info {
>> unsigned long flags;
>> + unsigned int txfifothresh;
>> + enum usb_dr_mode dr_mode;
>> +};
>> +
>> +static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
>> + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
>> + CI_HDRC_OVERRIDE_PHY_CONTROL,
>> + .dr_mode = USB_DR_MODE_HOST,
>> + .txfifothresh = 10,
>> +};
>> +
>> +static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
>> + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
>> + CI_HDRC_OVERRIDE_PHY_CONTROL
>> + .dr_mode = USB_DR_MODE_HOST,
>> + .txfifothresh = 16,
>> };
>>
>> static const struct tegra_usb_soc_info tegra_udc_soc_info = {
>> - .flags = CI_HDRC_REQUIRES_ALIGNED_DMA,
>> + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
>> + CI_HDRC_OVERRIDE_PHY_CONTROL,
>> + .dr_mode = USB_DR_MODE_UNKNOWN,
>> };
>
> What's the usage for this dr_mode? Does these three SoCs only supports
> single mode, it usually sets dr_mode at board dts file to indicate
> USB role for this board.
All Tegra SoCs have three USB controllers. Only one of these three
controllers supports peripheral / OTG modes, the other two controllers
are fixed to the host mode and device trees do not specify the dr_mode
for the host controllers.
Hence we need to enforce the dr_mode=host for the host-mode controllers.
For UDC the default mode is "unknown" because actual mode comes from a
board's device tree.
>> static const struct of_device_id tegra_usb_of_match[] = {
>> {
>> + .compatible = "nvidia,tegra20-ehci",
>> + .data = &tegra20_ehci_soc_info,
>> + }, {
>> + .compatible = "nvidia,tegra30-ehci",
>> + .data = &tegra30_ehci_soc_info,
>> + }, {
>> .compatible = "nvidia,tegra20-udc",
>> .data = &tegra_udc_soc_info,
>
> Your compatible indicates this controller is single USB role, is it
> on purpose?
Yes, the "tegra20/30-ehci" controllers are fixed to the host-mode in
hardware.
...
>> +static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
>> + u32 __iomem *portsc_reg,
>> + unsigned long *flags)
>> +{
>> + u32 saved_usbintr, temp;
>> + unsigned int i, tries;
>> + int retval = 0;
>> +
>> + saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
>> + /* disable USB interrupt */
>> + ehci_writel(ehci, 0, &ehci->regs->intr_enable);
>> + spin_unlock_irqrestore(&ehci->lock, *flags);
>> +
>> + /*
>> + * Here we have to do Port Reset at most twice for
>> + * Port Enable bit to be set.
>> + */
>> + for (i = 0; i < 2; i++) {
>> + temp = ehci_readl(ehci, portsc_reg);
>> + temp |= PORT_RESET;
>> + ehci_writel(ehci, temp, portsc_reg);
>> + mdelay(10);
>
> Needs accurate delay? How about usleep_range?
To be hones I don't know for sure whether hub_control() could be used
from interrupt context. This mdelay is borrowed from the older
ehci-tegra driver.
Are you suggesting that it should be safe to sleep here?
...
>> static int tegra_usb_probe(struct platform_device *pdev)
>> {
>> const struct tegra_usb_soc_info *soc;
>> @@ -83,24 +292,49 @@ static int tegra_usb_probe(struct platform_device *pdev)
>> return err;
>> }
>>
>> + if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
>> + usb->needs_double_reset = true;
>> +
>> + err = tegra_usb_reset_controller(&pdev->dev);
>> + if (err) {
>> + dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
>> + goto fail_power_off;
>> + }
>> +
>> + /*
>> + * USB controller registers shan't be touched before PHY is
>
> %s/shan't/shouldn't
ok
...
>> static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
>> {
>> struct ehci_hcd *ehci = hcd_to_ehci(hcd);
>> @@ -160,14 +166,14 @@ static int host_start(struct ci_hdrc *ci)
>> pinctrl_select_state(ci->platdata->pctl,
>> ci->platdata->pins_host);
>>
>> + ci->hcd = hcd;
>> +
>> ret = usb_add_hcd(hcd, 0, 0);
>> if (ret) {
>> goto disable_reg;
>> } else {
>> struct usb_otg *otg = &ci->otg;
>>
>> - ci->hcd = hcd;
>> -
>
> Why this changed?
The ci->hcd is used by tegra_usb_notify_event() to handle reset event
and the reset happens once usb_add_hcd() is invoked. Hence we need to
pre-assign the hcd pointer, otherwise there will be a NULL dereference.
^ permalink raw reply
* Re: [PATCH v1 1/8] usb: phy: tegra: Add delay after power up
From: Sergei Shtylyov @ 2020-12-16 8:51 UTC (permalink / raw)
To: Dmitry Osipenko, Thierry Reding, Jonathan Hunter, Peter Chen,
Greg Kroah-Hartman, Alan Stern, Felipe Balbi, Matt Merhar,
Nicolas Chauvet, Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-2-digetx@gmail.com>
Hello!
On 15.12.2020 23:21, Dmitry Osipenko wrote:
> The PHY hardware needs the delay of 2ms after power up, otherwise initial
> interrupt may be lost if USB controller is accessed before PHY is settled
> down. Previously this issue was masked by implicit delays, but now it pops
> up after squashing the older ehci-tegra driver into the ChipIdea driver.
>
> Tested-by: Matt Merhar <mattmerhar@protonmail.com>
> Tested-by: Nicolas Chauvet <kwizart@gmail.com>
> Tested-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/usb/phy/phy-tegra-usb.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
> index 03a333797382..cee9c9dbb775 100644
> --- a/drivers/usb/phy/phy-tegra-usb.c
> +++ b/drivers/usb/phy/phy-tegra-usb.c
> @@ -784,6 +784,9 @@ static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
>
> phy->powered_on = true;
>
> + /* let PHY to settle down */
Let the PHY settle down.
> + usleep_range(2000, 2500);
> +
> return 0;
> }
>
MBR, Sergei
^ permalink raw reply
* Re: [PATCH v1 5/8] usb: chipidea: tegra: Support host mode
From: Peter Chen @ 2020-12-16 6:08 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Greg Kroah-Hartman, Alan Stern,
Felipe Balbi, Matt Merhar, Nicolas Chauvet, Peter Geis,
linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20201215202113.30394-6-digetx@gmail.com>
On 20-12-15 23:21:10, Dmitry Osipenko wrote:
> From: Peter Geis <pgwipeout@gmail.com>
>
> struct tegra_usb_soc_info {
> unsigned long flags;
> + unsigned int txfifothresh;
> + enum usb_dr_mode dr_mode;
> +};
> +
> +static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
> + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
> + CI_HDRC_OVERRIDE_PHY_CONTROL,
> + .dr_mode = USB_DR_MODE_HOST,
> + .txfifothresh = 10,
> +};
> +
> +static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
> + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
> + CI_HDRC_OVERRIDE_PHY_CONTROL
> + .dr_mode = USB_DR_MODE_HOST,
> + .txfifothresh = 16,
> };
>
> static const struct tegra_usb_soc_info tegra_udc_soc_info = {
> - .flags = CI_HDRC_REQUIRES_ALIGNED_DMA,
> + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
> + CI_HDRC_OVERRIDE_PHY_CONTROL,
> + .dr_mode = USB_DR_MODE_UNKNOWN,
> };
What's the usage for this dr_mode? Does these three SoCs only supports
single mode, it usually sets dr_mode at board dts file to indicate
USB role for this board.
>
> static const struct of_device_id tegra_usb_of_match[] = {
> {
> + .compatible = "nvidia,tegra20-ehci",
> + .data = &tegra20_ehci_soc_info,
> + }, {
> + .compatible = "nvidia,tegra30-ehci",
> + .data = &tegra30_ehci_soc_info,
> + }, {
> .compatible = "nvidia,tegra20-udc",
> .data = &tegra_udc_soc_info,
Your compatible indicates this controller is single USB role, is it
on purpose?
> }, {
> @@ -47,6 +81,181 @@ static const struct of_device_id tegra_usb_of_match[] = {
> };
> MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
>
> +static int tegra_usb_reset_controller(struct device *dev)
> +{
> + struct reset_control *rst, *rst_utmi;
> + struct device_node *phy_np;
> + int err;
> +
> + rst = devm_reset_control_get_shared(dev, "usb");
> + if (IS_ERR(rst)) {
> + dev_err(dev, "can't get ehci reset: %pe\n", rst);
> + return PTR_ERR(rst);
> + }
> +
> + phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
> + if (!phy_np)
> + return -ENOENT;
> +
> + /*
> + * The 1st USB controller contains some UTMI pad registers that are
> + * global for all the controllers on the chip. Those registers are
> + * also cleared when reset is asserted to the 1st controller.
> + */
> + rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
> + if (IS_ERR(rst_utmi)) {
> + dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
> + dev_warn(dev, "continuing, but please update your DT\n");
> + } else {
> + /*
> + * PHY driver performs UTMI-pads reset in a case of a
> + * non-legacy DT.
> + */
> + reset_control_put(rst_utmi);
> + }
> +
> + of_node_put(phy_np);
> +
> + /* reset control is shared, hence initialize it first */
> + err = reset_control_deassert(rst);
> + if (err)
> + return err;
> +
> + err = reset_control_assert(rst);
> + if (err)
> + return err;
> +
> + udelay(1);
> +
> + err = reset_control_deassert(rst);
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
> +{
> + struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
> + struct ehci_hcd *ehci;
> +
> + switch (event) {
> + case CI_HDRC_CONTROLLER_RESET_EVENT:
> + if (ci->hcd) {
> + ehci = hcd_to_ehci(ci->hcd);
> + ehci->has_tdi_phy_lpm = false;
> + ehci_writel(ehci, usb->soc->txfifothresh << 16,
> + &ehci->regs->txfill_tuning);
> + }
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
> + u32 __iomem *portsc_reg,
> + unsigned long *flags)
> +{
> + u32 saved_usbintr, temp;
> + unsigned int i, tries;
> + int retval = 0;
> +
> + saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
> + /* disable USB interrupt */
> + ehci_writel(ehci, 0, &ehci->regs->intr_enable);
> + spin_unlock_irqrestore(&ehci->lock, *flags);
> +
> + /*
> + * Here we have to do Port Reset at most twice for
> + * Port Enable bit to be set.
> + */
> + for (i = 0; i < 2; i++) {
> + temp = ehci_readl(ehci, portsc_reg);
> + temp |= PORT_RESET;
> + ehci_writel(ehci, temp, portsc_reg);
> + mdelay(10);
Needs accurate delay? How about usleep_range?
> + temp &= ~PORT_RESET;
> + ehci_writel(ehci, temp, portsc_reg);
> + mdelay(1);
> + tries = 100;
> + do {
> + mdelay(1);
> + /*
> + * Up to this point, Port Enable bit is
> + * expected to be set after 2 ms waiting.
> + * USB1 usually takes extra 45 ms, for safety,
> + * we take 100 ms as timeout.
> + */
> + temp = ehci_readl(ehci, portsc_reg);
> + } while (!(temp & PORT_PE) && tries--);
> + if (temp & PORT_PE)
> + break;
> + }
> + if (i == 2)
> + retval = -ETIMEDOUT;
> +
> + /*
> + * Clear Connect Status Change bit if it's set.
> + * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
> + */
> + if (temp & PORT_CSC)
> + ehci_writel(ehci, PORT_CSC, portsc_reg);
> +
> + /*
> + * Write to clear any interrupt status bits that might be set
> + * during port reset.
> + */
> + temp = ehci_readl(ehci, &ehci->regs->status);
> + ehci_writel(ehci, temp, &ehci->regs->status);
> +
> + /* restore original interrupt-enable bits */
> + spin_lock_irqsave(&ehci->lock, *flags);
> + ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
> +
> + return retval;
> +}
> +
> +static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
> + u16 wIndex, char *buf, u16 wLength,
> + bool *done, unsigned long *flags)
> +{
> + struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
> + struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
> + u32 __iomem *status_reg;
> + int retval = 0;
> +
> + status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
> +
> + switch (typeReq) {
> + case SetPortFeature:
> + if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
> + break;
> +
> + /* for USB1 port we need to issue Port Reset twice internally */
> + retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
> + *done = true;
> + break;
> + }
> +
> + return retval;
> +}
> +
> +static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
> +{
> + /*
> + * Touching any register which belongs to AHB clock domain will
> + * hang CPU if USB controller is put into low power mode because
> + * AHB USB clock is gated on Tegra in the LPM.
> + *
> + * Tegra PHY has a separate register for checking the clock status
> + * and usb_phy_set_suspend() takes care of gating/ungating the clocks
> + * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
> + * shouldn't be touched directly by the CI driver.
> + */
> + usb_phy_set_suspend(ci->usb_phy, enable);
> +}
> +
> static int tegra_usb_probe(struct platform_device *pdev)
> {
> const struct tegra_usb_soc_info *soc;
> @@ -83,24 +292,49 @@ static int tegra_usb_probe(struct platform_device *pdev)
> return err;
> }
>
> + if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
> + usb->needs_double_reset = true;
> +
> + err = tegra_usb_reset_controller(&pdev->dev);
> + if (err) {
> + dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
> + goto fail_power_off;
> + }
> +
> + /*
> + * USB controller registers shan't be touched before PHY is
%s/shan't/shouldn't
> + * initialized, otherwise CPU will hang because clocks are gated.
> + * PHY driver controls gating of internal USB clocks on Tegra.
> + */
> + err = usb_phy_init(usb->phy);
> + if (err)
> + goto fail_power_off;
> +
> + platform_set_drvdata(pdev, usb);
> +
> /* setup and register ChipIdea HDRC device */
> + usb->soc = soc;
> usb->data.name = "tegra-usb";
> usb->data.flags = soc->flags;
> usb->data.usb_phy = usb->phy;
> + usb->data.dr_mode = soc->dr_mode;
> usb->data.capoffset = DEF_CAPOFFSET;
> + usb->data.enter_lpm = tegra_usb_enter_lpm;
> + usb->data.hub_control = tegra_ehci_hub_control;
> + usb->data.notify_event = tegra_usb_notify_event;
>
> usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
> pdev->num_resources, &usb->data);
> if (IS_ERR(usb->dev)) {
> err = PTR_ERR(usb->dev);
> dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
> - goto fail_power_off;
> + goto phy_shutdown;
> }
>
> - platform_set_drvdata(pdev, usb);
> -
> return 0;
>
> +phy_shutdown:
> + usb_phy_shutdown(usb->phy);
> fail_power_off:
> clk_disable_unprepare(usb->clk);
> return err;
> @@ -111,6 +345,7 @@ static int tegra_usb_remove(struct platform_device *pdev)
> struct tegra_usb *usb = platform_get_drvdata(pdev);
>
> ci_hdrc_remove_device(usb->dev);
> + usb_phy_shutdown(usb->phy);
> clk_disable_unprepare(usb->clk);
>
> return 0;
> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> index aa40e510b806..3f6c21406dbd 100644
> --- a/drivers/usb/chipidea/core.c
> +++ b/drivers/usb/chipidea/core.c
> @@ -195,7 +195,7 @@ static void hw_wait_phy_stable(void)
> }
>
> /* The PHY enters/leaves low power mode */
> -static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
> +static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
> {
> enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
> bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
> @@ -208,6 +208,11 @@ static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
> 0);
> }
>
> +static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
> +{
> + return ci->platdata->enter_lpm(ci, enable);
> +}
> +
> static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
> {
> u32 reg;
> @@ -790,6 +795,9 @@ static int ci_get_platdata(struct device *dev,
> platdata->pins_device = p;
> }
>
> + if (!platdata->enter_lpm)
> + platdata->enter_lpm = ci_hdrc_enter_lpm_common;
> +
> return 0;
> }
>
> diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c
> index 48e4a5ca1835..b8a4c44ab580 100644
> --- a/drivers/usb/chipidea/host.c
> +++ b/drivers/usb/chipidea/host.c
> @@ -29,6 +29,12 @@ struct ehci_ci_priv {
> bool enabled;
> };
>
> +struct ci_hdrc_dma_aligned_buffer {
> + void *kmalloc_ptr;
> + void *old_xfer_buffer;
> + u8 data[0];
> +};
> +
> static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
> {
> struct ehci_hcd *ehci = hcd_to_ehci(hcd);
> @@ -160,14 +166,14 @@ static int host_start(struct ci_hdrc *ci)
> pinctrl_select_state(ci->platdata->pctl,
> ci->platdata->pins_host);
>
> + ci->hcd = hcd;
> +
> ret = usb_add_hcd(hcd, 0, 0);
> if (ret) {
> goto disable_reg;
> } else {
> struct usb_otg *otg = &ci->otg;
>
> - ci->hcd = hcd;
> -
Why this changed?
Peter
> if (ci_otg_is_fsm_mode(ci)) {
> otg->host = &hcd->self;
> hcd->self.otg_port = 1;
> @@ -237,6 +243,7 @@ static int ci_ehci_hub_control(
> u32 temp;
> unsigned long flags;
> int retval = 0;
> + bool done = false;
> struct device *dev = hcd->self.controller;
> struct ci_hdrc *ci = dev_get_drvdata(dev);
>
> @@ -244,6 +251,13 @@ static int ci_ehci_hub_control(
>
> spin_lock_irqsave(&ehci->lock, flags);
>
> + if (ci->platdata->hub_control) {
> + retval = ci->platdata->hub_control(ci, typeReq, wValue, wIndex,
> + buf, wLength, &done, &flags);
> + if (done)
> + goto done;
> + }
> +
> if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
> temp = ehci_readl(ehci, status_reg);
> if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
> @@ -349,6 +363,86 @@ static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
> return 0;
> }
>
> +static void ci_hdrc_free_dma_aligned_buffer(struct urb *urb)
> +{
> + struct ci_hdrc_dma_aligned_buffer *temp;
> + size_t length;
> +
> + if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
> + return;
> +
> + temp = container_of(urb->transfer_buffer,
> + struct ci_hdrc_dma_aligned_buffer, data);
> +
> + if (usb_urb_dir_in(urb)) {
> + if (usb_pipeisoc(urb->pipe))
> + length = urb->transfer_buffer_length;
> + else
> + length = urb->actual_length;
> +
> + memcpy(temp->old_xfer_buffer, temp->data, length);
> + }
> + urb->transfer_buffer = temp->old_xfer_buffer;
> + kfree(temp->kmalloc_ptr);
> +
> + urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
> +}
> +
> +static int ci_hdrc_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
> +{
> + struct ci_hdrc_dma_aligned_buffer *temp, *kmalloc_ptr;
> + const unsigned int ci_hdrc_usb_dma_align = 32;
> + size_t kmalloc_size;
> +
> + if (urb->num_sgs || urb->sg || urb->transfer_buffer_length == 0 ||
> + !((uintptr_t)urb->transfer_buffer & (ci_hdrc_usb_dma_align - 1)))
> + return 0;
> +
> + /* Allocate a buffer with enough padding for alignment */
> + kmalloc_size = urb->transfer_buffer_length +
> + sizeof(struct ci_hdrc_dma_aligned_buffer) +
> + ci_hdrc_usb_dma_align - 1;
> +
> + kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
> + if (!kmalloc_ptr)
> + return -ENOMEM;
> +
> + /* Position our struct dma_aligned_buffer such that data is aligned */
> + temp = PTR_ALIGN(kmalloc_ptr + 1, ci_hdrc_usb_dma_align) - 1;
> + temp->kmalloc_ptr = kmalloc_ptr;
> + temp->old_xfer_buffer = urb->transfer_buffer;
> + if (usb_urb_dir_out(urb))
> + memcpy(temp->data, urb->transfer_buffer,
> + urb->transfer_buffer_length);
> + urb->transfer_buffer = temp->data;
> +
> + urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
> +
> + return 0;
> +}
> +
> +static int ci_hdrc_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
> + gfp_t mem_flags)
> +{
> + int ret;
> +
> + ret = ci_hdrc_alloc_dma_aligned_buffer(urb, mem_flags);
> + if (ret)
> + return ret;
> +
> + ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
> + if (ret)
> + ci_hdrc_free_dma_aligned_buffer(urb);
> +
> + return ret;
> +}
> +
> +static void ci_hdrc_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
> +{
> + usb_hcd_unmap_urb_for_dma(hcd, urb);
> + ci_hdrc_free_dma_aligned_buffer(urb);
> +}
> +
> int ci_hdrc_host_init(struct ci_hdrc *ci)
> {
> struct ci_role_driver *rdrv;
> @@ -366,6 +460,11 @@ int ci_hdrc_host_init(struct ci_hdrc *ci)
> rdrv->name = "host";
> ci->roles[CI_ROLE_HOST] = rdrv;
>
> + if (ci->platdata->flags & CI_HDRC_REQUIRES_ALIGNED_DMA) {
> + ci_ehci_hc_driver.map_urb_for_dma = ci_hdrc_map_urb_for_dma;
> + ci_ehci_hc_driver.unmap_urb_for_dma = ci_hdrc_unmap_urb_for_dma;
> + }
> +
> return 0;
> }
>
> diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
> index 025b41687ce9..edf3342507f1 100644
> --- a/include/linux/usb/chipidea.h
> +++ b/include/linux/usb/chipidea.h
> @@ -88,6 +88,12 @@ struct ci_hdrc_platform_data {
> struct pinctrl_state *pins_default;
> struct pinctrl_state *pins_host;
> struct pinctrl_state *pins_device;
> +
> + /* platform-specific hooks */
> + int (*hub_control)(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
> + u16 wIndex, char *buf, u16 wLength,
> + bool *done, unsigned long *flags);
> + void (*enter_lpm)(struct ci_hdrc *ci, bool enable);
> };
>
> /* Default offset of capability registers */
> --
> 2.29.2
>
--
Thanks,
Peter Chen
^ permalink raw reply
* Re: [PATCH] xhci: Introduce max wait timeout in xhci_handshake()
From: Chen Yu @ 2020-12-16 4:36 UTC (permalink / raw)
To: Greg KH
Cc: Mathias Nyman, linux-usb, linux-kernel, Muchowski, MaciejX,
Paczynski, Lukasz
In-Reply-To: <X9i8grY9BRbbCqNZ@kroah.com>
Hi Greg,
thanks for taking a look at this.
On Tue, Dec 15, 2020 at 02:39:14PM +0100, Greg KH wrote:
> On Tue, Dec 15, 2020 at 09:22:40PM +0800, Chen Yu wrote:
> > The time to finish a xhci_handshake() is platform specific
> > and sometimes during suspend resume test the followng
> > errors were encountered:
> > [53455.418330] ACPI: Waking up from system sleep state S4
> > [66838.490856] xhci_hcd 0000:00:14.0: xHCI dying, ignoring interrupt.
> > Shouldn't IRQs be disabled?
> > After changing the poll time granularity from 1 usec to 20 usec in
> > xhci_handshake() this issue was not reproduced. While tuning on the
> > poll time granularity might be painful on different platforms, it is
> > applicable to introduce a module parameter to allow the xhci driver to wait
> > for at max 16 ms.
> >
> > Reported-by: "Muchowski, MaciejX" <maciejx.muchowski@intel.com>
>
> I doubt the "X" is part of this person's name, please just spell it out
> without the "," please.
>
Okay, will do.
> > Signed-off-by: Chen Yu <yu.c.chen@intel.com>
> > ---
> > drivers/usb/host/xhci.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
> > index d4a8d0efbbc4..b8be9f3cc987 100644
> > --- a/drivers/usb/host/xhci.c
> > +++ b/drivers/usb/host/xhci.c
> > @@ -38,6 +38,10 @@ static unsigned long long quirks;
> > module_param(quirks, ullong, S_IRUGO);
> > MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
> >
> > +static int wait_handshake;
> > +module_param(wait_handshake, int, 0644);
> > +MODULE_PARM_DESC(wait_handshake, "Force wait for completion of handshake");
>
> This is not the 1990's, we are not adding new module parameters that no
> one will know how to change.
>
Okay.
> Make this dynamic, and per-device, and work properly instead. This can
> not handle multiple controllers in the system at all :(
>
Okay. After checking the error log, enlarging the timeout might not be enough
and I'll dig into it a little deeper and send feedback.
thanks,
Chenyu
> thanks,
>
> greg k-h
^ permalink raw reply
* Re: port power is on again after turning off by user space
From: Peter Chen @ 2020-12-16 2:56 UTC (permalink / raw)
To: Alan Stern; +Cc: Jun Li, linux-usb@vger.kernel.org
In-Reply-To: <20201215155541.GA195633@rowland.harvard.edu>
On 20-12-15 10:55:41, Alan Stern wrote:
> On Tue, Dec 15, 2020 at 09:57:53AM +0000, Peter Chen wrote:
> >
> > > > > Hi Alan,
> > > > >
> > > > > I use one HUB power control application
> > > > >
> > > (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> > > com%2Fmvp%2Fuhubctl&data=04%7C01%7Cpeter.chen%40nxp.com%7C
> > > 736ece19bc7a430c98b808d8a0b6975c%7C686ea1d3bc2b4c6fa92cd99c5c3016
> > > 35%7C0%7C0%7C637436053362151022%7CUnknown%7CTWFpbGZsb3d8eyJ
> > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> > > C1000&sdata=lptf1XO5yeb6lQbAFlKUrZ%2BEX5ATXQRftGwm26WowFA%
> > > 3D&reserved=0) to investigate power switchable HUB, and find the kernel
> > > turns port power on again at drivers/usb/core/hub.c, after port power is turned
> > > off by user space.
> > > > >
> > > > > 5122 if (hub_is_port_power_switchable(hub)
> > > > > 5123 && !port_is_power_on(hub,
> > > portstatus)
> > > > > 5124 && !port_dev->port_owner)
> > > > > 5125 set_port_feature(hdev, port1,
> > > USB_PORT_FEAT_POWER);
> > > > >
> > > > > The main sequence for testing turn port power off like below:
> > > > >
> > > > > - uhubctl sends command to turn specifc port (eg, 2-1.4) power off.
> > > > > - devio at kernel gets that command, and send to hub.
> > > > > - port power is off, the hub_event is triggered due to port status is changed.
> > > > > - usb_disconnect is called, but port power is on again by kernel at function
> > > hub_port_connect.
> > > > >
> > > > > I can't find the code history why the port power needs to turn on after
> > > device is disconnected, do you know why?
> > > > > Any sugguestions to fix it? Thanks.
> > > >
> > > > Seems in this case the port need claimed by user app, I am seeing this
> > > > commit
> > > >
> > > > commit fbaecff06a7db4defa899a664fe2758e5161b39d
> > > > Author: Deepak Das <deepakdas.linux@gmail.com>
> > > > Date: Wed Jan 21 23:39:58 2015 +0530
> > > >
> > > > usb: core: hub: modify hub reset logic in hub driver
> > > >
> > > > Currently if port power is turned off by user on hub port
> > > > using USBDEVFS then port power is turned back ON
> > > > by hub driver.
> > > > This commit modifies hub reset logic in hub_port_connect() to prevent
> > > > hub driver from turning back the port power ON if port is not owned
> > > > by kernel.
> > > >
> > > > Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
> > > > Acked-by: Alan Stern <stern@rowland.harvard.edu>
> > > > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > > >
> > > > diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index
> > > > b4bfa3a..3e9c4d4 100644
> > > > --- a/drivers/usb/core/hub.c
> > > > +++ b/drivers/usb/core/hub.c
> > > > @@ -4655,9 +4655,13 @@ static void hub_port_connect(struct usb_hub
> > > > *hub, int port1, u16 portstatus,
> > > > if (!(portstatus & USB_PORT_STAT_CONNECTION) ||
> > > > test_bit(port1, hub->removed_bits)) {
> > > >
> > > > - /* maybe switch power back on (e.g. root hub was reset)
> > > */
> > > > + /*
> > > > + * maybe switch power back on (e.g. root hub was reset)
> > > > + * but only if the port isn't owned by someone else.
> > > > + */
> > > > if (hub_is_port_power_switchable(hub)
> > > > - && !port_is_power_on(hub,
> > > portstatus))
> > > > + && !port_is_power_on(hub,
> > > portstatus)
> > > > + && !port_dev->port_owner)
> > > > set_port_feature(hdev, port1,
> > > > USB_PORT_FEAT_POWER);
> > > >
> > > > if (portstatus & USB_PORT_STAT_ENABLE)
> > > >
> > >
> > > Yes, I saw this commit. But the port is owned by kernel, the device on the port
> > > could be enumerated by kernel, just the power on the port could be changed by
> > > user space.
>
> You've got the general idea.
>
> Normally ports are owned by the hub driver. If one of them loses power
> for some reason (for example, the user turns it off), the hub driver
> will turn the power back on. This is because the hub driver wants
> ports to be powered at all times unless they are in runtime suspend.
>
> The way to prevent the hub driver from managing the port power is to
> claim the port for the user, by issuing the USBDEVFS_CLAIM_PORT ioctl.
> Also, when that is done, the kernel wno't try to manage a device
> attached to the port -- that is, the kernel won't automatically install
> a configuration for a new device and it won't try to probe drivers for
> the device's interfaces if the user installs a config.
>
Alan, we have several use cases for power switchable HUB, one of the use
cases is USB port is managed by kernel (eg, needs mass storage
class), but needs to toggle port power, is it reasonable we add a sysfs
entry to support it?
--
Thanks,
Peter Chen
^ permalink raw reply
* Re: [GIT PULL] USB / Thunderbolt driver changes for 5.11-rc1
From: pr-tracker-bot @ 2020-12-15 22:22 UTC (permalink / raw)
To: Greg KH; +Cc: Linus Torvalds, Andrew Morton, linux-kernel, linux-usb
In-Reply-To: <X9iNHGpdcl3cAlo4@kroah.com>
The pull request you sent on Tue, 15 Dec 2020 11:17:00 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git tags/usb-5.11-rc1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/0cee54c890a40051928991072e5d1cd279611dfd
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
^ permalink raw reply
* [PATCH v1 0/8] Support Runtime PM and host mode by Tegra ChipIdea USB driver
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
This series implements Runtime PM support for the Tegra ChipIdea USB driver.
It also squashes the older ehci-tegra driver into the ChipIdea driver, hence
the RPM is supported by both UDC and host controllers, secondly this opens
opportunity for implementing OTG support in the future.
Patchset was tested on various Tegra20, Tegra30 and Tegra124 devices.
Thanks to Peter Geis, Matt Merhar and Nicolas Chauvet for helping with
the extensive and productive testing!
Dmitry Osipenko (7):
usb: phy: tegra: Add delay after power up
usb: phy: tegra: Support waking up from a low power mode
usb: chipidea: tegra: Remove MODULE_ALIAS
usb: chipidea: tegra: Rename UDC to USB
usb: chipidea: tegra: Support runtime PM
usb: host: ehci-tegra: Remove the driver
ARM: tegra_defconfig: Enable USB_CHIPIDEA and remove USB_EHCI_TEGRA
Peter Geis (1):
usb: chipidea: tegra: Support host mode
arch/arm/configs/tegra_defconfig | 3 +-
drivers/usb/chipidea/Kconfig | 3 +-
drivers/usb/chipidea/ci_hdrc_tegra.c | 327 +++++++++++++--
drivers/usb/chipidea/core.c | 10 +-
drivers/usb/chipidea/host.c | 103 ++++-
drivers/usb/host/Kconfig | 9 -
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ehci-tegra.c | 604 ---------------------------
drivers/usb/phy/phy-tegra-usb.c | 82 +++-
include/linux/usb/chipidea.h | 6 +
include/linux/usb/tegra_usb_phy.h | 2 +
11 files changed, 481 insertions(+), 669 deletions(-)
delete mode 100644 drivers/usb/host/ehci-tegra.c
--
2.29.2
^ permalink raw reply
* [PATCH v1 4/8] usb: chipidea: tegra: Rename UDC to USB
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
Rename all occurrences in the code from "udc" to "usb" and change the
Kconfig entry in order to show that this driver supports USB modes other
than device-only mode. The follow up patch will add host-mode support and
it will be cleaner to perform the renaming separately, i.e. in this patch.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/usb/chipidea/Kconfig | 2 +-
drivers/usb/chipidea/ci_hdrc_tegra.c | 78 ++++++++++++++--------------
2 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig
index 8bafcfc6080d..8685ead6ccc7 100644
--- a/drivers/usb/chipidea/Kconfig
+++ b/drivers/usb/chipidea/Kconfig
@@ -53,7 +53,7 @@ config USB_CHIPIDEA_GENERIC
default USB_CHIPIDEA
config USB_CHIPIDEA_TEGRA
- tristate "Enable Tegra UDC glue driver" if EMBEDDED
+ tristate "Enable Tegra USB glue driver" if EMBEDDED
depends on OF
depends on USB_CHIPIDEA_UDC
default USB_CHIPIDEA
diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c
index 10eaaba2a3f0..d8efa80aa1c2 100644
--- a/drivers/usb/chipidea/ci_hdrc_tegra.c
+++ b/drivers/usb/chipidea/ci_hdrc_tegra.c
@@ -12,7 +12,7 @@
#include "ci.h"
-struct tegra_udc {
+struct tegra_usb {
struct ci_hdrc_platform_data data;
struct platform_device *dev;
@@ -20,15 +20,15 @@ struct tegra_udc {
struct clk *clk;
};
-struct tegra_udc_soc_info {
+struct tegra_usb_soc_info {
unsigned long flags;
};
-static const struct tegra_udc_soc_info tegra_udc_soc_info = {
+static const struct tegra_usb_soc_info tegra_udc_soc_info = {
.flags = CI_HDRC_REQUIRES_ALIGNED_DMA,
};
-static const struct of_device_id tegra_udc_of_match[] = {
+static const struct of_device_id tegra_usb_of_match[] = {
{
.compatible = "nvidia,tegra20-udc",
.data = &tegra_udc_soc_info,
@@ -45,16 +45,16 @@ static const struct of_device_id tegra_udc_of_match[] = {
/* sentinel */
}
};
-MODULE_DEVICE_TABLE(of, tegra_udc_of_match);
+MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
-static int tegra_udc_probe(struct platform_device *pdev)
+static int tegra_usb_probe(struct platform_device *pdev)
{
- const struct tegra_udc_soc_info *soc;
- struct tegra_udc *udc;
+ const struct tegra_usb_soc_info *soc;
+ struct tegra_usb *usb;
int err;
- udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
- if (!udc)
+ usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL);
+ if (!usb)
return -ENOMEM;
soc = of_device_get_match_data(&pdev->dev);
@@ -63,69 +63,69 @@ static int tegra_udc_probe(struct platform_device *pdev)
return -EINVAL;
}
- udc->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
- if (IS_ERR(udc->phy)) {
- err = PTR_ERR(udc->phy);
+ usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
+ if (IS_ERR(usb->phy)) {
+ err = PTR_ERR(usb->phy);
dev_err(&pdev->dev, "failed to get PHY: %d\n", err);
return err;
}
- udc->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(udc->clk)) {
- err = PTR_ERR(udc->clk);
+ usb->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(usb->clk)) {
+ err = PTR_ERR(usb->clk);
dev_err(&pdev->dev, "failed to get clock: %d\n", err);
return err;
}
- err = clk_prepare_enable(udc->clk);
+ err = clk_prepare_enable(usb->clk);
if (err < 0) {
dev_err(&pdev->dev, "failed to enable clock: %d\n", err);
return err;
}
/* setup and register ChipIdea HDRC device */
- udc->data.name = "tegra-udc";
- udc->data.flags = soc->flags;
- udc->data.usb_phy = udc->phy;
- udc->data.capoffset = DEF_CAPOFFSET;
-
- udc->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
- pdev->num_resources, &udc->data);
- if (IS_ERR(udc->dev)) {
- err = PTR_ERR(udc->dev);
+ usb->data.name = "tegra-usb";
+ usb->data.flags = soc->flags;
+ usb->data.usb_phy = usb->phy;
+ usb->data.capoffset = DEF_CAPOFFSET;
+
+ usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
+ pdev->num_resources, &usb->data);
+ if (IS_ERR(usb->dev)) {
+ err = PTR_ERR(usb->dev);
dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
goto fail_power_off;
}
- platform_set_drvdata(pdev, udc);
+ platform_set_drvdata(pdev, usb);
return 0;
fail_power_off:
- clk_disable_unprepare(udc->clk);
+ clk_disable_unprepare(usb->clk);
return err;
}
-static int tegra_udc_remove(struct platform_device *pdev)
+static int tegra_usb_remove(struct platform_device *pdev)
{
- struct tegra_udc *udc = platform_get_drvdata(pdev);
+ struct tegra_usb *usb = platform_get_drvdata(pdev);
- ci_hdrc_remove_device(udc->dev);
- clk_disable_unprepare(udc->clk);
+ ci_hdrc_remove_device(usb->dev);
+ clk_disable_unprepare(usb->clk);
return 0;
}
-static struct platform_driver tegra_udc_driver = {
+static struct platform_driver tegra_usb_driver = {
.driver = {
- .name = "tegra-udc",
- .of_match_table = tegra_udc_of_match,
+ .name = "tegra-usb",
+ .of_match_table = tegra_usb_of_match,
},
- .probe = tegra_udc_probe,
- .remove = tegra_udc_remove,
+ .probe = tegra_usb_probe,
+ .remove = tegra_usb_remove,
};
-module_platform_driver(tegra_udc_driver);
+module_platform_driver(tegra_usb_driver);
-MODULE_DESCRIPTION("NVIDIA Tegra USB device mode driver");
+MODULE_DESCRIPTION("NVIDIA Tegra USB driver");
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
MODULE_LICENSE("GPL v2");
--
2.29.2
^ permalink raw reply related
* [PATCH v1 8/8] ARM: tegra_defconfig: Enable USB_CHIPIDEA and remove USB_EHCI_TEGRA
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
The ehci-tegra driver was superseded by the generic ChipIdea USB driver,
update the tegra's defconfig accordingly.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/configs/tegra_defconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 74739a52a8ad..ae0709265493 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -237,12 +237,13 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_TEGRA=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ACM=y
CONFIG_USB_WDM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
--
2.29.2
^ permalink raw reply related
* [PATCH v1 7/8] usb: host: ehci-tegra: Remove the driver
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
The ChipIdea driver now provides USB2 host mode support for NVIDIA Tegra
SoCs. The ehci-tegra driver is obsolete now, remove it.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/usb/host/Kconfig | 9 -
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ehci-tegra.c | 604 ----------------------------------
3 files changed, 614 deletions(-)
delete mode 100644 drivers/usb/host/ehci-tegra.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 31e59309da1f..9c9e6ff9c43a 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -266,15 +266,6 @@ config USB_EHCI_HCD_AT91
Enables support for the on-chip EHCI controller on
Atmel chips.
-config USB_EHCI_TEGRA
- tristate "NVIDIA Tegra HCD support"
- depends on ARCH_TEGRA
- select USB_EHCI_ROOT_HUB_TT
- select USB_TEGRA_PHY
- help
- This driver enables support for the internal USB Host Controllers
- found in NVIDIA Tegra SoCs. The controllers are EHCI compliant.
-
config USB_EHCI_HCD_PPC_OF
bool "EHCI support for PPC USB controller on OF platform bus"
depends on PPC
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c1b08703af10..3e4d298d851f 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -47,7 +47,6 @@ obj-$(CONFIG_USB_EHCI_HCD_SPEAR) += ehci-spear.o
obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-st.o
obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
-obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o
obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
deleted file mode 100644
index 869d9c4de5fc..000000000000
--- a/drivers/usb/host/ehci-tegra.c
+++ /dev/null
@@ -1,604 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2009 - 2013 NVIDIA Corporation
- */
-
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/of_gpio.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-#include <linux/reset.h>
-#include <linux/slab.h>
-#include <linux/usb/ehci_def.h>
-#include <linux/usb/tegra_usb_phy.h>
-#include <linux/usb.h>
-#include <linux/usb/hcd.h>
-#include <linux/usb/otg.h>
-
-#include "ehci.h"
-
-#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
-
-#define TEGRA_USB_DMA_ALIGN 32
-
-#define DRIVER_DESC "Tegra EHCI driver"
-#define DRV_NAME "tegra-ehci"
-
-static struct hc_driver __read_mostly tegra_ehci_hc_driver;
-
-struct tegra_ehci_soc_config {
- bool has_hostpc;
-};
-
-struct tegra_ehci_hcd {
- struct clk *clk;
- struct reset_control *rst;
- int port_resuming;
- bool needs_double_reset;
-};
-
-static int tegra_reset_usb_controller(struct platform_device *pdev)
-{
- struct device_node *phy_np;
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct tegra_ehci_hcd *tegra =
- (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
- struct reset_control *rst;
- int err;
-
- phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
- if (!phy_np)
- return -ENOENT;
-
- /*
- * The 1st USB controller contains some UTMI pad registers that are
- * global for all the controllers on the chip. Those registers are
- * also cleared when reset is asserted to the 1st controller.
- */
- rst = of_reset_control_get_shared(phy_np, "utmi-pads");
- if (IS_ERR(rst)) {
- dev_warn(&pdev->dev,
- "can't get utmi-pads reset from the PHY\n");
- dev_warn(&pdev->dev,
- "continuing, but please update your DT\n");
- } else {
- /*
- * PHY driver performs UTMI-pads reset in a case of
- * non-legacy DT.
- */
- reset_control_put(rst);
- }
-
- of_node_put(phy_np);
-
- /* reset control is shared, hence initialize it first */
- err = reset_control_deassert(tegra->rst);
- if (err)
- return err;
-
- err = reset_control_assert(tegra->rst);
- if (err)
- return err;
-
- udelay(1);
-
- err = reset_control_deassert(tegra->rst);
- if (err)
- return err;
-
- return 0;
-}
-
-static int tegra_ehci_internal_port_reset(
- struct ehci_hcd *ehci,
- u32 __iomem *portsc_reg
-)
-{
- u32 temp;
- unsigned long flags;
- int retval = 0;
- int i, tries;
- u32 saved_usbintr;
-
- spin_lock_irqsave(&ehci->lock, flags);
- saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
- /* disable USB interrupt */
- ehci_writel(ehci, 0, &ehci->regs->intr_enable);
- spin_unlock_irqrestore(&ehci->lock, flags);
-
- /*
- * Here we have to do Port Reset at most twice for
- * Port Enable bit to be set.
- */
- for (i = 0; i < 2; i++) {
- temp = ehci_readl(ehci, portsc_reg);
- temp |= PORT_RESET;
- ehci_writel(ehci, temp, portsc_reg);
- mdelay(10);
- temp &= ~PORT_RESET;
- ehci_writel(ehci, temp, portsc_reg);
- mdelay(1);
- tries = 100;
- do {
- mdelay(1);
- /*
- * Up to this point, Port Enable bit is
- * expected to be set after 2 ms waiting.
- * USB1 usually takes extra 45 ms, for safety,
- * we take 100 ms as timeout.
- */
- temp = ehci_readl(ehci, portsc_reg);
- } while (!(temp & PORT_PE) && tries--);
- if (temp & PORT_PE)
- break;
- }
- if (i == 2)
- retval = -ETIMEDOUT;
-
- /*
- * Clear Connect Status Change bit if it's set.
- * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
- */
- if (temp & PORT_CSC)
- ehci_writel(ehci, PORT_CSC, portsc_reg);
-
- /*
- * Write to clear any interrupt status bits that might be set
- * during port reset.
- */
- temp = ehci_readl(ehci, &ehci->regs->status);
- ehci_writel(ehci, temp, &ehci->regs->status);
-
- /* restore original interrupt enable bits */
- ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
- return retval;
-}
-
-static int tegra_ehci_hub_control(
- struct usb_hcd *hcd,
- u16 typeReq,
- u16 wValue,
- u16 wIndex,
- char *buf,
- u16 wLength
-)
-{
- struct ehci_hcd *ehci = hcd_to_ehci(hcd);
- struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
- u32 __iomem *status_reg;
- u32 temp;
- unsigned long flags;
- int retval = 0;
-
- status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
-
- spin_lock_irqsave(&ehci->lock, flags);
-
- if (typeReq == GetPortStatus) {
- temp = ehci_readl(ehci, status_reg);
- if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
- /* Resume completed, re-enable disconnect detection */
- tegra->port_resuming = 0;
- tegra_usb_phy_postresume(hcd->usb_phy);
- }
- }
-
- else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
- temp = ehci_readl(ehci, status_reg);
- if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
- retval = -EPIPE;
- goto done;
- }
-
- temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
- temp |= PORT_WKDISC_E | PORT_WKOC_E;
- ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
-
- /*
- * If a transaction is in progress, there may be a delay in
- * suspending the port. Poll until the port is suspended.
- */
- if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
- PORT_SUSPEND, 5000))
- pr_err("%s: timeout waiting for SUSPEND\n", __func__);
-
- set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
- goto done;
- }
-
- /* For USB1 port we need to issue Port Reset twice internally */
- if (tegra->needs_double_reset &&
- (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
- spin_unlock_irqrestore(&ehci->lock, flags);
- return tegra_ehci_internal_port_reset(ehci, status_reg);
- }
-
- /*
- * Tegra host controller will time the resume operation to clear the bit
- * when the port control state switches to HS or FS Idle. This behavior
- * is different from EHCI where the host controller driver is required
- * to set this bit to a zero after the resume duration is timed in the
- * driver.
- */
- else if (typeReq == ClearPortFeature &&
- wValue == USB_PORT_FEAT_SUSPEND) {
- temp = ehci_readl(ehci, status_reg);
- if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
- retval = -EPIPE;
- goto done;
- }
-
- if (!(temp & PORT_SUSPEND))
- goto done;
-
- /* Disable disconnect detection during port resume */
- tegra_usb_phy_preresume(hcd->usb_phy);
-
- ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
-
- temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
- /* start resume signalling */
- ehci_writel(ehci, temp | PORT_RESUME, status_reg);
- set_bit(wIndex-1, &ehci->resuming_ports);
-
- spin_unlock_irqrestore(&ehci->lock, flags);
- msleep(20);
- spin_lock_irqsave(&ehci->lock, flags);
-
- /* Poll until the controller clears RESUME and SUSPEND */
- if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
- pr_err("%s: timeout waiting for RESUME\n", __func__);
- if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
- pr_err("%s: timeout waiting for SUSPEND\n", __func__);
-
- ehci->reset_done[wIndex-1] = 0;
- clear_bit(wIndex-1, &ehci->resuming_ports);
-
- tegra->port_resuming = 1;
- goto done;
- }
-
- spin_unlock_irqrestore(&ehci->lock, flags);
-
- /* Handle the hub control events here */
- return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
-
-done:
- spin_unlock_irqrestore(&ehci->lock, flags);
- return retval;
-}
-
-struct dma_aligned_buffer {
- void *kmalloc_ptr;
- void *old_xfer_buffer;
- u8 data[];
-};
-
-static void free_dma_aligned_buffer(struct urb *urb)
-{
- struct dma_aligned_buffer *temp;
- size_t length;
-
- if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
- return;
-
- temp = container_of(urb->transfer_buffer,
- struct dma_aligned_buffer, data);
-
- if (usb_urb_dir_in(urb)) {
- if (usb_pipeisoc(urb->pipe))
- length = urb->transfer_buffer_length;
- else
- length = urb->actual_length;
-
- memcpy(temp->old_xfer_buffer, temp->data, length);
- }
- urb->transfer_buffer = temp->old_xfer_buffer;
- kfree(temp->kmalloc_ptr);
-
- urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
-}
-
-static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
-{
- struct dma_aligned_buffer *temp, *kmalloc_ptr;
- size_t kmalloc_size;
-
- if (urb->num_sgs || urb->sg ||
- urb->transfer_buffer_length == 0 ||
- !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
- return 0;
-
- /* Allocate a buffer with enough padding for alignment */
- kmalloc_size = urb->transfer_buffer_length +
- sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
-
- kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
- if (!kmalloc_ptr)
- return -ENOMEM;
-
- /* Position our struct dma_aligned_buffer such that data is aligned */
- temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
- temp->kmalloc_ptr = kmalloc_ptr;
- temp->old_xfer_buffer = urb->transfer_buffer;
- if (usb_urb_dir_out(urb))
- memcpy(temp->data, urb->transfer_buffer,
- urb->transfer_buffer_length);
- urb->transfer_buffer = temp->data;
-
- urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
-
- return 0;
-}
-
-static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
- gfp_t mem_flags)
-{
- int ret;
-
- ret = alloc_dma_aligned_buffer(urb, mem_flags);
- if (ret)
- return ret;
-
- ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
- if (ret)
- free_dma_aligned_buffer(urb);
-
- return ret;
-}
-
-static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
-{
- usb_hcd_unmap_urb_for_dma(hcd, urb);
- free_dma_aligned_buffer(urb);
-}
-
-static const struct tegra_ehci_soc_config tegra30_soc_config = {
- .has_hostpc = true,
-};
-
-static const struct tegra_ehci_soc_config tegra20_soc_config = {
- .has_hostpc = false,
-};
-
-static const struct of_device_id tegra_ehci_of_match[] = {
- { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
- { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
- { },
-};
-
-static int tegra_ehci_probe(struct platform_device *pdev)
-{
- const struct of_device_id *match;
- const struct tegra_ehci_soc_config *soc_config;
- struct resource *res;
- struct usb_hcd *hcd;
- struct ehci_hcd *ehci;
- struct tegra_ehci_hcd *tegra;
- int err = 0;
- int irq;
- struct usb_phy *u_phy;
-
- match = of_match_device(tegra_ehci_of_match, &pdev->dev);
- if (!match) {
- dev_err(&pdev->dev, "Error: No device match found\n");
- return -ENODEV;
- }
- soc_config = match->data;
-
- /* Right now device-tree probed devices don't get dma_mask set.
- * Since shared usb code relies on it, set it here for now.
- * Once we have dma capability bindings this can go away.
- */
- err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
- if (err)
- return err;
-
- hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
- dev_name(&pdev->dev));
- if (!hcd) {
- dev_err(&pdev->dev, "Unable to create HCD\n");
- return -ENOMEM;
- }
- platform_set_drvdata(pdev, hcd);
- ehci = hcd_to_ehci(hcd);
- tegra = (struct tegra_ehci_hcd *)ehci->priv;
-
- hcd->has_tt = 1;
-
- tegra->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(tegra->clk)) {
- dev_err(&pdev->dev, "Can't get ehci clock\n");
- err = PTR_ERR(tegra->clk);
- goto cleanup_hcd_create;
- }
-
- tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb");
- if (IS_ERR(tegra->rst)) {
- dev_err(&pdev->dev, "Can't get ehci reset\n");
- err = PTR_ERR(tegra->rst);
- goto cleanup_hcd_create;
- }
-
- err = clk_prepare_enable(tegra->clk);
- if (err)
- goto cleanup_hcd_create;
-
- err = tegra_reset_usb_controller(pdev);
- if (err) {
- dev_err(&pdev->dev, "Failed to reset controller\n");
- goto cleanup_clk_en;
- }
-
- u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
- if (IS_ERR(u_phy)) {
- err = -EPROBE_DEFER;
- goto cleanup_clk_en;
- }
- hcd->usb_phy = u_phy;
- hcd->skip_phy_initialization = 1;
-
- tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
- "nvidia,needs-double-reset");
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hcd->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(hcd->regs)) {
- err = PTR_ERR(hcd->regs);
- goto cleanup_clk_en;
- }
- hcd->rsrc_start = res->start;
- hcd->rsrc_len = resource_size(res);
-
- ehci->caps = hcd->regs + 0x100;
- ehci->has_hostpc = soc_config->has_hostpc;
-
- err = usb_phy_init(hcd->usb_phy);
- if (err) {
- dev_err(&pdev->dev, "Failed to initialize phy\n");
- goto cleanup_clk_en;
- }
-
- u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
- GFP_KERNEL);
- if (!u_phy->otg) {
- err = -ENOMEM;
- goto cleanup_phy;
- }
- u_phy->otg->host = hcd_to_bus(hcd);
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- err = irq;
- goto cleanup_phy;
- }
-
- otg_set_host(u_phy->otg, &hcd->self);
-
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err) {
- dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto cleanup_otg_set_host;
- }
- device_wakeup_enable(hcd->self.controller);
-
- return err;
-
-cleanup_otg_set_host:
- otg_set_host(u_phy->otg, NULL);
-cleanup_phy:
- usb_phy_shutdown(hcd->usb_phy);
-cleanup_clk_en:
- clk_disable_unprepare(tegra->clk);
-cleanup_hcd_create:
- usb_put_hcd(hcd);
- return err;
-}
-
-static int tegra_ehci_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct tegra_ehci_hcd *tegra =
- (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
-
- usb_remove_hcd(hcd);
- otg_set_host(hcd->usb_phy->otg, NULL);
- usb_phy_shutdown(hcd->usb_phy);
- clk_disable_unprepare(tegra->clk);
- usb_put_hcd(hcd);
-
- return 0;
-}
-
-static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
- if (hcd->driver->shutdown)
- hcd->driver->shutdown(hcd);
-}
-
-static struct platform_driver tegra_ehci_driver = {
- .probe = tegra_ehci_probe,
- .remove = tegra_ehci_remove,
- .shutdown = tegra_ehci_hcd_shutdown,
- .driver = {
- .name = DRV_NAME,
- .of_match_table = tegra_ehci_of_match,
- }
-};
-
-static int tegra_ehci_reset(struct usb_hcd *hcd)
-{
- struct ehci_hcd *ehci = hcd_to_ehci(hcd);
- int retval;
- int txfifothresh;
-
- retval = ehci_setup(hcd);
- if (retval)
- return retval;
-
- /*
- * We should really pull this value out of tegra_ehci_soc_config, but
- * to avoid needing access to it, make use of the fact that Tegra20 is
- * the only one so far that needs a value of 10, and Tegra20 is the
- * only one which doesn't set has_hostpc.
- */
- txfifothresh = ehci->has_hostpc ? 0x10 : 10;
- ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
-
- return 0;
-}
-
-static const struct ehci_driver_overrides tegra_overrides __initconst = {
- .extra_priv_size = sizeof(struct tegra_ehci_hcd),
- .reset = tegra_ehci_reset,
-};
-
-static int __init ehci_tegra_init(void)
-{
- if (usb_disabled())
- return -ENODEV;
-
- pr_info(DRV_NAME ": " DRIVER_DESC "\n");
-
- ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
-
- /*
- * The Tegra HW has some unusual quirks, which require Tegra-specific
- * workarounds. We override certain hc_driver functions here to
- * achieve that. We explicitly do not enhance ehci_driver_overrides to
- * allow this more easily, since this is an unusual case, and we don't
- * want to encourage others to override these functions by making it
- * too easy.
- */
-
- tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
- tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
- tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
-
- return platform_driver_register(&tegra_ehci_driver);
-}
-module_init(ehci_tegra_init);
-
-static void __exit ehci_tegra_cleanup(void)
-{
- platform_driver_unregister(&tegra_ehci_driver);
-}
-module_exit(ehci_tegra_cleanup);
-
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRV_NAME);
-MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);
--
2.29.2
^ permalink raw reply related
* [PATCH v1 5/8] usb: chipidea: tegra: Support host mode
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
From: Peter Geis <pgwipeout@gmail.com>
Add USB host mode to the Tegra HDRC driver. This allows us to benefit from
support provided by the generic ChipIdea driver instead of duplicating the
effort in a separate ehci-terga driver.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/usb/chipidea/Kconfig | 1 -
drivers/usb/chipidea/ci_hdrc_tegra.c | 243 ++++++++++++++++++++++++++-
drivers/usb/chipidea/core.c | 10 +-
drivers/usb/chipidea/host.c | 103 +++++++++++-
include/linux/usb/chipidea.h | 6 +
5 files changed, 355 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig
index 8685ead6ccc7..661818e8fed6 100644
--- a/drivers/usb/chipidea/Kconfig
+++ b/drivers/usb/chipidea/Kconfig
@@ -55,7 +55,6 @@ config USB_CHIPIDEA_GENERIC
config USB_CHIPIDEA_TEGRA
tristate "Enable Tegra USB glue driver" if EMBEDDED
depends on OF
- depends on USB_CHIPIDEA_UDC
default USB_CHIPIDEA
endif
diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c
index d8efa80aa1c2..fff130f08996 100644
--- a/drivers/usb/chipidea/ci_hdrc_tegra.c
+++ b/drivers/usb/chipidea/ci_hdrc_tegra.c
@@ -4,11 +4,18 @@
*/
#include <linux/clk.h>
+#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/reset.h>
+#include <linux/usb.h>
#include <linux/usb/chipidea.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/of.h>
+#include <linux/usb/phy.h>
+
+#include "../host/ehci.h"
#include "ci.h"
@@ -16,20 +23,47 @@ struct tegra_usb {
struct ci_hdrc_platform_data data;
struct platform_device *dev;
+ const struct tegra_usb_soc_info *soc;
struct usb_phy *phy;
struct clk *clk;
+
+ bool needs_double_reset;
};
struct tegra_usb_soc_info {
unsigned long flags;
+ unsigned int txfifothresh;
+ enum usb_dr_mode dr_mode;
+};
+
+static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
+ .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
+ CI_HDRC_OVERRIDE_PHY_CONTROL,
+ .dr_mode = USB_DR_MODE_HOST,
+ .txfifothresh = 10,
+};
+
+static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
+ .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
+ CI_HDRC_OVERRIDE_PHY_CONTROL
+ .dr_mode = USB_DR_MODE_HOST,
+ .txfifothresh = 16,
};
static const struct tegra_usb_soc_info tegra_udc_soc_info = {
- .flags = CI_HDRC_REQUIRES_ALIGNED_DMA,
+ .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
+ CI_HDRC_OVERRIDE_PHY_CONTROL,
+ .dr_mode = USB_DR_MODE_UNKNOWN,
};
static const struct of_device_id tegra_usb_of_match[] = {
{
+ .compatible = "nvidia,tegra20-ehci",
+ .data = &tegra20_ehci_soc_info,
+ }, {
+ .compatible = "nvidia,tegra30-ehci",
+ .data = &tegra30_ehci_soc_info,
+ }, {
.compatible = "nvidia,tegra20-udc",
.data = &tegra_udc_soc_info,
}, {
@@ -47,6 +81,181 @@ static const struct of_device_id tegra_usb_of_match[] = {
};
MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
+static int tegra_usb_reset_controller(struct device *dev)
+{
+ struct reset_control *rst, *rst_utmi;
+ struct device_node *phy_np;
+ int err;
+
+ rst = devm_reset_control_get_shared(dev, "usb");
+ if (IS_ERR(rst)) {
+ dev_err(dev, "can't get ehci reset: %pe\n", rst);
+ return PTR_ERR(rst);
+ }
+
+ phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
+ if (!phy_np)
+ return -ENOENT;
+
+ /*
+ * The 1st USB controller contains some UTMI pad registers that are
+ * global for all the controllers on the chip. Those registers are
+ * also cleared when reset is asserted to the 1st controller.
+ */
+ rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
+ if (IS_ERR(rst_utmi)) {
+ dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
+ dev_warn(dev, "continuing, but please update your DT\n");
+ } else {
+ /*
+ * PHY driver performs UTMI-pads reset in a case of a
+ * non-legacy DT.
+ */
+ reset_control_put(rst_utmi);
+ }
+
+ of_node_put(phy_np);
+
+ /* reset control is shared, hence initialize it first */
+ err = reset_control_deassert(rst);
+ if (err)
+ return err;
+
+ err = reset_control_assert(rst);
+ if (err)
+ return err;
+
+ udelay(1);
+
+ err = reset_control_deassert(rst);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
+{
+ struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
+ struct ehci_hcd *ehci;
+
+ switch (event) {
+ case CI_HDRC_CONTROLLER_RESET_EVENT:
+ if (ci->hcd) {
+ ehci = hcd_to_ehci(ci->hcd);
+ ehci->has_tdi_phy_lpm = false;
+ ehci_writel(ehci, usb->soc->txfifothresh << 16,
+ &ehci->regs->txfill_tuning);
+ }
+ break;
+ }
+
+ return 0;
+}
+
+static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
+ u32 __iomem *portsc_reg,
+ unsigned long *flags)
+{
+ u32 saved_usbintr, temp;
+ unsigned int i, tries;
+ int retval = 0;
+
+ saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
+ /* disable USB interrupt */
+ ehci_writel(ehci, 0, &ehci->regs->intr_enable);
+ spin_unlock_irqrestore(&ehci->lock, *flags);
+
+ /*
+ * Here we have to do Port Reset at most twice for
+ * Port Enable bit to be set.
+ */
+ for (i = 0; i < 2; i++) {
+ temp = ehci_readl(ehci, portsc_reg);
+ temp |= PORT_RESET;
+ ehci_writel(ehci, temp, portsc_reg);
+ mdelay(10);
+ temp &= ~PORT_RESET;
+ ehci_writel(ehci, temp, portsc_reg);
+ mdelay(1);
+ tries = 100;
+ do {
+ mdelay(1);
+ /*
+ * Up to this point, Port Enable bit is
+ * expected to be set after 2 ms waiting.
+ * USB1 usually takes extra 45 ms, for safety,
+ * we take 100 ms as timeout.
+ */
+ temp = ehci_readl(ehci, portsc_reg);
+ } while (!(temp & PORT_PE) && tries--);
+ if (temp & PORT_PE)
+ break;
+ }
+ if (i == 2)
+ retval = -ETIMEDOUT;
+
+ /*
+ * Clear Connect Status Change bit if it's set.
+ * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
+ */
+ if (temp & PORT_CSC)
+ ehci_writel(ehci, PORT_CSC, portsc_reg);
+
+ /*
+ * Write to clear any interrupt status bits that might be set
+ * during port reset.
+ */
+ temp = ehci_readl(ehci, &ehci->regs->status);
+ ehci_writel(ehci, temp, &ehci->regs->status);
+
+ /* restore original interrupt-enable bits */
+ spin_lock_irqsave(&ehci->lock, *flags);
+ ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
+
+ return retval;
+}
+
+static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
+ u16 wIndex, char *buf, u16 wLength,
+ bool *done, unsigned long *flags)
+{
+ struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
+ struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
+ u32 __iomem *status_reg;
+ int retval = 0;
+
+ status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
+
+ switch (typeReq) {
+ case SetPortFeature:
+ if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
+ break;
+
+ /* for USB1 port we need to issue Port Reset twice internally */
+ retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
+ *done = true;
+ break;
+ }
+
+ return retval;
+}
+
+static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
+{
+ /*
+ * Touching any register which belongs to AHB clock domain will
+ * hang CPU if USB controller is put into low power mode because
+ * AHB USB clock is gated on Tegra in the LPM.
+ *
+ * Tegra PHY has a separate register for checking the clock status
+ * and usb_phy_set_suspend() takes care of gating/ungating the clocks
+ * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
+ * shouldn't be touched directly by the CI driver.
+ */
+ usb_phy_set_suspend(ci->usb_phy, enable);
+}
+
static int tegra_usb_probe(struct platform_device *pdev)
{
const struct tegra_usb_soc_info *soc;
@@ -83,24 +292,49 @@ static int tegra_usb_probe(struct platform_device *pdev)
return err;
}
+ if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
+ usb->needs_double_reset = true;
+
+ err = tegra_usb_reset_controller(&pdev->dev);
+ if (err) {
+ dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
+ goto fail_power_off;
+ }
+
+ /*
+ * USB controller registers shan't be touched before PHY is
+ * initialized, otherwise CPU will hang because clocks are gated.
+ * PHY driver controls gating of internal USB clocks on Tegra.
+ */
+ err = usb_phy_init(usb->phy);
+ if (err)
+ goto fail_power_off;
+
+ platform_set_drvdata(pdev, usb);
+
/* setup and register ChipIdea HDRC device */
+ usb->soc = soc;
usb->data.name = "tegra-usb";
usb->data.flags = soc->flags;
usb->data.usb_phy = usb->phy;
+ usb->data.dr_mode = soc->dr_mode;
usb->data.capoffset = DEF_CAPOFFSET;
+ usb->data.enter_lpm = tegra_usb_enter_lpm;
+ usb->data.hub_control = tegra_ehci_hub_control;
+ usb->data.notify_event = tegra_usb_notify_event;
usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
pdev->num_resources, &usb->data);
if (IS_ERR(usb->dev)) {
err = PTR_ERR(usb->dev);
dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
- goto fail_power_off;
+ goto phy_shutdown;
}
- platform_set_drvdata(pdev, usb);
-
return 0;
+phy_shutdown:
+ usb_phy_shutdown(usb->phy);
fail_power_off:
clk_disable_unprepare(usb->clk);
return err;
@@ -111,6 +345,7 @@ static int tegra_usb_remove(struct platform_device *pdev)
struct tegra_usb *usb = platform_get_drvdata(pdev);
ci_hdrc_remove_device(usb->dev);
+ usb_phy_shutdown(usb->phy);
clk_disable_unprepare(usb->clk);
return 0;
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index aa40e510b806..3f6c21406dbd 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -195,7 +195,7 @@ static void hw_wait_phy_stable(void)
}
/* The PHY enters/leaves low power mode */
-static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
+static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
{
enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
@@ -208,6 +208,11 @@ static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
0);
}
+static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
+{
+ return ci->platdata->enter_lpm(ci, enable);
+}
+
static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
{
u32 reg;
@@ -790,6 +795,9 @@ static int ci_get_platdata(struct device *dev,
platdata->pins_device = p;
}
+ if (!platdata->enter_lpm)
+ platdata->enter_lpm = ci_hdrc_enter_lpm_common;
+
return 0;
}
diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c
index 48e4a5ca1835..b8a4c44ab580 100644
--- a/drivers/usb/chipidea/host.c
+++ b/drivers/usb/chipidea/host.c
@@ -29,6 +29,12 @@ struct ehci_ci_priv {
bool enabled;
};
+struct ci_hdrc_dma_aligned_buffer {
+ void *kmalloc_ptr;
+ void *old_xfer_buffer;
+ u8 data[0];
+};
+
static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
@@ -160,14 +166,14 @@ static int host_start(struct ci_hdrc *ci)
pinctrl_select_state(ci->platdata->pctl,
ci->platdata->pins_host);
+ ci->hcd = hcd;
+
ret = usb_add_hcd(hcd, 0, 0);
if (ret) {
goto disable_reg;
} else {
struct usb_otg *otg = &ci->otg;
- ci->hcd = hcd;
-
if (ci_otg_is_fsm_mode(ci)) {
otg->host = &hcd->self;
hcd->self.otg_port = 1;
@@ -237,6 +243,7 @@ static int ci_ehci_hub_control(
u32 temp;
unsigned long flags;
int retval = 0;
+ bool done = false;
struct device *dev = hcd->self.controller;
struct ci_hdrc *ci = dev_get_drvdata(dev);
@@ -244,6 +251,13 @@ static int ci_ehci_hub_control(
spin_lock_irqsave(&ehci->lock, flags);
+ if (ci->platdata->hub_control) {
+ retval = ci->platdata->hub_control(ci, typeReq, wValue, wIndex,
+ buf, wLength, &done, &flags);
+ if (done)
+ goto done;
+ }
+
if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
temp = ehci_readl(ehci, status_reg);
if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
@@ -349,6 +363,86 @@ static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
return 0;
}
+static void ci_hdrc_free_dma_aligned_buffer(struct urb *urb)
+{
+ struct ci_hdrc_dma_aligned_buffer *temp;
+ size_t length;
+
+ if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
+ return;
+
+ temp = container_of(urb->transfer_buffer,
+ struct ci_hdrc_dma_aligned_buffer, data);
+
+ if (usb_urb_dir_in(urb)) {
+ if (usb_pipeisoc(urb->pipe))
+ length = urb->transfer_buffer_length;
+ else
+ length = urb->actual_length;
+
+ memcpy(temp->old_xfer_buffer, temp->data, length);
+ }
+ urb->transfer_buffer = temp->old_xfer_buffer;
+ kfree(temp->kmalloc_ptr);
+
+ urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
+}
+
+static int ci_hdrc_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
+{
+ struct ci_hdrc_dma_aligned_buffer *temp, *kmalloc_ptr;
+ const unsigned int ci_hdrc_usb_dma_align = 32;
+ size_t kmalloc_size;
+
+ if (urb->num_sgs || urb->sg || urb->transfer_buffer_length == 0 ||
+ !((uintptr_t)urb->transfer_buffer & (ci_hdrc_usb_dma_align - 1)))
+ return 0;
+
+ /* Allocate a buffer with enough padding for alignment */
+ kmalloc_size = urb->transfer_buffer_length +
+ sizeof(struct ci_hdrc_dma_aligned_buffer) +
+ ci_hdrc_usb_dma_align - 1;
+
+ kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
+ if (!kmalloc_ptr)
+ return -ENOMEM;
+
+ /* Position our struct dma_aligned_buffer such that data is aligned */
+ temp = PTR_ALIGN(kmalloc_ptr + 1, ci_hdrc_usb_dma_align) - 1;
+ temp->kmalloc_ptr = kmalloc_ptr;
+ temp->old_xfer_buffer = urb->transfer_buffer;
+ if (usb_urb_dir_out(urb))
+ memcpy(temp->data, urb->transfer_buffer,
+ urb->transfer_buffer_length);
+ urb->transfer_buffer = temp->data;
+
+ urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
+
+ return 0;
+}
+
+static int ci_hdrc_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
+ gfp_t mem_flags)
+{
+ int ret;
+
+ ret = ci_hdrc_alloc_dma_aligned_buffer(urb, mem_flags);
+ if (ret)
+ return ret;
+
+ ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
+ if (ret)
+ ci_hdrc_free_dma_aligned_buffer(urb);
+
+ return ret;
+}
+
+static void ci_hdrc_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
+{
+ usb_hcd_unmap_urb_for_dma(hcd, urb);
+ ci_hdrc_free_dma_aligned_buffer(urb);
+}
+
int ci_hdrc_host_init(struct ci_hdrc *ci)
{
struct ci_role_driver *rdrv;
@@ -366,6 +460,11 @@ int ci_hdrc_host_init(struct ci_hdrc *ci)
rdrv->name = "host";
ci->roles[CI_ROLE_HOST] = rdrv;
+ if (ci->platdata->flags & CI_HDRC_REQUIRES_ALIGNED_DMA) {
+ ci_ehci_hc_driver.map_urb_for_dma = ci_hdrc_map_urb_for_dma;
+ ci_ehci_hc_driver.unmap_urb_for_dma = ci_hdrc_unmap_urb_for_dma;
+ }
+
return 0;
}
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index 025b41687ce9..edf3342507f1 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -88,6 +88,12 @@ struct ci_hdrc_platform_data {
struct pinctrl_state *pins_default;
struct pinctrl_state *pins_host;
struct pinctrl_state *pins_device;
+
+ /* platform-specific hooks */
+ int (*hub_control)(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
+ u16 wIndex, char *buf, u16 wLength,
+ bool *done, unsigned long *flags);
+ void (*enter_lpm)(struct ci_hdrc *ci, bool enable);
};
/* Default offset of capability registers */
--
2.29.2
^ permalink raw reply related
* [PATCH v1 3/8] usb: chipidea: tegra: Remove MODULE_ALIAS
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
The module alias is provided by the OF core for the OF drivers, it
overrides the alias set by the drivers. Hence remove the unneeded macro
in order to keep the driver code cleaner.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/usb/chipidea/ci_hdrc_tegra.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c
index 7455df0ede49..10eaaba2a3f0 100644
--- a/drivers/usb/chipidea/ci_hdrc_tegra.c
+++ b/drivers/usb/chipidea/ci_hdrc_tegra.c
@@ -128,5 +128,4 @@ module_platform_driver(tegra_udc_driver);
MODULE_DESCRIPTION("NVIDIA Tegra USB device mode driver");
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
-MODULE_ALIAS("platform:tegra-udc");
MODULE_LICENSE("GPL v2");
--
2.29.2
^ permalink raw reply related
* [PATCH v1 6/8] usb: chipidea: tegra: Support runtime PM
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
Tegra PHY driver now supports waking up controller from a low power mode.
Enable runtime PM in order to put controller into the LPM during idle.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/usb/chipidea/ci_hdrc_tegra.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c
index fff130f08996..4531c2b069fe 100644
--- a/drivers/usb/chipidea/ci_hdrc_tegra.c
+++ b/drivers/usb/chipidea/ci_hdrc_tegra.c
@@ -38,21 +38,24 @@ struct tegra_usb_soc_info {
static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
- CI_HDRC_OVERRIDE_PHY_CONTROL,
+ CI_HDRC_OVERRIDE_PHY_CONTROL |
+ CI_HDRC_SUPPORTS_RUNTIME_PM,
.dr_mode = USB_DR_MODE_HOST,
.txfifothresh = 10,
};
static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
- CI_HDRC_OVERRIDE_PHY_CONTROL
+ CI_HDRC_OVERRIDE_PHY_CONTROL |
+ CI_HDRC_SUPPORTS_RUNTIME_PM,
.dr_mode = USB_DR_MODE_HOST,
.txfifothresh = 16,
};
static const struct tegra_usb_soc_info tegra_udc_soc_info = {
.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
- CI_HDRC_OVERRIDE_PHY_CONTROL,
+ CI_HDRC_OVERRIDE_PHY_CONTROL |
+ CI_HDRC_SUPPORTS_RUNTIME_PM,
.dr_mode = USB_DR_MODE_UNKNOWN,
};
@@ -323,6 +326,10 @@ static int tegra_usb_probe(struct platform_device *pdev)
usb->data.hub_control = tegra_ehci_hub_control;
usb->data.notify_event = tegra_usb_notify_event;
+ /* Tegra PHY driver currently doesn't support LPM for ULPI */
+ if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI)
+ usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM;
+
usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
pdev->num_resources, &usb->data);
if (IS_ERR(usb->dev)) {
--
2.29.2
^ permalink raw reply related
* [PATCH v1 2/8] usb: phy: tegra: Support waking up from a low power mode
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
Support programming of waking up from a low power mode by implementing the
generic set_wakeup() callback of the USB PHY API.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/usb/phy/phy-tegra-usb.c | 79 ++++++++++++++++++++++++++++---
include/linux/usb/tegra_usb_phy.h | 2 +
2 files changed, 75 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
index cee9c9dbb775..ed5f6611b36a 100644
--- a/drivers/usb/phy/phy-tegra-usb.c
+++ b/drivers/usb/phy/phy-tegra-usb.c
@@ -45,6 +45,7 @@
#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
#define USB_SUSP_CTRL 0x400
+#define USB_WAKE_ON_RESUME_EN BIT(2)
#define USB_WAKE_ON_CNNT_EN_DEV BIT(3)
#define USB_WAKE_ON_DISCON_EN_DEV BIT(4)
#define USB_SUSP_CLR BIT(5)
@@ -56,6 +57,9 @@
#define USB_SUSP_SET BIT(14)
#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
+#define USB_PHY_VBUS_WAKEUP_ID 0x408
+#define VBUS_WAKEUP_WAKEUP_EN BIT(30)
+
#define USB1_LEGACY_CTRL 0x410
#define USB1_NO_LEGACY_MODE BIT(0)
#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
@@ -334,6 +338,11 @@ static int utmip_pad_power_on(struct tegra_usb_phy *phy)
writel_relaxed(val, base + UTMIP_BIAS_CFG0);
}
+ if (phy->pad_wakeup) {
+ phy->pad_wakeup = false;
+ utmip_pad_count--;
+ }
+
spin_unlock(&utmip_pad_lock);
clk_disable_unprepare(phy->pad_clk);
@@ -359,6 +368,17 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
goto ulock;
}
+ /*
+ * In accordance to TRM, OTG and Bias pad circuits could be turned off
+ * to save power if wake is enabled, but the VBUS-change detection
+ * method is board-specific and these circuits may need to be enabled
+ * to generate wakeup event, hence we will just keep them both enabled.
+ */
+ if (phy->wakeup_enabled) {
+ phy->pad_wakeup = true;
+ utmip_pad_count++;
+ }
+
if (--utmip_pad_count == 0) {
val = readl_relaxed(base + UTMIP_BIAS_CFG0);
val |= UTMIP_OTGPD | UTMIP_BIASPD;
@@ -503,11 +523,19 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
writel_relaxed(val, base + UTMIP_PLL_CFG1);
}
+ val = readl_relaxed(base + USB_SUSP_CTRL);
+ val &= ~USB_WAKE_ON_RESUME_EN;
+ writel_relaxed(val, base + USB_SUSP_CTRL);
+
if (phy->mode == USB_DR_MODE_PERIPHERAL) {
val = readl_relaxed(base + USB_SUSP_CTRL);
val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
writel_relaxed(val, base + USB_SUSP_CTRL);
+ val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
+ val &= ~VBUS_WAKEUP_WAKEUP_EN;
+ writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
+
val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
val &= ~UTMIP_PD_CHRG;
writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
@@ -605,31 +633,51 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy)
utmi_phy_clk_disable(phy);
- if (phy->mode == USB_DR_MODE_PERIPHERAL) {
- val = readl_relaxed(base + USB_SUSP_CTRL);
- val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
- val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
- writel_relaxed(val, base + USB_SUSP_CTRL);
- }
+ /* PHY won't resume if reset is asserted */
+ if (phy->wakeup_enabled)
+ goto chrg_cfg0;
val = readl_relaxed(base + USB_SUSP_CTRL);
val |= UTMIP_RESET;
writel_relaxed(val, base + USB_SUSP_CTRL);
+chrg_cfg0:
val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
val |= UTMIP_PD_CHRG;
writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
+ if (phy->wakeup_enabled)
+ goto xcvr_cfg1;
+
val = readl_relaxed(base + UTMIP_XCVR_CFG0);
val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
UTMIP_FORCE_PDZI_POWERDOWN;
writel_relaxed(val, base + UTMIP_XCVR_CFG0);
+xcvr_cfg1:
val = readl_relaxed(base + UTMIP_XCVR_CFG1);
val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
UTMIP_FORCE_PDDR_POWERDOWN;
writel_relaxed(val, base + UTMIP_XCVR_CFG1);
+ if (phy->wakeup_enabled) {
+ val = readl_relaxed(base + USB_SUSP_CTRL);
+ val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
+ val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
+ val |= USB_WAKE_ON_RESUME_EN;
+ writel_relaxed(val, base + USB_SUSP_CTRL);
+
+ /*
+ * Ask VBUS sensor to generate wake event once cable is
+ * connected.
+ */
+ if (phy->mode == USB_DR_MODE_PERIPHERAL) {
+ val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
+ val |= VBUS_WAKEUP_WAKEUP_EN;
+ writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
+ }
+ }
+
return utmip_pad_power_off(phy);
}
@@ -765,6 +813,15 @@ static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
usleep_range(5000, 6000);
clk_disable_unprepare(phy->clk);
+ /*
+ * Wakeup currently unimplemented for ULPI, thus PHY needs to be
+ * force-resumed.
+ */
+ if (WARN_ON_ONCE(phy->wakeup_enabled)) {
+ ulpi_phy_power_on(phy);
+ return -EOPNOTSUPP;
+ }
+
return 0;
}
@@ -827,6 +884,15 @@ static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
phy->freq = NULL;
}
+static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable)
+{
+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
+
+ phy->wakeup_enabled = enable;
+
+ return 0;
+}
+
static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
{
struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
@@ -1198,6 +1264,7 @@ static int tegra_usb_phy_probe(struct platform_device *pdev)
tegra_phy->u_phy.dev = &pdev->dev;
tegra_phy->u_phy.init = tegra_usb_phy_init;
tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
+ tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup;
tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
platform_set_drvdata(pdev, tegra_phy);
diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h
index c29d1b4c9381..fd1c9f6a4e37 100644
--- a/include/linux/usb/tegra_usb_phy.h
+++ b/include/linux/usb/tegra_usb_phy.h
@@ -79,6 +79,8 @@ struct tegra_usb_phy {
bool is_ulpi_phy;
struct gpio_desc *reset_gpio;
struct reset_control *pad_rst;
+ bool wakeup_enabled;
+ bool pad_wakeup;
bool powered_on;
};
--
2.29.2
^ permalink raw reply related
* [PATCH v1 1/8] usb: phy: tegra: Add delay after power up
From: Dmitry Osipenko @ 2020-12-15 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter Chen, Greg Kroah-Hartman,
Alan Stern, Felipe Balbi, Matt Merhar, Nicolas Chauvet,
Peter Geis
Cc: linux-tegra, linux-usb, linux-kernel
In-Reply-To: <20201215202113.30394-1-digetx@gmail.com>
The PHY hardware needs the delay of 2ms after power up, otherwise initial
interrupt may be lost if USB controller is accessed before PHY is settled
down. Previously this issue was masked by implicit delays, but now it pops
up after squashing the older ehci-tegra driver into the ChipIdea driver.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/usb/phy/phy-tegra-usb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
index 03a333797382..cee9c9dbb775 100644
--- a/drivers/usb/phy/phy-tegra-usb.c
+++ b/drivers/usb/phy/phy-tegra-usb.c
@@ -784,6 +784,9 @@ static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
phy->powered_on = true;
+ /* let PHY to settle down */
+ usleep_range(2000, 2500);
+
return 0;
}
--
2.29.2
^ permalink raw reply related
* [PATCH] xhci: fix U1/U2 handling for hardware with XHCI_INTEL_HOST quirk set
From: Michael Grzeschik @ 2020-12-15 19:31 UTC (permalink / raw)
To: linux-usb; +Cc: gregkh, mathias.nyman
The commit 0472bf06c6fd ("xhci: Prevent U1/U2 link pm states if exit
latency is too long") was constraining the xhci code not to allow U1/U2
sleep states if the latency to wake up from the U-states reached the
service interval of an periodic endpoint. This fix was not taking into
account that in case the quirk XHCI_INTEL_HOST is set, the wakeup time
will be calculated and configured differently.
It checks for u1_params.mel/u2_params.mel as a limit. But the code could
decide to write another MEL into the hardware. This leads to broken
cases where not enough bandwidth is available for other devices:
usb 1-2: can't set config #1, error -28
This patch is fixing that case by checking for timeout_ns after the
wakeup time was calculated depending on the quirks.
Fixes: 0472bf06c6fd ("xhci: Prevent U1/U2 link pm states if exit latency is too long")
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/usb/host/xhci.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index f4cedcaee14b3..0385ef9cb628b 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -4640,19 +4640,19 @@ static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
{
unsigned long long timeout_ns;
+ if (xhci->quirks & XHCI_INTEL_HOST)
+ timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
+ else
+ timeout_ns = udev->u1_params.sel;
+
/* Prevent U1 if service interval is shorter than U1 exit latency */
if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
- if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
+ if (xhci_service_interval_to_ns(desc) <= timeout_ns) {
dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
return USB3_LPM_DISABLED;
}
}
- if (xhci->quirks & XHCI_INTEL_HOST)
- timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
- else
- timeout_ns = udev->u1_params.sel;
-
/* The U1 timeout is encoded in 1us intervals.
* Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
*/
@@ -4704,19 +4704,19 @@ static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
{
unsigned long long timeout_ns;
+ if (xhci->quirks & XHCI_INTEL_HOST)
+ timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
+ else
+ timeout_ns = udev->u2_params.sel;
+
/* Prevent U2 if service interval is shorter than U2 exit latency */
if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
- if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
+ if (xhci_service_interval_to_ns(desc) <= timeout_ns) {
dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
return USB3_LPM_DISABLED;
}
}
- if (xhci->quirks & XHCI_INTEL_HOST)
- timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
- else
- timeout_ns = udev->u2_params.sel;
-
/* The U2 timeout is encoded in 256us intervals */
timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
/* If the necessary timeout value is bigger than what we can set in the
--
2.29.2
^ permalink raw reply related
* Re: [PATCH v6] dt-bindings: usb: Add new compatible string for AM64 SoC
From: Rob Herring @ 2020-12-15 18:18 UTC (permalink / raw)
To: Aswath Govindraju
Cc: Greg Kroah-Hartman, Sekhar Nori, Vignesh Raghavendra, Rob Herring,
Roger Quadros, devicetree, linux-kernel, linux-usb
In-Reply-To: <20201215042549.7956-1-a-govindraju@ti.com>
On Tue, 15 Dec 2020 09:55:49 +0530, Aswath Govindraju wrote:
> Add compatible string in j721e-usb binding file as the same USB subsystem
> is present in AM64.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> ---
>
> Changes since v5:
> - Added const as the type for objects in items.
>
> Changes since v4:
> - used oneOf instead of enum, as the schema has to convey that the strings
> ti,j721e-usb and ti,am64-usb can be used combined or seperately in the
> DT nodes.
>
> Changes since v3:
> - used enum instead of anyOf.
>
> Changes since v2:
> - added changes done over the versions.
>
> Changes since v1:
> - replaced the '\t' at the beginning of the lines with spaces as it was
> causing the dt_binding_check to fail.
>
> Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
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