* Re: [PATCH v1] wifi: ath9k: Fix typo
From: Jeff Johnson @ 2026-02-26 21:29 UTC (permalink / raw)
To: linux-wireless, Alejandro Colomar
Cc: Rajkumar Manoharan, John W. Linville,
Toke Høiland-Jørgensen
In-Reply-To: <6ab107cf786f9d05dc4d84ea4e2d1b219ce108c0.1766355822.git.alx@kernel.org>
On Sun, 21 Dec 2025 23:25:54 +0100, Alejandro Colomar wrote:
> This only worked by chance, because all callers of this macro used the
> same identifiers that were expected by the macro.
>
> $ grep -rn ath_for_each_chanctx
> drivers/net/wireless/ath/ath9k/main.c:1576: ath_for_each_chanctx(sc, ctx)
> drivers/net/wireless/ath/ath9k/main.c:2554: ath_for_each_chanctx(sc, ctx) {
> drivers/net/wireless/ath/ath9k/channel.c:165: ath_for_each_chanctx(sc, ctx) {
> drivers/net/wireless/ath/ath9k/channel.c:291: ath_for_each_chanctx(sc, ctx) {
> drivers/net/wireless/ath/ath9k/channel.c:861: ath_for_each_chanctx(sc, ctx) {
> drivers/net/wireless/ath/ath9k/debug.c:717: ath_for_each_chanctx(sc, ctx) {
> drivers/net/wireless/ath/ath9k/ath9k.h:446:#define ath_for_each_chanctx(_sc, _ctx) \
>
> [...]
Applied, thanks!
[1/1] wifi: ath9k: Fix typo
commit: a8911fbeff8bee4fe3376c5044b64fbf3cceb78e
Best regards,
--
Jeff Johnson <jeff.johnson@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH ath-next] wifi: ath12k: fix indentation in ath12k_qmi_aux_uc_load()
From: Jeff Johnson @ 2026-02-26 21:29 UTC (permalink / raw)
To: Jeff Johnson, Baochen Qiang
Cc: linux-wireless, ath12k, linux-kernel, kernel test robot
In-Reply-To: <20260209-ath12k-fix-indention-v1-1-6b87ae99745e@oss.qualcomm.com>
On Mon, 09 Feb 2026 10:52:19 +0800, Baochen Qiang wrote:
> Smatch complains:
>
> drivers/net/wireless/ath/ath12k/qmi.c:3342 ath12k_qmi_aux_uc_load() warn: inconsistent indenting
>
> Fix it.
>
> Compile tested only.
>
> [...]
Applied, thanks!
[1/1] wifi: ath12k: fix indentation in ath12k_qmi_aux_uc_load()
commit: 0ef4738f0d38f103e525ffb12c112a935c2cf011
Best regards,
--
Jeff Johnson <jeff.johnson@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH ath-next v4] wifi: ath12k: add basic hwmon temperature reporting
From: Jeff Johnson @ 2026-02-26 21:29 UTC (permalink / raw)
To: ath12k, Maharaja Kennadyrajan; +Cc: linux-wireless, Aishwarya R
In-Reply-To: <20260223132622.43464-1-maharaja.kennadyrajan@oss.qualcomm.com>
On Mon, 23 Feb 2026 18:56:22 +0530, Maharaja Kennadyrajan wrote:
> Add initial thermal support by wiring up a per-radio (pdev) hwmon temperature
> sensor backed by the existing WMI pdev temperature command and event.
> When userspace reads the sysfs file temp1_input, the driver sends
> WMI_PDEV_GET_TEMPERATURE_CMDID (tag WMI_TAG_PDEV_GET_TEMPERATURE_CMD) and waits
> for the corresponding WMI_PDEV_TEMPERATURE_EVENTID
> (tag WMI_TAG_PDEV_TEMPERATURE_EVENT) to get the temperature and pdev_id.
>
> [...]
Applied, thanks!
[1/1] wifi: ath12k: add basic hwmon temperature reporting
commit: 151322bccdbdb132f5a73cc8ad5d3ab89b90ed52
Best regards,
--
Jeff Johnson <jeff.johnson@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v3] wifi: ath11k: fix memory leaks in beacon template setup
From: Jeff Johnson @ 2026-02-26 21:29 UTC (permalink / raw)
To: Zilin Guan
Cc: ath11k, baochen.qiang, jianhao.xu, jjohnson, linux-kernel,
linux-wireless
In-Reply-To: <20260130084451.110768-1-zilin@seu.edu.cn>
On Fri, 30 Jan 2026 08:44:51 +0000, Zilin Guan wrote:
> The functions ath11k_mac_setup_bcn_tmpl_ema() and
> ath11k_mac_setup_bcn_tmpl_mbssid() allocate memory for beacon templates
> but fail to free it when parameter setup returns an error.
>
> Since beacon templates must be released during normal execution, they
> must also be released in the error handling paths to prevent memory
> leaks.
>
> [...]
Applied, thanks!
[1/1] wifi: ath11k: fix memory leaks in beacon template setup
commit: ff49eba595df500e4ddccc593088c8a4ab5f2c27
Best regards,
--
Jeff Johnson <jeff.johnson@oss.qualcomm.com>
^ permalink raw reply
* [PATCH] wifi: mt76: mt7915: add debug query from WA firmware
From: David Bauer @ 2026-02-26 21:45 UTC (permalink / raw)
To: Felix Fietkau, Lorenzo Bianconi, Ryder Lee, Shayne Chen,
Sean Wang, Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-wireless, linux-kernel, linux-arm-kernel, linux-mediatek
Add a new file to the mt76 debugfs to allow querying internal state
information from the WA firmware.
This allows to extract more information from the internal queue
structures and configured limits.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
.../wireless/mediatek/mt76/mt7915/debugfs.c | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
index 26ed3745af43e..018b1c70b524b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
@@ -603,6 +603,86 @@ mt7915_fw_debug_wa_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7915_fw_debug_wa_get,
mt7915_fw_debug_wa_set, "%lld\n");
+struct {
+ u8 idx;
+ u8 query_cmd;
+ char *description;
+} mt7915_fw_wa_debug_query[] = {
+ { 0, 0x16, "MSDU drop info" },
+ { 1, 0x17, "AC queue tail drop" },
+ { 2, 0x19, "TX Free info" },
+ { 3, 0x20, "BSS Table" },
+ { 4, 0x21, "STA records" },
+};
+
+static ssize_t
+mt7915_fw_query_wa_set(struct file *file, const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct mt7915_phy *phy = file->private_data;
+ struct mt7915_dev *dev = phy->dev;
+ char buf[16];
+ u16 val;
+
+ if (count >= sizeof(buf))
+ return -EINVAL;
+
+ if (copy_from_user(buf, user_buf, count))
+ return -EFAULT;
+
+ if (count && buf[count - 1] == '\n')
+ buf[count - 1] = '\0';
+ else
+ buf[count] = '\0';
+
+ if (kstrtou16(buf, 0, &val))
+ return -EINVAL;
+
+ for (int i = 0; i < ARRAY_SIZE(mt7915_fw_wa_debug_query); i++) {
+ if (val != mt7915_fw_wa_debug_query[i].idx)
+ continue;
+
+ mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
+ mt7915_fw_wa_debug_query[i].query_cmd,
+ 0, 0);
+ return count;
+ }
+
+ return -EINVAL;
+}
+
+static ssize_t
+mt7915_fw_query_wa_get(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ static const size_t bufsz = 1024;
+ ssize_t ret;
+ char *buff;
+ int desc = 0;
+ int i;
+
+ buff = kmalloc(bufsz, GFP_KERNEL);
+ if (!buff)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(mt7915_fw_wa_debug_query); i++) {
+ desc += scnprintf(buff + desc, bufsz - desc,
+ "%d: %s\n", mt7915_fw_wa_debug_query[i].idx,
+ mt7915_fw_wa_debug_query[i].description);
+ }
+
+ ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc);
+ kfree(buff);
+ return ret;
+}
+
+static const struct file_operations fw_query_wa_fops = {
+ .write = mt7915_fw_query_wa_set,
+ .read = mt7915_fw_query_wa_get,
+ .open = simple_open,
+ .llseek = default_llseek,
+};
+
static struct dentry *
create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode,
struct rchan_buf *buf, int *is_global)
@@ -1310,6 +1390,7 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
&mt7915_sys_recovery_ops);
debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm);
debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa);
+ debugfs_create_file("fw_query_wa", 0600, dir, dev, &fw_query_wa_fops);
debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin);
debugfs_create_file("fw_util_wm", 0400, dir, dev,
&mt7915_fw_util_wm_fops);
--
2.51.0
^ permalink raw reply related
* Re: [PATCH ath-next] wifi: ath5k: ahb: use devm for ioremap
From: Rosen Penev @ 2026-02-26 23:58 UTC (permalink / raw)
To: Jiri Slaby; +Cc: linux-wireless, Nick Kossifidis, Luis Chamberlain, open list
In-Reply-To: <cf50211c-4f0c-45e3-860d-220b49f4cc11@kernel.org>
On Tue, Feb 24, 2026 at 10:23 AM Jiri Slaby <jirislaby@kernel.org> wrote:
>
> On 23. 02. 26, 4:08, Rosen Penev wrote:
> > Simplifies the code by quite a bit in probe.
> >
> > Also allows removing a goto and returning directly.
>
> Looks good except:
>
> > --- a/drivers/net/wireless/ath/ath5k/ahb.c
> > +++ b/drivers/net/wireless/ath/ath5k/ahb.c
> ...
> > @@ -95,35 +94,21 @@ static int ath_ahb_probe(struct platform_device *pdev)
> >
> > if (!dev_get_platdata(&pdev->dev)) {
> > dev_err(&pdev->dev, "no platform data specified\n");
> > - ret = -EINVAL;
> > - goto err_out;
> > + return -EINVAL;
> > }
> >
> > - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > - if (res == NULL) {
> > - dev_err(&pdev->dev, "no memory resource found\n");
> > - ret = -ENXIO;
> > - goto err_out;
> > - }
> > -
> > - mem = ioremap(res->start, resource_size(res));
> > - if (mem == NULL) {
> > - dev_err(&pdev->dev, "ioremap failed\n");
> > - ret = -ENOMEM;
> > - goto err_out;
> > - }
> > + mem = devm_platform_ioremap_resources(pdev, 0);
>
> Is this a typo or devm_platform_ioremap_resources() is new?
typo. Looks like COMPILE_TEST is needed.
>
> --
> js
> suse labs
^ permalink raw reply
* [syzbot] [wireless?] WARNING in ieee80211_set_disassoc (2)
From: syzbot @ 2026-02-27 1:43 UTC (permalink / raw)
To: johannes, linux-kernel, linux-wireless, netdev, syzkaller-bugs
Hello,
syzbot found the following issue on:
HEAD commit: 189f164e573e Convert remaining multi-line kmalloc_obj/flex..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=1750855a580000
kernel config: https://syzkaller.appspot.com/x/.config?x=2208a171312e89b7
dashboard link: https://syzkaller.appspot.com/bug?extid=4b737df95e84787fec21
compiler: Debian clang version 21.1.8 (++20251221033036+2078da43e25a-1~exp1~20251221153213.50), Debian LLD 21.1.8
Unfortunately, I don't have any reproducer for this issue yet.
Downloadable assets:
disk image (non-bootable): https://storage.googleapis.com/syzbot-assets/d900f083ada3/non_bootable_disk-189f164e.raw.xz
vmlinux: https://storage.googleapis.com/syzbot-assets/669b52dbab53/vmlinux-189f164e.xz
kernel image: https://storage.googleapis.com/syzbot-assets/51b76feb584c/bzImage-189f164e.xz
IMPORTANT: if you fix the issue, please add the following tag to the commit:
Reported-by: syzbot+4b737df95e84787fec21@syzkaller.appspotmail.com
mac80211_hwsim: wmediumd released netlink socket, switching to perfect channel medium
mac80211_hwsim: wmediumd released netlink socket, switching to perfect channel medium
mac80211_hwsim: wmediumd released netlink socket, switching to perfect channel medium
wlan1: deauthenticating from 08:02:11:00:00:00 by local choice (Reason: 3=DEAUTH_LEAVING)
------------[ cut here ]------------
!ap_sta
WARNING: net/mac80211/mlme.c:4137 at ieee80211_set_disassoc+0x3c8/0x1a90 net/mac80211/mlme.c:4137, CPU#0: syz.0.0/5315
Modules linked in:
CPU: 0 UID: 0 PID: 5315 Comm: syz.0.0 Not tainted syzkaller #0 PREEMPT(full)
Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.16.3-debian-1.16.3-2 04/01/2014
RIP: 0010:ieee80211_set_disassoc+0x3c8/0x1a90 net/mac80211/mlme.c:4137
Code: c4 8c f6 45 85 ff 0f 84 c9 11 00 00 e8 81 c0 8c f6 eb 2b e8 7a c0 8c f6 48 83 7c 24 48 00 0f 85 38 fe ff ff e8 69 c0 8c f6 90 <0f> 0b 90 e9 aa 10 00 00 e8 5b c0 8c f6 eb 05 e8 54 c0 8c f6 48 8d
RSP: 0018:ffffc9000dd4efa0 EFLAGS: 00010287
RAX: ffffffff8b38dab7 RBX: ffff888038b28dc0 RCX: 0000000000100000
RDX: ffffc9000ec12000 RSI: 000000000001762f RDI: 0000000000017630
RBP: ffffc9000dd4f0b0 R08: 0000000000000001 R09: 0000000000000000
R10: ffffc9000dd4f1e0 R11: fffff52001ba9e3f R12: ffff888038b297f0
R13: dffffc0000000000 R14: 1ffff92001ba9e04 R15: ffffc9000dd4f1e0
FS: 00007f5691c2d6c0(0000) GS:ffff88808ca5b000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00007ffc7ffad0c8 CR3: 0000000035dd8000 CR4: 0000000000352ef0
Call Trace:
<TASK>
ieee80211_mgd_deauth+0x9fa/0xe60 net/mac80211/mlme.c:10198
rdev_deauth net/wireless/rdev-ops.h:509 [inline]
cfg80211_mlme_deauth+0x51b/0x8f0 net/wireless/mlme.c:536
cfg80211_sme_disconnect net/wireless/sme.c:666 [inline]
cfg80211_disconnect+0x3b2/0x7c0 net/wireless/sme.c:1559
cfg80211_netdev_notifier_call+0x1ba/0x1470 net/wireless/core.c:1599
notifier_call_chain+0x1be/0x400 kernel/notifier.c:85
call_netdevice_notifiers_extack net/core/dev.c:2287 [inline]
call_netdevice_notifiers net/core/dev.c:2301 [inline]
__dev_close_many+0x119/0x6d0 net/core/dev.c:1746
netif_close_many+0x225/0x420 net/core/dev.c:1800
netif_close+0x160/0x220 net/core/dev.c:1817
dev_close+0x10a/0x220 net/core/dev_api.c:220
cfg80211_shutdown_all_interfaces+0xc4/0x200 net/wireless/core.c:282
cfg80211_rfkill_set_block+0x2d/0x50 net/wireless/core.c:312
rfkill_set_block+0x1d2/0x440 net/rfkill/core.c:346
rfkill_fop_write+0x461/0x5a0 net/rfkill/core.c:1301
vfs_write+0x29a/0xb90 fs/read_write.c:686
ksys_write+0x150/0x270 fs/read_write.c:740
do_syscall_x64 arch/x86/entry/syscall_64.c:63 [inline]
do_syscall_64+0x14d/0xf80 arch/x86/entry/syscall_64.c:94
entry_SYSCALL_64_after_hwframe+0x77/0x7f
RIP: 0033:0x7f5690d9c629
Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 e8 ff ff ff f7 d8 64 89 01 48
RSP: 002b:00007f5691c2d028 EFLAGS: 00000246 ORIG_RAX: 0000000000000001
RAX: ffffffffffffffda RBX: 00007f5691015fa0 RCX: 00007f5690d9c629
RDX: 0000000000000008 RSI: 0000200000000080 RDI: 0000000000000006
RBP: 00007f5690e32b39 R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
R13: 00007f5691016038 R14: 00007f5691015fa0 R15: 00007fff6e9cd5a8
</TASK>
---
This report is generated by a bot. It may contain errors.
See https://goo.gl/tpsmEJ for more information about syzbot.
syzbot engineers can be reached at syzkaller@googlegroups.com.
syzbot will keep track of this issue. See:
https://goo.gl/tpsmEJ#status for how to communicate with syzbot.
If the report is already addressed, let syzbot know by replying with:
#syz fix: exact-commit-title
If you want to overwrite report's subsystems, reply with:
#syz set subsystems: new-subsystem
(See the list of subsystem names on the web dashboard)
If the report is a duplicate of another one, reply with:
#syz dup: exact-subject-of-another-report
If you want to undo deduplication, reply with:
#syz undup
^ permalink raw reply
* [PATCH ath-next] wifi: ath12k: Enable monitor mode support on IPQ5332
From: Aaradhana Sahu @ 2026-02-27 3:33 UTC (permalink / raw)
To: ath12k; +Cc: linux-wireless, Aaradhana Sahu
Currently, rxdma1_enable and supports_monitor are set to false in
IPQ5332 hardware parameters, which skips monitor ring configuration
and removes NL80211_IFTYPE_MONITOR from the supported interface modes.
Set rxdma1_enable and supports_monitor to true so that monitor rings are
configured and monitor mode is enabled on IPQ5332.
Tested-on: IPQ5332 hw1.0 AHB WLAN.WBE.1.7-00587-QCAHKSWPL_SILICONZ-1
Signed-off-by: Aaradhana Sahu <aaradhana.sahu@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/wifi7/hw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hw.c b/drivers/net/wireless/ath/ath12k/wifi7/hw.c
index df045ddf42da..27acdfc35459 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hw.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hw.c
@@ -617,7 +617,7 @@ static const struct ath12k_hw_params ath12k_wifi7_hw_params[] = {
ath12k_wifi7_target_service_to_ce_map_wlan_ipq5332,
.svc_to_ce_map_len = 18,
- .rxdma1_enable = false,
+ .rxdma1_enable = true,
.num_rxdma_per_pdev = 1,
.num_rxdma_dst_ring = 0,
.rx_mac_buf_ring = false,
@@ -626,7 +626,7 @@ static const struct ath12k_hw_params ath12k_wifi7_hw_params[] = {
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_AP) |
BIT(NL80211_IFTYPE_MESH_POINT),
- .supports_monitor = false,
+ .supports_monitor = true,
.idle_ps = false,
.download_calib = true,
base-commit: 20ad0d58517073b3b683ff786c65dd3142321707
--
2.34.1
^ permalink raw reply related
* [PATCH wireless-next 00/35] wifi: mm81x: add mm81x driver
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes
Cc: arien.judge, dan.callaghan, ayman.grais, linux-wireless,
Lachlan Hodges
This series adds the first Wi-Fi HaLow driver to support the Morse
Micro mm81x chip family via USB and SDIO.
S1G support in the kernel is only new, and as a result this driver has
been scoped to be simple and only support station and AP interface.
The Wi-Fi specific features only cover the minimum required for basic
use such as powersave, aggregation, rate control and so on. The driver
will be extended into the future as S1G support for operations such as
ACS, channel switching and so on are added into the wireless stack.
The driver contains a single checkpatch CHECK for a static rate array
using the same ignore list as the wireless checkpatch NIPA bot with
the exception of OPEN_ENDED_LINE which has been added.
The driver has been build tested on a long list of architectures and
compilers via Intels LKP.
The driver currently supports IEEE80211-2024 US channels only, with
AU 2020 also available. In order for this to be expanded additional
non-trivial kernel work is required which will begin once the
driver is upstream.
Some items of importance:
* Our firmware cannot be loaded with the 00 regdom. Due to the
disparate nature of S1G channels, it's not feasible to store the
entire regdom on the chip in EEPROM or similar. This means the chip
will fail to boot when the world regdom is selected. The nature of
the reg notifier means there is no clean way to propagate this error
to usermode besides through kernel logs (obviously interface
addition will also fail).
* When reacting to dynamic regulatory changes from usermode, we must
perform a full chip restart. Unfortunately this requires a blocking
reset in the regulatory notifier to prevent subsequent command
failures. Feedback on this would be appreciated, but we note that
this is due to the limitation of our current chip/firmware as above.
* There is currently no upstream support for S1G within
hostpad / wpa_supplicant / iwd. This makes testing of the driver
challenging. We intend to post upstream patches for these utilities
shortly following the submission of this driver.
* We were going to push the driver to staging, but we believe the driver
is in a good enough state for the regular tree (pending review of
course :-)). However, while it is not the normal process, staging may
be something to consider so that the upstream ecosystem can mature over
~6 months.
The firmware will be posted in the next version.
The driver has had many authors who are listed below in
alphabetical order:
Signed-off-by: Andrew Pope andrew.pope@morsemicro.com
Signed-off-by: Arien Judge arien.judge@morsemicro.com
Signed-off-by: Ayman Grais ayman.grais@morsemicro.com
Signed-off-by: Bassem Dawood bassem@morsemicro.com
Signed-off-by: Chetan Mistry chetan.mistry@morsemicro.com
Signed-off-by: Dan Callaghan dan.callaghan@morsemicro.com
Signed-off-by: James Herbert james.herbert@morsemicro.com
Signed-off-by: Sahand Maleki sahand.maleki@morsemicro.com
Signed-off-by: Simon Wadsworth simon@morsemicro.com
Signed-off-by: Lachlan Hodges lachlan.hodges@morsemicro.com
Lachlan Hodges (35):
wifi: mm81x: add bus.h
wifi: mm81x: add command.c
wifi: mm81x: add command_defs.h
wifi: mm81x: add command.h
wifi: mm81x: add core.c
wifi: mm81x: add core.h
wifi: mm81x: add debug.c
wifi: mm81x: add debug.h
wifi: mm81x: add fw.c
wifi: mm81x: add fw.h
wifi: mm81x: add hif.h
wifi: mm81x: add hw.c
wifi: mm81x: add hw.h
wifi: mm81x: add mac.c
wifi: mm81x: add mac.h
wifi: mm81x: add mmrc.c
wifi: mm81x: add mmrc.h
wifi: mm81x: add ps.c
wifi: mm81x: add ps.h
wifi: mm81x: add rate_code.h
wifi: mm81x: add rc.c
wifi: mm81x: add rc.h
wifi: mm81x: add sdio.c
wifi: mm81x: add skbq.c
wifi: mm81x: add skbq.h
wifi: mm81x: add usb.c
wifi: mm81x: add yaps.c
wifi: mm81x: add yaps.h
wifi: mm81x: add yaps_hw.c
wifi: mm81x: add yaps_hw.h
dt-bindings: vendor-prefixes: add Morse Micro
dt-bindings: net: wireless: morsemicro: add mm81x family
mmc: sdio: add Morse Micro vendor ids
wifi: mm81x: add Kconfig and Makefile
wifi: mm81x: add MAINTAINERS entry
.../net/wireless/morsemicro,mm81x.yaml | 74 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 9 +
drivers/net/wireless/Kconfig | 1 +
drivers/net/wireless/Makefile | 1 +
drivers/net/wireless/morsemicro/Kconfig | 15 +
drivers/net/wireless/morsemicro/Makefile | 2 +
drivers/net/wireless/morsemicro/mm81x/Kconfig | 34 +
.../net/wireless/morsemicro/mm81x/Makefile | 19 +
drivers/net/wireless/morsemicro/mm81x/bus.h | 90 +
.../net/wireless/morsemicro/mm81x/command.c | 619 ++++
.../net/wireless/morsemicro/mm81x/command.h | 84 +
.../wireless/morsemicro/mm81x/command_defs.h | 1668 +++++++++++
drivers/net/wireless/morsemicro/mm81x/core.c | 157 +
drivers/net/wireless/morsemicro/mm81x/core.h | 499 ++++
drivers/net/wireless/morsemicro/mm81x/debug.c | 87 +
drivers/net/wireless/morsemicro/mm81x/debug.h | 58 +
drivers/net/wireless/morsemicro/mm81x/fw.c | 743 +++++
drivers/net/wireless/morsemicro/mm81x/fw.h | 107 +
drivers/net/wireless/morsemicro/mm81x/hif.h | 116 +
drivers/net/wireless/morsemicro/mm81x/hw.c | 372 +++
drivers/net/wireless/morsemicro/mm81x/hw.h | 175 ++
drivers/net/wireless/morsemicro/mm81x/mac.c | 2642 +++++++++++++++++
drivers/net/wireless/morsemicro/mm81x/mac.h | 69 +
drivers/net/wireless/morsemicro/mm81x/mmrc.c | 1353 +++++++++
drivers/net/wireless/morsemicro/mm81x/mmrc.h | 198 ++
drivers/net/wireless/morsemicro/mm81x/ps.c | 239 ++
drivers/net/wireless/morsemicro/mm81x/ps.h | 22 +
.../net/wireless/morsemicro/mm81x/rate_code.h | 177 ++
drivers/net/wireless/morsemicro/mm81x/rc.c | 559 ++++
drivers/net/wireless/morsemicro/mm81x/rc.h | 62 +
drivers/net/wireless/morsemicro/mm81x/sdio.c | 803 +++++
drivers/net/wireless/morsemicro/mm81x/skbq.c | 1056 +++++++
drivers/net/wireless/morsemicro/mm81x/skbq.h | 218 ++
drivers/net/wireless/morsemicro/mm81x/usb.c | 971 ++++++
drivers/net/wireless/morsemicro/mm81x/yaps.c | 704 +++++
drivers/net/wireless/morsemicro/mm81x/yaps.h | 77 +
.../net/wireless/morsemicro/mm81x/yaps_hw.c | 683 +++++
.../net/wireless/morsemicro/mm81x/yaps_hw.h | 52 +
include/linux/mmc/sdio_ids.h | 4 +
40 files changed, 14821 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/wireless/morsemicro,mm81x.yaml
create mode 100644 drivers/net/wireless/morsemicro/Kconfig
create mode 100644 drivers/net/wireless/morsemicro/Makefile
create mode 100644 drivers/net/wireless/morsemicro/mm81x/Kconfig
create mode 100644 drivers/net/wireless/morsemicro/mm81x/Makefile
create mode 100644 drivers/net/wireless/morsemicro/mm81x/bus.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/command.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/command.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/command_defs.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/core.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/core.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/debug.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/debug.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/fw.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/fw.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/hif.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/hw.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/hw.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/mac.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/mac.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/mmrc.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/mmrc.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/ps.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/ps.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/rate_code.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/rc.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/rc.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/sdio.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/skbq.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/skbq.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/usb.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/yaps.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/yaps.h
create mode 100644 drivers/net/wireless/morsemicro/mm81x/yaps_hw.c
create mode 100644 drivers/net/wireless/morsemicro/mm81x/yaps_hw.h
--
2.43.0
^ permalink raw reply
* [PATCH ath-next] wifi: ath12k: Set up MLO after SSR
From: Roopni Devanathan @ 2026-02-27 4:11 UTC (permalink / raw)
To: ath12k; +Cc: linux-wireless, Ramya Gnanasekar, Roopni Devanathan
From: Ramya Gnanasekar <ramya.gnanasekar@oss.qualcomm.com>
During recovery of an MLO setup from a core reset,
ATH12K_GROUP_FLAG_REGISTERED is set because ath12k_mac_unregister is not
called during core reset. So, when an MLO setup is recovering from a core
reset, ath12k_core_mlo_setup() is skipped. Hence, the firmware will not
have information about partner links. This makes MLO association fail
after recovery.
To resolve this, call ath12k_core_mlo_setup() during recovery, to set up
MLO. Also, if MLO setup fails during recovery, call
ath12k_mac_unregister() and ath12k_mac_destroy() to unregister mac and
then tear down the mac structures.
Also, initiate MLO teardown in the hardware group stop sequence to align
with the hardware group start sequence.
Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01181-QCAHKSWPL_SILICONZ-1
Signed-off-by: Ramya Gnanasekar <ramya.gnanasekar@oss.qualcomm.com>
Signed-off-by: Roopni Devanathan <roopni.devanathan@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/core.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c
index 9dca1a0af73e..218c0a0c9699 100644
--- a/drivers/net/wireless/ath/ath12k/core.c
+++ b/drivers/net/wireless/ath/ath12k/core.c
@@ -1017,6 +1017,8 @@ static void ath12k_core_hw_group_stop(struct ath12k_hw_group *ag)
ath12k_mac_unregister(ag);
+ ath12k_mac_mlo_teardown(ag);
+
for (i = ag->num_devices - 1; i >= 0; i--) {
ab = ag->ab[i];
if (!ab)
@@ -1134,8 +1136,14 @@ static int ath12k_core_hw_group_start(struct ath12k_hw_group *ag)
lockdep_assert_held(&ag->mutex);
- if (test_bit(ATH12K_GROUP_FLAG_REGISTERED, &ag->flags))
+ if (test_bit(ATH12K_GROUP_FLAG_REGISTERED, &ag->flags)) {
+ ret = ath12k_core_mlo_setup(ag);
+ if (WARN_ON(ret)) {
+ ath12k_mac_unregister(ag);
+ goto err_mac_destroy;
+ }
goto core_pdev_create;
+ }
ret = ath12k_mac_allocate(ag);
if (WARN_ON(ret))
base-commit: 20ad0d58517073b3b683ff786c65dd3142321707
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 01/35] wifi: mm81x: add bus.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/bus.h | 90 +++++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/bus.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/bus.h b/drivers/net/wireless/morsemicro/mm81x/bus.h
new file mode 100644
index 000000000000..3c0b8bb1d8c3
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/bus.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_BUS_H_
+#define _MM81X_BUS_H_
+
+#include <linux/skbuff.h>
+#include "core.h"
+
+enum mm81x_bus_type {
+ MM81X_BUS_TYPE_USB,
+ MM81X_BUS_TYPE_SDIO,
+};
+
+struct mm81x_bus_ops {
+ int (*dm_read)(struct mm81x *mm, u32 addr, u8 *data, int len);
+ int (*dm_write)(struct mm81x *mm, u32 addr, const u8 *data, int len);
+ int (*reg32_read)(struct mm81x *mm, u32 addr, u32 *data);
+ int (*reg32_write)(struct mm81x *mm, u32 addr, u32 data);
+ void (*set_bus_enable)(struct mm81x *mm, bool enable);
+ void (*config_burst_mode)(struct mm81x *mm, bool enable_burst);
+ void (*claim)(struct mm81x *mm);
+ void (*set_irq)(struct mm81x *mm, bool enable);
+ void (*release)(struct mm81x *mm);
+ unsigned int bulk_alignment;
+};
+
+/*
+ * Default TX alignment for buses which don't care. mac80211 will give us
+ * SKBs aligned to the 2 byte boundary, so 2 is effectively a noop.
+ */
+#define MM81X_BUS_DEFAULT_BULK_ALIGNMENT (2)
+
+/* mm81x_dm_read - len must be rounded up to the nearest 4-byte boundary */
+static inline int mm81x_dm_read(struct mm81x *mm, u32 addr, u8 *data, int len)
+{
+ return mm->bus_ops->dm_read(mm, addr, data, len);
+}
+
+static inline int mm81x_dm_write(struct mm81x *mm, u32 addr, const u8 *data,
+ int len)
+{
+ return mm->bus_ops->dm_write(mm, addr, data, len);
+}
+
+static inline int mm81x_reg32_read(struct mm81x *mm, u32 addr, u32 *data)
+{
+ return mm->bus_ops->reg32_read(mm, addr, data);
+}
+
+static inline int mm81x_reg32_write(struct mm81x *mm, u32 addr, u32 data)
+{
+ return mm->bus_ops->reg32_write(mm, addr, data);
+}
+
+static inline void mm81x_set_bus_enable(struct mm81x *mm, bool enable)
+{
+ mm->bus_ops->set_bus_enable(mm, enable);
+}
+
+static inline void mm81x_bus_config_burst_mode(struct mm81x *mm,
+ bool enable_burst)
+{
+ if (mm->bus_ops->config_burst_mode)
+ mm->bus_ops->config_burst_mode(mm, enable_burst);
+}
+
+static inline void mm81x_claim_bus(struct mm81x *mm)
+{
+ mm->bus_ops->claim(mm);
+}
+
+static inline void mm81x_bus_set_irq(struct mm81x *mm, bool enable)
+{
+ mm->bus_ops->set_irq(mm, enable);
+}
+
+static inline void mm81x_release_bus(struct mm81x *mm)
+{
+ mm->bus_ops->release(mm);
+}
+
+static inline unsigned int mm81x_bus_get_alignment(struct mm81x *mm)
+{
+ return mm->bus_ops->bulk_alignment;
+}
+
+#endif /* !_MM81X_BUS_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 02/35] wifi: mm81x: add command.c
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
.../net/wireless/morsemicro/mm81x/command.c | 619 ++++++++++++++++++
1 file changed, 619 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/command.c
diff --git a/drivers/net/wireless/morsemicro/mm81x/command.c b/drivers/net/wireless/morsemicro/mm81x/command.c
new file mode 100644
index 000000000000..d756bcf5a318
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/command.c
@@ -0,0 +1,619 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#include <linux/types.h>
+#include <linux/atomic.h>
+#include <linux/slab.h>
+#include <linux/atomic.h>
+#include <linux/workqueue.h>
+
+#include "debug.h"
+#include "command.h"
+#include "mac.h"
+#include "ps.h"
+#include "hif.h"
+
+#define MM_MAX_COMMAND_RETRY 2
+#define HOST_CMD_DEFAULT_TIMEOUT_MS 600
+#define HOST_CMD_POWERSAVE_TIMEOUT_MS 2000
+
+struct host_cmd_resp_cb {
+ int ret;
+ u32 length;
+ struct host_cmd_resp *dest_resp;
+};
+
+static void mm81x_cmd_init(struct mm81x *mm, struct host_cmd_header *hdr,
+ enum host_cmd_id cmd, u16 vif_id, u16 len)
+{
+ if (len < sizeof(*hdr)) {
+ mm81x_err(mm, "Invalid cmd len %d\n", len);
+ return;
+ }
+
+ hdr->message_id = cpu_to_le16(cmd);
+ hdr->len = cpu_to_le16(len - sizeof(*hdr));
+ hdr->vif_id = cpu_to_le16(vif_id);
+}
+
+static int mm81x_cmd_tx(struct mm81x *mm, struct host_cmd_resp *resp,
+ struct host_cmd_req *req, u32 length, u32 timeout)
+{
+ int cmd_len;
+ int ret = 0;
+ u16 host_id;
+ int retry = 0;
+ unsigned long wait_ret = 0;
+ struct sk_buff *skb;
+ struct mm81x_skbq *cmd_q = mm81x_hif_get_tx_cmd_queue(mm);
+ struct host_cmd_resp_cb *resp_cb;
+ DECLARE_COMPLETION_ONSTACK(cmd_comp);
+
+ BUILD_BUG_ON(sizeof(struct host_cmd_resp_cb) >
+ IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
+
+ if (!cmd_q)
+ /* No control pageset, not supported by FW */
+ return -ENODEV;
+
+ cmd_len = sizeof(*req) + le16_to_cpu(req->hdr.len);
+ req->hdr.flags = cpu_to_le16(HOST_CMD_TYPE_REQ);
+
+ mutex_lock(&mm->cmd_wait);
+ mm->cmd_seq++;
+ if (mm->cmd_seq > HOST_CMD_HOST_ID_SEQ_MAX)
+ mm->cmd_seq = 1;
+ host_id = mm->cmd_seq << HOST_CMD_HOST_ID_SEQ_SHIFT;
+
+ mm81x_ps_disable(mm);
+
+ do {
+ req->hdr.host_id = cpu_to_le16(host_id | retry);
+
+ skb = mm81x_skbq_alloc_skb(cmd_q, cmd_len);
+ if (!skb) {
+ ret = -ENOMEM;
+ break;
+ }
+
+ memcpy(skb->data, req, cmd_len);
+ resp_cb = (struct host_cmd_resp_cb *)IEEE80211_SKB_CB(skb)
+ ->driver_data;
+ resp_cb->length = length;
+ resp_cb->dest_resp = resp;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "CMD 0x%04x:%04x",
+ le16_to_cpu(req->hdr.message_id),
+ le16_to_cpu(req->hdr.host_id));
+
+ mutex_lock(&mm->cmd_lock);
+ mm->cmd_comp = &cmd_comp;
+ if (retry > 0)
+ reinit_completion(&cmd_comp);
+ timeout = timeout ? timeout : HOST_CMD_DEFAULT_TIMEOUT_MS;
+ ret = mm81x_skbq_skb_tx(cmd_q, &skb, NULL,
+ MM81X_SKB_CHAN_COMMAND);
+ mutex_unlock(&mm->cmd_lock);
+
+ if (ret) {
+ mm81x_err(mm, "mm81x_skbq_tx fail: %d", ret);
+ break;
+ }
+
+ wait_ret = wait_for_completion_timeout(
+ &cmd_comp, msecs_to_jiffies(timeout));
+ mutex_lock(&mm->cmd_lock);
+ mm->cmd_comp = NULL;
+
+ if (!wait_ret) {
+ mm81x_err(
+ mm,
+ "Try:%d Command %04x:%04x timeout after %u ms",
+ retry, le16_to_cpu(req->hdr.message_id),
+ le16_to_cpu(req->hdr.host_id), timeout);
+ ret = -ETIMEDOUT;
+ } else {
+ ret = (length && resp) ? le32_to_cpu(resp->status) :
+ resp_cb->ret;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "Command 0x%04x:%04x status 0x%08x",
+ le16_to_cpu(req->hdr.message_id),
+ le16_to_cpu(req->hdr.host_id), ret);
+ if (ret) {
+ mm81x_err(mm, "Command 0x%04x:%04x error %d",
+ le16_to_cpu(req->hdr.message_id),
+ le16_to_cpu(req->hdr.host_id), ret);
+ }
+ }
+ /* Free the command request */
+ spin_lock_bh(&cmd_q->lock);
+ mm81x_skbq_skb_finish(cmd_q, skb, NULL);
+ spin_unlock_bh(&cmd_q->lock);
+ mutex_unlock(&mm->cmd_lock);
+
+ retry++;
+ } while ((ret == -ETIMEDOUT) && retry < MM_MAX_COMMAND_RETRY);
+
+ mm81x_ps_enable(mm);
+ mutex_unlock(&mm->cmd_wait);
+
+ if (ret == -ETIMEDOUT) {
+ mm81x_err(mm, "Command %02x:%02x timed out",
+ le16_to_cpu(req->hdr.message_id),
+ le16_to_cpu(req->hdr.host_id));
+ } else if (ret != 0) {
+ mm81x_err(mm, "Command %02x:%02x failed with rc %d (0x%x)\n",
+ le16_to_cpu(req->hdr.message_id),
+ le16_to_cpu(req->hdr.host_id), ret, ret);
+ }
+
+ return ret;
+}
+
+int mm81x_cmd_sta_state(struct mm81x *mm, struct mm81x_vif *mm_vif, u16 aid,
+ struct ieee80211_sta *sta,
+ enum ieee80211_sta_state state)
+{
+ struct host_cmd_req_set_sta_state req;
+ struct host_cmd_resp_set_sta_state resp;
+
+ memset(&req, 0, sizeof(req));
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_SET_STA_STATE, mm_vif->id,
+ sizeof(req));
+
+ memcpy(req.sta_addr, sta->addr, sizeof(req.sta_addr));
+ req.aid = cpu_to_le16(aid);
+ req.state = cpu_to_le16(state);
+ req.uapsd_queues = sta->uapsd_queues;
+
+ return mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, sizeof(resp), 0);
+}
+
+int mm81x_cmd_resp_process(struct mm81x *mm, struct sk_buff *skb)
+{
+ int length, ret = -ESRCH; /* No such process */
+ struct mm81x_skbq *cmd_q = mm81x_hif_get_tx_cmd_queue(mm);
+ struct host_cmd_resp *src_resp = (struct host_cmd_resp *)(skb->data);
+ struct sk_buff *cmd_skb = NULL;
+ struct host_cmd_resp_cb *resp_cb;
+ struct host_cmd_resp *dest_resp;
+ struct host_cmd_req *req;
+ u16 message_id = 0;
+ u16 host_id = 0;
+ u16 resp_message_id = le16_to_cpu(src_resp->hdr.message_id);
+ u16 resp_host_id = le16_to_cpu(src_resp->hdr.host_id);
+ bool is_late_response = false;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "EVT 0x%04x:0x%04x", resp_message_id,
+ resp_host_id);
+
+ if (!HOST_CMD_IS_RESP(src_resp)) {
+ ret = mm81x_mac_event_recv(mm, skb);
+ goto exit_free;
+ }
+
+ mutex_lock(&mm->cmd_lock);
+
+ cmd_skb = mm81x_skbq_tx_pending(cmd_q);
+ if (cmd_skb) {
+ mm81x_skbq_pull_hdr_post_tx(cmd_skb);
+ req = (struct host_cmd_req *)cmd_skb->data;
+ message_id = le16_to_cpu(req->hdr.message_id);
+ host_id = le16_to_cpu(req->hdr.host_id);
+ }
+
+ /*
+ * If there is no pending command or the sequence ID does not match,
+ * this is a late response for a timed out command which has been
+ * cleaned up, so just free up the response. If a command was retried,
+ * the response may be from the retry or from the original command
+ * (late response) but not from both because the firmware will silently
+ * drop a retry if it received the initial request. So a mismatched
+ * retry counter is treated as a matched command and response.
+ */
+ if (!cmd_skb || message_id != resp_message_id ||
+ (host_id & HOST_CMD_HOST_ID_SEQ_MASK) !=
+ (resp_host_id & HOST_CMD_HOST_ID_SEQ_MASK)) {
+ mm81x_err(
+ mm,
+ "Late response for timed out req 0x%04x:%04x have 0x%04x:%04x 0x%04x",
+ resp_message_id, resp_host_id, message_id, host_id,
+ mm->cmd_seq);
+ is_late_response = true;
+ goto exit;
+ }
+ if ((host_id & HOST_CMD_HOST_ID_RETRY_MASK) !=
+ (resp_host_id & HOST_CMD_HOST_ID_RETRY_MASK))
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "Command retry mismatch 0x%04x:%04x 0x%04x:%04x",
+ message_id, host_id, resp_message_id, resp_host_id);
+
+ resp_cb = (struct host_cmd_resp_cb *)IEEE80211_SKB_CB(cmd_skb)
+ ->driver_data;
+ length = resp_cb->length;
+ dest_resp = resp_cb->dest_resp;
+ if (length >= sizeof(struct host_cmd_resp) && dest_resp) {
+ ret = 0;
+ length = min_t(int, length,
+ le16_to_cpu(src_resp->hdr.len) +
+ sizeof(struct host_cmd_header));
+ memcpy(dest_resp, src_resp, length);
+ } else {
+ ret = le32_to_cpu(src_resp->status);
+ }
+
+ resp_cb->ret = ret;
+
+exit:
+ if (cmd_skb && !is_late_response) {
+ /* Complete if not already timed out */
+ if (mm->cmd_comp)
+ complete(mm->cmd_comp);
+ }
+
+ mutex_unlock(&mm->cmd_lock);
+exit_free:
+ dev_kfree_skb(skb);
+ return 0;
+}
+
+int mm81x_cmd_add_if(struct mm81x *mm, u16 *vif_id, const u8 *addr,
+ enum nl80211_iftype type)
+{
+ int ret;
+ struct host_cmd_req_add_interface req;
+ struct host_cmd_resp_add_interface resp;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_ADD_INTERFACE, 0, sizeof(req));
+
+ switch (type) {
+ case NL80211_IFTYPE_STATION:
+ req.interface_type = cpu_to_le32(HOST_CMD_INTERFACE_TYPE_STA);
+ break;
+ case NL80211_IFTYPE_AP:
+ req.interface_type = cpu_to_le32(HOST_CMD_INTERFACE_TYPE_AP);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ memcpy(req.addr.octet, addr, sizeof(req.addr.octet));
+
+ ret = mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, sizeof(resp), 0);
+ if (ret == 0)
+ *vif_id = le16_to_cpu(resp.hdr.vif_id);
+
+ return ret;
+}
+
+int mm81x_cmd_get_capabilities(struct mm81x *mm, u16 vif_id,
+ struct mm81x_fw_caps *capabilities)
+{
+ int ret = 0;
+ int i;
+ struct host_cmd_req_get_capabilities req;
+ struct host_cmd_resp_get_capabilities rsp;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_GET_CAPABILITIES, vif_id,
+ sizeof(req));
+
+ ret = mm81x_cmd_tx(mm, (struct host_cmd_resp *)&rsp,
+ (struct host_cmd_req *)&req, sizeof(rsp), 0);
+ if (ret)
+ return ret;
+
+ capabilities->ampdu_mss = rsp.capabilities.ampdu_mss;
+ capabilities->mm81x_mmss_offset = rsp.morse_mmss_offset;
+ capabilities->beamformee_sts_capability =
+ rsp.capabilities.beamformee_sts_capability;
+ capabilities->maximum_ampdu_length_exponent =
+ rsp.capabilities.maximum_ampdu_length_exponent;
+ capabilities->number_sounding_dimensions =
+ rsp.capabilities.number_sounding_dimensions;
+ for (i = 0; i < FW_CAPABILITIES_FLAGS_WIDTH; i++)
+ capabilities->flags[i] = le32_to_cpu(rsp.capabilities.flags[i]);
+
+ return ret;
+}
+
+int mm81x_cmd_get_max_txpower(struct mm81x *mm, s32 *out_power_mbm)
+{
+ int ret;
+ struct host_cmd_req_get_max_txpower req;
+ struct host_cmd_resp_get_max_txpower resp;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_GET_MAX_TXPOWER, 0,
+ sizeof(req));
+
+ ret = mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, sizeof(resp), 0);
+ if (ret == 0)
+ *out_power_mbm = QDBM_TO_MBM(le32_to_cpu(resp.power_qdbm));
+
+ return ret;
+}
+
+int mm81x_cmd_hw_scan(struct mm81x *mm, struct mm81x_hw_scan_params *params,
+ bool store)
+{
+ int ret;
+ struct host_cmd_req_hw_scan *req;
+ size_t cmd_size;
+ u8 *buf;
+ u32 flags = 0;
+
+ cmd_size = mm81x_hw_scan_h_get_cmd_size(params);
+ cmd_size = ROUND_BYTES_TO_WORD(cmd_size);
+
+ req = kzalloc(cmd_size, GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ buf = req->variable;
+
+ if (store)
+ flags = HOST_CMD_HW_SCAN_FLAGS_STORE;
+ else if (params->operation == MM81X_HW_SCAN_OP_START)
+ flags |= HOST_CMD_HW_SCAN_FLAGS_START;
+ else if (params->operation == MM81X_HW_SCAN_OP_STOP)
+ flags |= HOST_CMD_HW_SCAN_FLAGS_ABORT;
+
+ if (params->use_1mhz_probes)
+ flags |= HOST_CMD_HW_SCAN_FLAGS_1MHZ_PROBES;
+
+ if (params->operation == MM81X_HW_SCAN_OP_START) {
+ req->dwell_time_ms = cpu_to_le32(params->dwell_time_ms);
+ buf = mm81x_hw_scan_h_insert_tlvs(params, buf);
+ }
+
+ req->flags = cpu_to_le32(flags);
+ mm81x_cmd_init(mm, &req->hdr, HOST_CMD_ID_HW_SCAN, 0, buf - (u8 *)req);
+ ret = mm81x_cmd_tx(mm, NULL, (struct host_cmd_req *)req, 0, 0);
+ kfree(req);
+
+ return ret;
+}
+
+int mm81x_cmd_set_txpower(struct mm81x *mm, s32 *out_power_mbm, int txpower_mbm)
+{
+ int ret;
+ struct host_cmd_req_set_txpower req;
+ struct host_cmd_resp_set_txpower resp;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_SET_TXPOWER, 0, sizeof(req));
+
+ req.power_qdbm = cpu_to_le32(MBM_TO_QDBM(txpower_mbm));
+
+ ret = mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, sizeof(resp), 0);
+ if (ret == 0)
+ *out_power_mbm = QDBM_TO_MBM(le32_to_cpu(resp.power_qdbm));
+
+ return ret;
+}
+
+int mm81x_cmd_set_channel(struct mm81x *mm, u32 op_chan_freq_hz,
+ u8 pri_1mhz_chan_idx, u8 op_bw_mhz, u8 pri_bw_mhz,
+ s32 *power_mbm)
+{
+ int ret;
+ struct host_cmd_req_set_channel req;
+ struct host_cmd_resp_set_channel resp;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_SET_CHANNEL, 0, sizeof(req));
+
+ req.op_chan_freq_hz = cpu_to_le32(op_chan_freq_hz);
+ req.op_bw_mhz = op_bw_mhz;
+ req.pri_bw_mhz = pri_bw_mhz;
+ req.pri_1mhz_chan_idx = pri_1mhz_chan_idx;
+ req.dot11_mode = HOST_CMD_DOT11_PROTO_MODE_AH;
+
+ ret = mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, sizeof(resp), 0);
+ if (!ret)
+ *power_mbm = QDBM_TO_MBM(le32_to_cpu(resp.power_qdbm));
+
+ return ret;
+}
+
+int mm81x_cmd_disable_key(struct mm81x *mm, struct mm81x_vif *mm_vif, u16 aid,
+ struct ieee80211_key_conf *key)
+{
+ struct host_cmd_req_disable_key req;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "%s Disabling key for vif (%d):\n"
+ "\tkey->hw_key_idx: %d\n"
+ "\taid (optional): %d\n",
+ __func__, mm_vif->id, key->hw_key_idx, aid);
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_DISABLE_KEY, mm_vif->id,
+ sizeof(req));
+
+ req.aid = cpu_to_le32(aid);
+ req.key_idx = key->hw_key_idx;
+ req.key_type = cpu_to_le32((key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ?
+ HOST_CMD_TEMPORAL_KEY_TYPE_PTK :
+ HOST_CMD_TEMPORAL_KEY_TYPE_GTK);
+
+ return mm81x_cmd_tx(mm, NULL, (struct host_cmd_req *)&req, 0, 0);
+}
+
+int mm81x_cmd_install_key(struct mm81x *mm, struct mm81x_vif *mm_vif, u16 aid,
+ struct ieee80211_key_conf *key,
+ enum host_cmd_key_cipher cipher,
+ enum host_cmd_aes_key_len length)
+{
+ int ret;
+ struct host_cmd_req_install_key req;
+ struct host_cmd_resp_install_key resp;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "%s Installing key for vif (%d):\n"
+ "\tkey->idx: %d\n"
+ "\tkey->cipher: 0x%08x\n"
+ "\tkey->pn: %lld\n"
+ "\tkey->len: %d\n"
+ "\tkey->flags: 0x%08x\n"
+ "\taid (optional): %d\n",
+ __func__, mm_vif->id, key->keyidx, key->cipher,
+ (u64)atomic64_read(&key->tx_pn), key->keylen, key->flags,
+ aid);
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_INSTALL_KEY, mm_vif->id,
+ sizeof(req));
+
+ req.pn = cpu_to_le64(atomic64_read(&key->tx_pn));
+ req.aid = cpu_to_le32(aid);
+ req.cipher = cipher;
+ req.key_length = length;
+ req.key_idx = key->keyidx;
+ req.key_type = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ?
+ HOST_CMD_TEMPORAL_KEY_TYPE_PTK :
+ HOST_CMD_TEMPORAL_KEY_TYPE_GTK;
+
+ if (key->keylen > sizeof(req.key))
+ return -EINVAL;
+
+ memcpy(req.key, key->key, key->keylen);
+
+ ret = mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, sizeof(resp), 0);
+
+ if (ret == 0) {
+ key->hw_key_idx = resp.key_idx;
+ mm81x_dbg(mm, MM81X_DBG_ANY, "Installed key @ hw index: %d",
+ resp.key_idx);
+ }
+
+ return ret;
+}
+
+int mm81x_cmd_cfg_multicast_filter(struct mm81x *mm, struct mm81x_vif *mm_vif)
+{
+ struct host_cmd_req_mcast_filter *req;
+ struct mcast_filter *filter = mm->mcast_filter;
+ u16 filter_list_len = sizeof(filter->addr_list[0]) * filter->count;
+ u16 alloc_len = filter_list_len + sizeof(*req);
+ int ret = 0;
+
+ req = kmalloc(alloc_len, GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ mm81x_cmd_init(mm, &req->hdr, HOST_CMD_ID_MCAST_FILTER, mm_vif->id,
+ alloc_len);
+
+ req->count = filter->count;
+ memcpy(req->hw_addr, filter->addr_list, filter_list_len);
+
+ ret = mm81x_cmd_tx(mm, NULL, (struct host_cmd_req *)req, 0, 0);
+ kfree(req);
+ return ret;
+}
+
+int mm81x_cmd_cfg_bss(struct mm81x *mm, u16 vif_id, u16 beacon_int,
+ u16 dtim_period, u32 cssid)
+{
+ struct host_cmd_req_bss_config req;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_BSS_CONFIG, vif_id,
+ sizeof(req));
+
+ req.beacon_interval_tu = cpu_to_le16(beacon_int);
+ req.cssid = cpu_to_le32(cssid);
+ req.dtim_period = cpu_to_le16(dtim_period);
+
+ return mm81x_cmd_tx(mm, NULL, (struct host_cmd_req *)&req, 0, 0);
+}
+
+int mm81x_cmd_config_beacon_timer(struct mm81x *mm, void *mm81x_vif,
+ bool enabled)
+{
+ struct host_cmd_req_bss_beacon_config req;
+ struct host_cmd_resp_bss_beacon_config resp;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_BSS_BEACON_CONFIG,
+ ((struct mm81x_vif *)mm81x_vif)->id, sizeof(req));
+ req.enable = enabled;
+
+ return mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, 0, 0);
+}
+
+int mm81x_cmd_set_ps(struct mm81x *mm, bool enabled)
+{
+ struct host_cmd_req_config_ps req;
+
+ if (!mm->ps.enable)
+ return 0;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_CONFIG_PS, 0, sizeof(req));
+
+ req.enabled = (u8)enabled;
+ req.dynamic_ps_offload = false;
+
+ return mm81x_cmd_tx(mm, NULL, (struct host_cmd_req *)&req, 0,
+ HOST_CMD_POWERSAVE_TIMEOUT_MS);
+}
+
+int mm81x_cmd_cfg_qos(struct mm81x *mm, struct mm81x_queue_params *params)
+{
+ struct host_cmd_req_set_qos_params req;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_SET_QOS_PARAMS, 0,
+ sizeof(req));
+
+ req.uapsd = params->uapsd;
+ req.queue_idx = params->aci;
+ req.aifs_slot_count = params->aifs;
+ req.contention_window_min = cpu_to_le16(params->cw_min);
+ req.contention_window_max = cpu_to_le16(params->cw_max);
+ req.max_txop_usec = cpu_to_le32(params->txop);
+
+ return mm81x_cmd_tx(mm, NULL, (struct host_cmd_req *)&req, 0, 0);
+}
+
+int mm81x_cmd_rm_if(struct mm81x *mm, u16 vif_id)
+{
+ struct host_cmd_req_remove_interface req;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_REMOVE_INTERFACE, vif_id,
+ sizeof(req));
+
+ return mm81x_cmd_tx(mm, NULL, (struct host_cmd_req *)&req, 0, 0);
+}
+
+int mm81x_cmd_set_frag_threshold(struct mm81x *mm, u32 frag_threshold)
+{
+ struct host_cmd_req_get_set_generic_param req = {
+ .param_id = cpu_to_le32(HOST_CMD_PARAM_ID_FRAGMENT_THRESHOLD),
+ .action = cpu_to_le32(HOST_CMD_PARAM_ACTION_SET),
+ .value = cpu_to_le32(frag_threshold),
+ };
+ struct host_cmd_resp_get_set_generic_param resp;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_GET_SET_GENERIC_PARAM, 0,
+ sizeof(req));
+
+ return mm81x_cmd_tx(mm, (struct host_cmd_resp *)&resp,
+ (struct host_cmd_req *)&req, sizeof(resp), 0);
+}
+
+int mm81x_cmd_get_disabled_channels(
+ struct mm81x *mm, struct host_cmd_resp_get_disabled_channels *resp,
+ uint resp_len)
+{
+ struct host_cmd_req req;
+
+ mm81x_cmd_init(mm, &req.hdr, HOST_CMD_ID_GET_DISABLED_CHANNELS, 0,
+ sizeof(req));
+
+ return mm81x_cmd_tx(mm, (struct host_cmd_resp *)resp, &req, resp_len,
+ 0);
+}
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 03/35] wifi: mm81x: add command_defs.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
.../wireless/morsemicro/mm81x/command_defs.h | 1668 +++++++++++++++++
1 file changed, 1668 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/command_defs.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/command_defs.h b/drivers/net/wireless/morsemicro/mm81x/command_defs.h
new file mode 100644
index 000000000000..71e6f21bf658
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/command_defs.h
@@ -0,0 +1,1668 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+#ifndef _MM81X_COMMAND_DEFS_H_
+#define _MM81X_COMMAND_DEFS_H_
+
+#include <linux/types.h>
+
+#define __sle16 __le16
+#define __sle32 __le32
+#define __sle64 __le64
+
+#define HOST_CMD_SEMVER_MAJOR 56
+#define HOST_CMD_SEMVER_MINOR 24
+#define HOST_CMD_SEMVER_PATCH 0
+
+#define HOST_CMD_TYPE_REQ BIT(0)
+#define HOST_CMD_TYPE_RESP BIT(1)
+#define HOST_CMD_TYPE_EVT BIT(2)
+
+#define HOST_CMD_SSID_MAX_LEN 32
+#define HOST_CMD_MAC_ADDR_LEN 6
+
+enum host_cmd_id {
+ HOST_CMD_ID_SET_CHANNEL = 0x0001,
+ HOST_CMD_ID_GET_CHANNEL = 0x001D,
+ HOST_CMD_ID_GET_CHANNEL_FULL = 0x0013,
+ HOST_CMD_ID_GET_CHANNEL_DTIM = 0x001C,
+ HOST_CMD_ID_GET_VERSION = 0x0002,
+ HOST_CMD_ID_SET_TXPOWER = 0x0003,
+ HOST_CMD_ID_GET_MAX_TXPOWER = 0x0024,
+ HOST_CMD_ID_ADD_INTERFACE = 0x0004,
+ HOST_CMD_ID_REMOVE_INTERFACE = 0x0005,
+ HOST_CMD_ID_BSS_CONFIG = 0x0006,
+ HOST_CMD_ID_SCAN_CONFIG = 0x0010,
+ HOST_CMD_ID_SET_QOS_PARAMS = 0x0011,
+ HOST_CMD_ID_GET_QOS_PARAMS = 0x0012,
+ HOST_CMD_ID_SET_STA_STATE = 0x0014,
+ HOST_CMD_ID_SET_BSS_COLOR = 0x0015,
+ HOST_CMD_ID_CONFIG_PS = 0x0016,
+ HOST_CMD_ID_HEALTH_CHECK = 0x0019,
+ HOST_CMD_ID_CTS_SELF_PS = 0x001A,
+ HOST_CMD_ID_DTIM_CHANNEL_ENABLE = 0x001B,
+ HOST_CMD_ID_ARP_OFFLOAD = 0x0020,
+ HOST_CMD_ID_SET_LONG_SLEEP_CONFIG = 0x0021,
+ HOST_CMD_ID_SET_DUTY_CYCLE = 0x0022,
+ HOST_CMD_ID_GET_DUTY_CYCLE = 0x0023,
+ HOST_CMD_ID_GET_CAPABILITIES = 0x0025,
+ HOST_CMD_ID_TWT_AGREEMENT_INSTALL = 0x0026,
+ HOST_CMD_ID_TWT_AGREEMENT_VALIDATE = 0x0036,
+ HOST_CMD_ID_TWT_AGREEMENT_REMOVE = 0x0027,
+ HOST_CMD_ID_GET_TSF = 0x0028,
+ HOST_CMD_ID_MAC_ADDR = 0x0029,
+ HOST_CMD_ID_MPSW_CONFIG = 0x0030,
+ HOST_CMD_ID_INSTALL_KEY = 0x000A,
+ HOST_CMD_ID_DISABLE_KEY = 0x000B,
+ HOST_CMD_ID_DHCP_OFFLOAD = 0x0032,
+ HOST_CMD_ID_SET_KEEP_ALIVE_OFFLOAD = 0x0033,
+ HOST_CMD_ID_UPDATE_OUI_FILTER = 0x0034,
+ HOST_CMD_ID_IBSS_CONFIG = 0x0035,
+ HOST_CMD_ID_OCS = 0x0038,
+ HOST_CMD_ID_MESH_CONFIG = 0x0039,
+ HOST_CMD_ID_SET_OFFSET_TSF = 0x003A,
+ HOST_CMD_ID_GET_CHANNEL_USAGE = 0x003B,
+ HOST_CMD_ID_MCAST_FILTER = 0x003C,
+ HOST_CMD_ID_BSS_BEACON_CONFIG = 0x003D,
+ HOST_CMD_ID_UAPSD_CONFIG = 0x0040,
+ HOST_CMD_ID_PAGE_SLICING_CONFIG = 0x0043,
+ HOST_CMD_ID_HW_SCAN = 0x0044,
+ HOST_CMD_ID_SET_WHITELIST = 0x0045,
+ HOST_CMD_ID_ARP_PERIODIC_REFRESH = 0x0046,
+ HOST_CMD_ID_SET_TCP_KEEPALIVE = 0x0047,
+ HOST_CMD_ID_FORCE_POWER_MODE = 0x0048,
+ HOST_CMD_ID_LI_SLEEP = 0x0049,
+ HOST_CMD_ID_GET_DISABLED_CHANNELS = 0x004A,
+ HOST_CMD_ID_SET_CQM_RSSI = 0x004F,
+ HOST_CMD_ID_GET_APF_CAPABILITIES = 0x0050,
+ HOST_CMD_ID_READ_WRITE_APF = 0x0051,
+ HOST_CMD_ID_BSSID_SET = 0x0052,
+ HOST_CMD_ID_BEACON_OFFLOAD = 0x0053,
+ HOST_CMD_ID_PROBE_RESPONSE_OFFLOAD = 0x0054,
+ HOST_CMD_ID_HOST_STATS_LOG = 0x2007,
+ HOST_CMD_ID_HOST_STATS_RESET = 0x2008,
+ HOST_CMD_ID_MAC_STATS_LOG = 0x200C,
+ HOST_CMD_ID_MAC_STATS_RESET = 0x200D,
+ HOST_CMD_ID_UPHY_STATS_LOG = 0x200E,
+ HOST_CMD_ID_UPHY_STATS_RESET = 0x200F,
+ HOST_CMD_ID_SET_STA_TYPE = 0xA000,
+ HOST_CMD_ID_SET_ENC_MODE = 0xA001,
+ HOST_CMD_ID_TEST_BA = 0xA002,
+ HOST_CMD_ID_SET_LISTEN_INTERVAL = 0xA003,
+ HOST_CMD_ID_SET_AMPDU = 0xA004,
+ HOST_CMD_ID_COREDUMP = 0xA006,
+ HOST_CMD_ID_SET_S1G_OP_CLASS = 0xA007,
+ HOST_CMD_ID_SEND_WAKE_ACTION_FRAME = 0xA008,
+ HOST_CMD_ID_VENDOR_IE_CONFIG = 0xA009,
+ HOST_CMD_ID_SET_TWT_CONF = 0xA010,
+ HOST_CMD_ID_GET_AVAILABLE_CHANNELS = 0xA011,
+ HOST_CMD_ID_SET_ECSA_S1G_INFO = 0xA012,
+ HOST_CMD_ID_GET_HW_VERSION = 0xA013,
+ HOST_CMD_ID_CAC = 0xA014,
+ HOST_CMD_ID_DRIVER_SET_DUTY_CYCLE = 0xA015,
+ HOST_CMD_ID_OCS_DRIVER = 0xA017,
+ HOST_CMD_ID_MBSSID = 0xA016,
+ HOST_CMD_ID_SET_MESH_CONFIG = 0xA018,
+ HOST_CMD_ID_SET_MCBA_CONF = 0xA019,
+ HOST_CMD_ID_DYNAMIC_PEERING_CONFIG = 0xA020,
+ HOST_CMD_ID_CONFIG_RAW = 0xA021,
+ HOST_CMD_ID_CONFIG_BSS_STATS = 0xA022,
+ HOST_CMD_ID_GET_RSSI = 0x1002,
+ HOST_CMD_ID_SET_IFS = 0x1003,
+ HOST_CMD_ID_SET_FEM_SETTINGS = 0x1005,
+ HOST_CMD_ID_SET_TXOP = 0x1008,
+ HOST_CMD_ID_SET_CONTROL_RESPONSE = 0x1009,
+ HOST_CMD_ID_SET_PERIODIC_CAL = 0x100A,
+ HOST_CMD_ID_SET_BCN_RSSI_THRESHOLD = 0x100B,
+ HOST_CMD_ID_SET_TX_PKT_LIFETIME_USECS = 0x100C,
+ HOST_CMD_ID_SET_PHYSM_WATCHDOG = 0x100D,
+ HOST_CMD_ID_TX_POLAR = 0x100E,
+ HOST_CMD_ID_EVT_STA_STATE = 0x4001,
+ HOST_CMD_ID_EVT_BEACON_LOSS = 0x4002,
+ HOST_CMD_ID_EVT_SIG_FIELD_ERROR = 0x4003,
+ HOST_CMD_ID_EVT_UMAC_TRAFFIC_CONTROL = 0x4004,
+ HOST_CMD_ID_EVT_DHCP_LEASE_UPDATE = 0x4005,
+ HOST_CMD_ID_EVT_OCS_DONE = 0x4006,
+ HOST_CMD_ID_EVT_HW_SCAN_DONE = 0x4011,
+ HOST_CMD_ID_EVT_CHANNEL_USAGE = 0x4012,
+ HOST_CMD_ID_EVT_CONNECTION_LOSS = 0x4013,
+ HOST_CMD_ID_EVT_SCHED_SCAN_RESULTS = 0x4014,
+ HOST_CMD_ID_EVT_CQM_RSSI_NOTIFY = 0x4015,
+ HOST_CMD_ID_EVT_NDP_PROBE_REQUEST_RECEIVED = 0x4017,
+ HOST_CMD_ID_EVT_SCAN_DONE = 0x4007,
+ HOST_CMD_ID_EVT_SCAN_RESULT = 0x4008,
+ HOST_CMD_ID_EVT_CONNECTED = 0x4009,
+ HOST_CMD_ID_EVT_DISCONNECTED = 0x4010,
+ HOST_CMD_ID_EVT_BEACON_FILTER_MATCH = 0x4016,
+ HOST_CMD_ID_SET_CAPABILITIES = 0x8118,
+ HOST_CMD_ID_SET_TRANSMISSION_RATE = 0x8009,
+ HOST_CMD_ID_FORCE_ASSERT = 0x800E,
+ HOST_CMD_ID_GET_SET_GENERIC_PARAM = 0x003E,
+};
+
+struct host_cmd_mac_addr {
+ u8 octet[HOST_CMD_MAC_ADDR_LEN];
+};
+
+enum host_cmd_ocs_subcmd {
+ HOST_CMD_OCS_SUBCMD_CONFIG = 1,
+ HOST_CMD_OCS_SUBCMD_STATUS = 2,
+};
+
+enum host_cmd_headless_cfg_option {
+ HOST_CMD_HEADLESS_CFG_OPTION_KEEP_IFACES = BIT(0),
+ HOST_CMD_HEADLESS_CFG_OPTION_BUFFER_RX = BIT(1),
+ HOST_CMD_HEADLESS_CFG_OPTION_NOTIFY_ON_ANY_RX = BIT(2),
+};
+
+struct host_cmd_header {
+ __le16 flags;
+ __le16 message_id;
+ __le16 len;
+ __le16 host_id;
+ __le16 vif_id;
+ __le16 pad;
+};
+
+#define HOST_CMD_CHANNEL_BW_NOT_SET 0xFF
+#define HOST_CMD_CHANNEL_IDX_NOT_SET 0xFF
+#define HOST_CMD_CHANNEL_FREQ_NOT_SET 0xFFFFFFFF
+
+enum host_cmd_dot11_proto_mode {
+ HOST_CMD_DOT11_PROTO_MODE_AH = 0,
+};
+
+struct host_cmd_req_set_channel {
+ struct host_cmd_header hdr;
+ __le32 op_chan_freq_hz;
+ u8 op_bw_mhz;
+ u8 pri_bw_mhz;
+ u8 pri_1mhz_chan_idx;
+ u8 dot11_mode;
+ u8 __deprecated_reg_tx_power_set;
+ u8 is_off_channel;
+} __packed;
+
+struct host_cmd_resp_set_channel {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __sle32 power_qdbm;
+} __packed;
+
+struct host_cmd_req_get_channel {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_channel {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 op_chan_freq_hz;
+ u8 op_chan_bw_mhz;
+ u8 pri_chan_bw_mhz;
+ u8 pri_1mhz_chan_idx;
+} __packed;
+
+#define HOST_CMD_MAX_VERSION_LEN 128
+
+struct host_cmd_req_get_version {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_version {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __sle32 length;
+ u8 version[];
+} __packed;
+
+struct host_cmd_req_set_txpower {
+ struct host_cmd_header hdr;
+ __sle32 power_qdbm;
+} __packed;
+
+struct host_cmd_resp_set_txpower {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __sle32 power_qdbm;
+} __packed;
+
+struct host_cmd_req_get_max_txpower {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_max_txpower {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __sle32 power_qdbm;
+} __packed;
+
+enum host_cmd_interface_type {
+ HOST_CMD_INTERFACE_TYPE_INVALID = 0,
+ HOST_CMD_INTERFACE_TYPE_STA = 1,
+ HOST_CMD_INTERFACE_TYPE_AP = 2,
+ HOST_CMD_INTERFACE_TYPE_MON = 3,
+ HOST_CMD_INTERFACE_TYPE_ADHOC = 4,
+ HOST_CMD_INTERFACE_TYPE_MESH = 5,
+ HOST_CMD_INTERFACE_TYPE_LAST = HOST_CMD_INTERFACE_TYPE_MESH,
+};
+
+struct host_cmd_req_add_interface {
+ struct host_cmd_header hdr;
+ struct host_cmd_mac_addr addr;
+ __le32 interface_type;
+} __packed;
+
+struct host_cmd_resp_add_interface {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_remove_interface {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_remove_interface {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_bss_config {
+ struct host_cmd_header hdr;
+ __le16 beacon_interval_tu;
+ __le16 dtim_period;
+ u8 __padding[2];
+ __le32 cssid;
+} __packed;
+
+struct host_cmd_resp_bss_config {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_scan_config {
+ struct host_cmd_header hdr;
+ u8 enabled;
+ u8 is_survey;
+} __packed;
+
+struct host_cmd_resp_scan_config {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_qos_params {
+ struct host_cmd_header hdr;
+ u8 uapsd;
+ u8 queue_idx;
+ u8 aifs_slot_count;
+ __le16 contention_window_min;
+ __le16 contention_window_max;
+ __le32 max_txop_usec;
+} __packed;
+
+struct host_cmd_resp_set_qos_params {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_get_qos_params {
+ struct host_cmd_header hdr;
+ u8 queue_idx;
+} __packed;
+
+struct host_cmd_resp_get_qos_params {
+ struct host_cmd_header hdr;
+ __le32 status;
+ u8 aifs_slot_count;
+ __le16 contention_window_min;
+ __le16 contention_window_max;
+ __le32 max_txop_usec;
+} __packed;
+
+struct host_cmd_req_set_sta_state {
+ struct host_cmd_header hdr;
+ u8 sta_addr[HOST_CMD_MAC_ADDR_LEN];
+ __le16 aid;
+ __le16 state;
+ u8 uapsd_queues;
+ __le32 flags;
+} __packed;
+
+struct host_cmd_resp_set_sta_state {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_bss_color {
+ struct host_cmd_header hdr;
+ u8 bss_color;
+} __packed;
+
+struct host_cmd_resp_set_bss_color {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_config_ps {
+ struct host_cmd_header hdr;
+ u8 enabled;
+ u8 dynamic_ps_offload;
+} __packed;
+
+struct host_cmd_resp_config_ps {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_health_check {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_health_check {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_cts_self_ps {
+ struct host_cmd_header hdr;
+ u8 enable;
+} __packed;
+
+struct host_cmd_resp_cts_self_ps {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_dtim_channel_enable {
+ struct host_cmd_header hdr;
+ u8 enable;
+} __packed;
+
+struct host_cmd_resp_dtim_channel_enable {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+#define HOST_CMD_ARP_OFFLOAD_MAX_IP_ADDRESSES 4
+
+struct host_cmd_req_arp_offload {
+ struct host_cmd_header hdr;
+ __be32 ip_table[HOST_CMD_ARP_OFFLOAD_MAX_IP_ADDRESSES];
+} __packed;
+
+struct host_cmd_resp_arp_offload {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_long_sleep_config {
+ struct host_cmd_header hdr;
+ u8 enabled;
+} __packed;
+
+struct host_cmd_resp_set_long_sleep_config {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+#define HOST_CMD_DUTY_CYCLE_SET_CFG_DUTY_CYCLE BIT(0)
+#define HOST_CMD_DUTY_CYCLE_SET_CFG_OMIT_CONTROL_RESP BIT(1)
+#define HOST_CMD_DUTY_CYCLE_SET_CFG_EXT BIT(2)
+#define HOST_CMD_DUTY_CYCLE_SET_CFG_BURST_RECORD_UNIT BIT(3)
+
+enum host_cmd_duty_cycle_mode {
+ HOST_CMD_DUTY_CYCLE_MODE_SPREAD = 0,
+ HOST_CMD_DUTY_CYCLE_MODE_BURST = 1,
+ HOST_CMD_DUTY_CYCLE_MODE_LAST = HOST_CMD_DUTY_CYCLE_MODE_BURST,
+};
+
+struct host_cmd_duty_cycle_configuration {
+ u8 omit_control_responses;
+ __le32 duty_cycle;
+} __packed;
+
+struct host_cmd_duty_cycle_set_configuration_ext {
+ __le32 burst_record_unit_us;
+ u8 mode;
+} __packed;
+
+struct host_cmd_duty_cycle_configuration_ext {
+ __le32 airtime_remaining_us;
+ __le32 burst_window_duration_us;
+ struct host_cmd_duty_cycle_set_configuration_ext set;
+} __packed;
+
+struct host_cmd_req_set_duty_cycle {
+ struct host_cmd_header hdr;
+ struct host_cmd_duty_cycle_configuration config;
+ u8 set_cfgs;
+ struct host_cmd_duty_cycle_set_configuration_ext config_ext;
+} __packed;
+
+struct host_cmd_resp_get_duty_cycle {
+ struct host_cmd_header hdr;
+ __le32 status;
+ struct host_cmd_duty_cycle_configuration config;
+ struct host_cmd_duty_cycle_configuration_ext config_ext;
+} __packed;
+
+#define HOST_CMD_SET_S1G_CAP_FLAGS BIT(0)
+#define HOST_CMD_SET_S1G_CAP_AMPDU_MSS BIT(1)
+#define HOST_CMD_SET_S1G_CAP_BEAM_STS BIT(2)
+#define HOST_CMD_SET_S1G_CAP_NUM_SOUND_DIMS BIT(3)
+#define HOST_CMD_SET_S1G_CAP_MAX_AMPDU_LEXP BIT(4)
+#define HOST_CMD_SET_MORSE_CAP_MMSS_OFFSET BIT(5)
+#define HOST_CMD_S1G_CAPABILITY_FLAGS_WIDTH 4
+
+struct host_cmd_mm_capabilities {
+ __le32 flags[HOST_CMD_S1G_CAPABILITY_FLAGS_WIDTH];
+ u8 ampdu_mss;
+ u8 beamformee_sts_capability;
+ u8 number_sounding_dimensions;
+ u8 maximum_ampdu_length_exponent;
+} __packed;
+
+struct host_cmd_req_get_capabilities {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_capabilities {
+ struct host_cmd_header hdr;
+ __le32 status;
+ struct host_cmd_mm_capabilities capabilities;
+ u8 morse_mmss_offset;
+} __packed;
+
+#define HOST_CMD_DOT11_TWT_AGREEMENT_MAX_LEN 20
+
+struct host_cmd_req_twt_agreement_install {
+ struct host_cmd_header hdr;
+ u8 flow_id;
+ u8 agreement_len;
+ u8 agreement[HOST_CMD_DOT11_TWT_AGREEMENT_MAX_LEN];
+} __packed;
+
+struct host_cmd_resp_twt_agreement_install {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_twt_agreement_validate {
+ struct host_cmd_header hdr;
+ u8 flow_id;
+ u8 agreement_len;
+ u8 agreement[HOST_CMD_DOT11_TWT_AGREEMENT_MAX_LEN];
+} __packed;
+
+struct host_cmd_resp_twt_agreement_validate {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_twt_agreement_remove {
+ struct host_cmd_header hdr;
+ u8 flow_id;
+} __packed;
+
+struct host_cmd_req_get_tsf {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_tsf {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le64 now_tsf;
+ __le64 now_chip_ts;
+} __packed;
+
+struct host_cmd_req_mac_addr {
+ struct host_cmd_header hdr;
+ u8 write;
+ u8 octet[HOST_CMD_MAC_ADDR_LEN];
+} __packed;
+
+struct host_cmd_resp_mac_addr {
+ struct host_cmd_header hdr;
+ __le32 status;
+ u8 octet[HOST_CMD_MAC_ADDR_LEN];
+} __packed;
+
+#define HOST_CMD_SET_MPSW_CFG_AIRTIME_BOUNDS BIT(0)
+#define HOST_CMD_SET_MPSW_CFG_PKT_SPC_WIN_LEN BIT(1)
+#define HOST_CMD_SET_MPSW_CFG_ENABLED BIT(2)
+
+struct host_cmd_mpsw_configuration {
+ __le32 airtime_max_us;
+ __le32 airtime_min_us;
+ __le32 packet_space_window_length_us;
+ u8 enable;
+} __packed;
+
+struct host_cmd_req_mpsw_config {
+ struct host_cmd_header hdr;
+ struct host_cmd_mpsw_configuration config;
+ u8 set_cfgs;
+} __packed;
+
+struct host_cmd_resp_mpsw_config {
+ struct host_cmd_header hdr;
+ __le32 status;
+ struct host_cmd_mpsw_configuration config;
+} __packed;
+
+#define HOST_CMD_MAX_KEY_LEN 32
+
+enum host_cmd_key_cipher {
+ HOST_CMD_KEY_CIPHER_INVALID = 0,
+ HOST_CMD_KEY_CIPHER_AES_CCM = 1,
+ HOST_CMD_KEY_CIPHER_AES_GCM = 2,
+ HOST_CMD_KEY_CIPHER_AES_CMAC = 3,
+ HOST_CMD_KEY_CIPHER_AES_GMAC = 4,
+ HOST_CMD_KEY_CIPHER_LAST = HOST_CMD_KEY_CIPHER_AES_GMAC,
+};
+
+enum host_cmd_aes_key_len {
+ HOST_CMD_AES_KEY_LEN_INVALID = 0,
+ HOST_CMD_AES_KEY_LEN_LENGTH_128 = 1,
+ HOST_CMD_AES_KEY_LEN_LENGTH_256 = 2,
+ HOST_CMD_AES_KEY_LEN_LENGTH_LAST = HOST_CMD_AES_KEY_LEN_LENGTH_256,
+};
+
+enum host_cmd_temporal_key_type {
+ HOST_CMD_TEMPORAL_KEY_TYPE_INVALID = 0,
+ HOST_CMD_TEMPORAL_KEY_TYPE_GTK = 1,
+ HOST_CMD_TEMPORAL_KEY_TYPE_PTK = 2,
+ HOST_CMD_TEMPORAL_KEY_TYPE_IGTK = 3,
+ HOST_CMD_TEMPORAL_KEY_TYPE_LAST = HOST_CMD_TEMPORAL_KEY_TYPE_IGTK,
+};
+
+struct host_cmd_req_install_key {
+ struct host_cmd_header hdr;
+ __le64 pn;
+ __le32 aid;
+ u8 key_idx;
+ u8 cipher;
+ u8 key_length;
+ u8 key_type;
+ u8 __padding[2];
+ u8 key[HOST_CMD_MAX_KEY_LEN];
+} __packed;
+
+struct host_cmd_resp_install_key {
+ struct host_cmd_header hdr;
+ __le32 status;
+ u8 key_idx;
+} __packed;
+
+struct host_cmd_req_disable_key {
+ struct host_cmd_header hdr;
+ __le32 key_type;
+ __le32 aid;
+ u8 key_idx;
+} __packed;
+
+struct host_cmd_resp_disable_key {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+enum host_cmd_dhcp_opcode {
+ HOST_CMD_DHCP_OPCODE_ENABLE = 0,
+ HOST_CMD_DHCP_OPCODE_DO_DISCOVERY = 1,
+ HOST_CMD_DHCP_OPCODE_GET_LEASE = 2,
+ HOST_CMD_DHCP_OPCODE_CLEAR_LEASE = 3,
+ HOST_CMD_DHCP_OPCODE_RENEW_LEASE = 4,
+ HOST_CMD_DHCP_OPCODE_REBIND_LEASE = 5,
+ HOST_CMD_DHCP_OPCODE_SEND_LEASE_UPDATE = 6,
+};
+
+enum host_cmd_dhcp_retcode {
+ HOST_CMD_DHCP_RETCODE_SUCCESS = 0,
+ HOST_CMD_DHCP_RETCODE_NOT_ENABLED = 1,
+ HOST_CMD_DHCP_RETCODE_ALREADY_ENABLED = 2,
+ HOST_CMD_DHCP_RETCODE_NO_LEASE = 3,
+ HOST_CMD_DHCP_RETCODE_HAVE_LEASE = 4,
+ HOST_CMD_DHCP_RETCODE_BUSY = 5,
+ HOST_CMD_DHCP_RETCODE_BAD_VIF = 6,
+};
+
+struct host_cmd_req_dhcp_offload {
+ struct host_cmd_header hdr;
+ __le32 opcode;
+} __packed;
+
+struct host_cmd_resp_dhcp_offload {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 retcode;
+ __le32 my_ip;
+ __le32 netmask;
+ __le32 router;
+ __le32 dns;
+} __packed;
+
+struct host_cmd_req_set_keep_alive_offload {
+ struct host_cmd_header hdr;
+ __le16 bss_max_idle_period;
+ u8 interpret_as_11ah;
+} __packed;
+
+#define HOST_CMD_MAX_OUI_FILTERS 5
+#define HOST_CMD_OUI_SIZE 3
+#define HOST_CMD_MAX_OUI_FILTER_ARRAY_SIZE 15
+
+struct host_cmd_req_update_oui_filter {
+ struct host_cmd_header hdr;
+ u8 n_ouis;
+ u8 ouis[HOST_CMD_MAX_OUI_FILTERS][HOST_CMD_OUI_SIZE];
+} __packed;
+
+enum host_cmd_ibss_config_opcode {
+ HOST_CMD_IBSS_CONFIG_OPCODE_CREATE = 0,
+ HOST_CMD_IBSS_CONFIG_OPCODE_JOIN = 1,
+ HOST_CMD_IBSS_CONFIG_OPCODE_STOP = 2,
+};
+
+struct host_cmd_req_ibss_config {
+ struct host_cmd_header hdr;
+ u8 ibss_bssid[HOST_CMD_MAC_ADDR_LEN];
+ u8 ibss_cfg_opcode;
+ u8 ibss_probe_filtering;
+} __packed;
+
+enum host_cmd_ocs_type {
+ HOST_CMD_OCS_TYPE_QNULL = 0,
+ HOST_CMD_OCS_TYPE_RAW = 1,
+};
+
+struct host_cmd_ocs_config_req {
+ __le32 op_channel_freq_hz;
+ u8 op_channel_bw_mhz;
+ u8 pri_channel_bw_mhz;
+ u8 pri_1mhz_channel_index;
+ __le16 aid;
+ u8 type;
+} __packed;
+
+struct host_cmd_ocs_status_resp {
+ u8 running;
+} __packed;
+
+struct host_cmd_req_ocs {
+ struct host_cmd_header hdr;
+ __le32 subcmd;
+ union {
+ u8 opaque[0];
+ struct host_cmd_ocs_config_req config;
+ };
+} __packed;
+
+struct host_cmd_resp_ocs {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 subcmd;
+ union {
+ u8 opaque[0];
+ struct host_cmd_ocs_status_resp ocs_status;
+ };
+} __packed;
+
+enum host_cmd_mesh_config_opcode {
+ HOST_CMD_MESH_CONFIG_OPCODE_START = 0,
+ HOST_CMD_MESH_CONFIG_OPCODE_STOP = 1,
+};
+
+struct host_cmd_req_mesh_config {
+ struct host_cmd_header hdr;
+ u8 mesh_cfg_opcode;
+ u8 enable_beaconing;
+ u8 mbca_config;
+ u8 min_beacon_gap_ms;
+ __le16 mbss_start_scan_duration_ms;
+ __le16 tbtt_adj_timer_interval_ms;
+} __packed;
+
+struct host_cmd_req_set_offset_tsf {
+ struct host_cmd_header hdr;
+ __sle64 offset_tsf;
+} __packed;
+
+struct host_cmd_req_get_channel_usage {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_channel_usage {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le64 time_listen;
+ __le64 busy_time;
+ __le32 freq_hz;
+ s8 noise;
+ u8 bw_mhz;
+} __packed;
+
+#define HOST_CMD_MAX_MCAST_FILTERS 12
+
+struct host_cmd_req_mcast_filter {
+ struct host_cmd_header hdr;
+ u8 count;
+ __le32 hw_addr[];
+} __packed;
+
+struct host_cmd_req_bss_beacon_config {
+ struct host_cmd_header hdr;
+ u8 enable;
+} __packed;
+
+struct host_cmd_resp_bss_beacon_config {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le16 interface_id;
+} __packed;
+
+struct host_cmd_req_uapsd_config {
+ struct host_cmd_header hdr;
+ u8 auto_trigger_enabled;
+ __le32 auto_trigger_timeout;
+} __packed;
+
+struct host_cmd_resp_uapsd_config {
+ struct host_cmd_header hdr;
+ __le32 status;
+ u8 auto_trigger_enabled;
+} __packed;
+
+struct host_cmd_req_page_slicing_config {
+ struct host_cmd_header hdr;
+ u8 enable;
+} __packed;
+
+#define HOST_CMD_HW_SCAN_FLAGS_START BIT(0)
+#define HOST_CMD_HW_SCAN_FLAGS_ABORT BIT(1)
+#define HOST_CMD_HW_SCAN_FLAGS_SURVEY BIT(2)
+#define HOST_CMD_HW_SCAN_FLAGS_STORE BIT(3)
+#define HOST_CMD_HW_SCAN_FLAGS_1MHZ_PROBES BIT(4)
+#define HOST_CMD_HW_SCAN_FLAGS_SCHED_START BIT(5)
+#define HOST_CMD_HW_SCAN_FLAGS_SCHED_STOP BIT(6)
+#define HOST_CMD_HW_SCAN_FLAGS_PROBE_ON_DOZE_BEACON BIT(7)
+
+enum host_cmd_hw_scan_tlv_tag {
+ HOST_CMD_HW_SCAN_TLV_TAG_PAD = 0,
+ HOST_CMD_HW_SCAN_TLV_TAG_PROBE_REQ = 1,
+ HOST_CMD_HW_SCAN_TLV_TAG_CHAN_LIST = 2,
+ HOST_CMD_HW_SCAN_TLV_TAG_POWER_LIST = 3,
+ HOST_CMD_HW_SCAN_TLV_TAG_DWELL_ON_HOME = 4,
+ HOST_CMD_HW_SCAN_TLV_TAG_SCHED = 5,
+ HOST_CMD_HW_SCAN_TLV_TAG_FILTER = 6,
+ HOST_CMD_HW_SCAN_TLV_TAG_SCHED_PARAMS = 7,
+};
+
+struct host_cmd_hw_scan_tlv {
+ __le16 tag;
+ __le16 len;
+ u8 value[];
+} __packed;
+
+struct host_cmd_req_hw_scan {
+ struct host_cmd_header hdr;
+ __le32 flags;
+ __le32 dwell_time_ms;
+ u8 variable[];
+} __packed;
+
+#define HOST_CMD_WHITELIST_FLAGS_CLEAR BIT(0)
+
+struct host_cmd_req_set_whitelist {
+ struct host_cmd_header hdr;
+ u8 flags;
+ u8 ip_protocol;
+ __be16 llc_protocol;
+ __be32 src_ip;
+ __be32 dest_ip;
+ __be32 netmask;
+ __be16 src_port;
+ __be16 dest_port;
+} __packed;
+
+struct host_cmd_arp_periodic_params {
+ __le32 refresh_period_s;
+ __le32 destination_ip;
+ u8 send_as_garp;
+} __packed;
+
+struct host_cmd_req_arp_periodic_refresh {
+ struct host_cmd_header hdr;
+ struct host_cmd_arp_periodic_params config;
+} __packed;
+
+#define HOST_CMD_TCP_KEEPALIVE_SET_CFG_PERIOD BIT(0)
+#define HOST_CMD_TCP_KEEPALIVE_SET_CFG_RETRY_COUNT BIT(1)
+#define HOST_CMD_TCP_KEEPALIVE_SET_CFG_RETRY_INTERVAL BIT(2)
+#define HOST_CMD_TCP_KEEPALIVE_SET_CFG_SRC_IP_ADDR BIT(3)
+#define HOST_CMD_TCP_KEEPALIVE_SET_CFG_DEST_IP_ADDR BIT(4)
+#define HOST_CMD_TCP_KEEPALIVE_SET_CFG_SRC_PORT BIT(5)
+#define HOST_CMD_TCP_KEEPALIVE_SET_CFG_DEST_PORT BIT(6)
+
+struct host_cmd_req_set_tcp_keepalive {
+ struct host_cmd_header hdr;
+ u8 enabled;
+ u8 retry_count;
+ u8 retry_interval_s;
+ u8 set_cfgs;
+ __be32 src_ip;
+ __be32 dest_ip;
+ __be16 src_port;
+ __be16 dest_port;
+ __le16 period_s;
+} __packed;
+
+enum host_cmd_power_mode {
+ HOST_CMD_POWER_MODE_SNOOZE = 0,
+ HOST_CMD_POWER_MODE_DEEP_SLEEP = 1,
+ HOST_CMD_POWER_MODE_HIBERNATE = 2,
+};
+
+struct host_cmd_req_force_power_mode {
+ struct host_cmd_header hdr;
+ __le32 mode;
+} __packed;
+
+struct host_cmd_req_li_sleep {
+ struct host_cmd_header hdr;
+ __le32 listen_interval;
+} __packed;
+
+struct host_cmd_disabled_channel_entry {
+ __le16 freq_100khz;
+ u8 bw_mhz;
+} __packed;
+
+struct host_cmd_resp_get_disabled_channels {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 n_channels;
+ struct host_cmd_disabled_channel_entry channels[];
+} __packed;
+
+struct host_cmd_req_set_cqm_rssi {
+ struct host_cmd_header hdr;
+ __sle32 threshold;
+ __le32 hysteresis;
+} __packed;
+
+struct host_cmd_req_get_apf_capabilities {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_apf_capabilities {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 max_length;
+ u8 version;
+} __packed;
+
+struct host_cmd_req_read_write_apf {
+ struct host_cmd_header hdr;
+ __le32 offset;
+ __le16 program_length;
+ u8 write;
+ u8 program[];
+} __packed;
+
+struct host_cmd_resp_read_write_apf {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le16 program_length;
+ u8 program[];
+} __packed;
+
+struct host_cmd_req_bssid_set {
+ struct host_cmd_header hdr;
+ struct host_cmd_mac_addr bssid;
+} __packed;
+
+#define HOST_CMD_BEACON_OFFLOAD_FLAGS_START BIT(0)
+#define HOST_CMD_BEACON_OFFLOAD_FLAGS_STOP BIT(1)
+#define HOST_CMD_BEACON_OFFLOAD_CSSID_LEN 4
+
+enum host_cmd_beacon_offload_tlv_tag {
+ HOST_CMD_BEACON_OFFLOAD_TLV_TAG_DTIM_CNT = 0,
+ HOST_CMD_BEACON_OFFLOAD_TLV_TAG_FRAME_CTRL = 1,
+ HOST_CMD_BEACON_OFFLOAD_TLV_TAG_CHANGE_SEQ = 2,
+ HOST_CMD_BEACON_OFFLOAD_TLV_TAG_CSSID = 3,
+ HOST_CMD_BEACON_OFFLOAD_TLV_TAG_IES = 4,
+ HOST_CMD_BEACON_OFFLOAD_TLV_TAG_TX_INFO = 5,
+};
+
+struct host_cmd_beacon_offload_tlv_hdr {
+ __le16 tag;
+ __le16 len;
+} __packed;
+
+struct host_cmd_beacon_offload_tlv_generic {
+ struct host_cmd_beacon_offload_tlv_hdr hdr;
+ u8 value[];
+} __packed;
+
+struct host_cmd_beacon_offload_tlv_dtim_cnt {
+ struct host_cmd_beacon_offload_tlv_hdr hdr;
+ __le16 dtim_cnt;
+} __packed;
+
+struct host_cmd_beacon_offload_tlv_frame_ctrl {
+ struct host_cmd_beacon_offload_tlv_hdr hdr;
+ u8 frame_ctrl[2];
+} __packed;
+
+struct host_cmd_beacon_offload_tlv_change_seq {
+ struct host_cmd_beacon_offload_tlv_hdr hdr;
+ __le16 change_seq;
+} __packed;
+
+struct host_cmd_beacon_offload_tlv_tx_info {
+ struct host_cmd_beacon_offload_tlv_hdr hdr;
+ u8 bw_mhz;
+} __packed;
+
+struct host_cmd_beacon_offload_tlv_cssid {
+ struct host_cmd_beacon_offload_tlv_hdr hdr;
+ u8 cssid[HOST_CMD_BEACON_OFFLOAD_CSSID_LEN];
+} __packed;
+
+struct host_cmd_beacon_offload_tlv_ies {
+ struct host_cmd_beacon_offload_tlv_hdr hdr;
+ u8 buf[];
+} __packed;
+
+struct host_cmd_req_beacon_offload {
+ struct host_cmd_header hdr;
+ __le32 flags;
+ u8 variable[];
+} __packed;
+
+struct host_cmd_resp_beacon_offload {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le16 dtim_count;
+} __packed;
+
+struct host_cmd_req_probe_response_offload {
+ struct host_cmd_header hdr;
+ u8 enable;
+ __le16 probe_resp_len;
+ u8 probe_resp_buf[];
+} __packed;
+
+struct host_cmd_resp_probe_response_offload {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_sta_type {
+ struct host_cmd_header hdr;
+ u8 sta_type;
+} __packed;
+
+struct host_cmd_req_set_enc_mode {
+ struct host_cmd_header hdr;
+ u8 enc_mode;
+} __packed;
+
+struct host_cmd_req_test_ba {
+ struct host_cmd_header hdr;
+ u8 addr[HOST_CMD_MAC_ADDR_LEN];
+ u8 start;
+ u8 tx;
+ __le32 tid;
+} __packed;
+
+struct host_cmd_req_set_listen_interval {
+ struct host_cmd_header hdr;
+ __le16 listen_interval;
+} __packed;
+
+struct host_cmd_req_set_ampdu {
+ struct host_cmd_header hdr;
+ u8 ampdu_enabled;
+} __packed;
+
+struct host_cmd_req_set_s1g_op_class {
+ struct host_cmd_header hdr;
+ u8 opclass;
+ u8 prim_opclass;
+} __packed;
+
+struct host_cmd_req_send_wake_action_frame {
+ struct host_cmd_header hdr;
+ u8 dest_addr[HOST_CMD_MAC_ADDR_LEN];
+ __le32 payload_size;
+ u8 payload[];
+} __packed;
+
+#define HOST_CMD_MAX_VENDOR_IE_LENGTH 255
+#define HOST_CMD_VENDOR_IE_TYPE_FLAG_BEACON BIT(0)
+#define HOST_CMD_VENDOR_IE_TYPE_FLAG_PROBE_REQ BIT(1)
+#define HOST_CMD_VENDOR_IE_TYPE_FLAG_PROBE_RESP BIT(2)
+#define HOST_CMD_VENDOR_IE_TYPE_FLAG_ASSOC_REQ BIT(3)
+#define HOST_CMD_VENDOR_IE_TYPE_FLAG_ASSOC_RESP BIT(4)
+
+enum host_cmd_vendor_ie_op {
+ HOST_CMD_VENDOR_IE_OP_ADD_ELEMENT = 0,
+ HOST_CMD_VENDOR_IE_OP_CLEAR_ELEMENTS = 1,
+ HOST_CMD_VENDOR_IE_OP_ADD_FILTER = 2,
+ HOST_CMD_VENDOR_IE_OP_CLEAR_FILTERS = 3,
+ HOST_CMD_VENDOR_IE_OP_INVALID = U16_MAX,
+};
+
+struct host_cmd_req_vendor_ie_config {
+ struct host_cmd_header hdr;
+ __le16 opcode;
+ __le16 mgmt_type_mask;
+ u8 data[HOST_CMD_MAX_VENDOR_IE_LENGTH];
+} __packed;
+
+struct host_cmd_resp_vendor_ie_config {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+enum host_cmd_twt_conf_op {
+ HOST_CMD_TWT_CONF_OP_CONFIGURE = 0,
+ HOST_CMD_TWT_CONF_OP_FORCE_INSTALL_AGREEMENT = 1,
+ HOST_CMD_TWT_CONF_OP_REMOVE_AGREEMENT = 2,
+ HOST_CMD_TWT_CONF_OP_CONFIGURE_EXPLICIT = 3,
+};
+
+struct host_cmd_explicit_twt_wake_interval {
+ __le16 wake_interval_mantissa;
+ u8 wake_interval_exponent;
+ u8 __padding[5];
+} __packed;
+
+union host_cmd_wake_interval {
+ __le64 wake_interval_us;
+ struct host_cmd_explicit_twt_wake_interval explicit_twt;
+} __packed;
+
+struct host_cmd_req_set_twt_conf {
+ struct host_cmd_header hdr;
+ u8 opcode;
+ u8 flow_id;
+ __le64 target_wake_time;
+ union host_cmd_wake_interval wake_interval;
+ __le32 wake_duration_us;
+ u8 twt_setup_command;
+ u8 __padding[3];
+} __packed;
+
+#define HOST_CMD_MAX_AVAILABLE_CHANNELS 255
+
+struct host_cmd_channel_info {
+ __le32 frequency_khz;
+ u8 channel_5g;
+ u8 channel_s1g;
+ u8 bandwidth_mhz;
+} __packed;
+
+struct host_cmd_resp_get_available_channels {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 num_channels;
+ struct host_cmd_channel_info channels[HOST_CMD_MAX_AVAILABLE_CHANNELS];
+} __packed;
+
+#define HOST_CMD_S1G_CAP0_S1G_LONG BIT(0)
+#define HOST_CMD_S1G_CAP0_SGI_1MHZ BIT(1)
+#define HOST_CMD_S1G_CAP0_SGI_2MHZ BIT(2)
+#define HOST_CMD_S1G_CAP0_SGI_4MHZ BIT(3)
+#define HOST_CMD_S1G_CAP0_SGI_8MHZ BIT(4)
+#define HOST_CMD_S1G_CAP0_SGI_16MHZ BIT(5)
+
+struct host_cmd_req_set_ecsa_s1g_info {
+ struct host_cmd_header hdr;
+ __le32 operating_channel_freq_hz;
+ u8 opclass;
+ u8 primary_channel_bw_mhz;
+ u8 prim_1mhz_ch_idx;
+ u8 operating_channel_bw_mhz;
+ u8 prim_opclass;
+ u8 s1g_cap0;
+ u8 s1g_cap1;
+ u8 s1g_cap2;
+ u8 s1g_cap3;
+} __packed;
+
+struct host_cmd_resp_get_hw_version {
+ struct host_cmd_header hdr;
+ __le32 status;
+ u8 hw_version[64];
+} __packed;
+
+#define HOST_CMD_CAC_CFG_CHANGE_RULE_MAX 8
+#define HOST_CMD_CAC_CFG_ARFS_MAX 99
+#define HOST_CMD_CAC_CFG_CHANGE_MAX 99
+#define HOST_CMD_CAC_CFG_CHANGE_STEP 5
+
+enum host_cmd_cac_op {
+ HOST_CMD_CAC_OP_DISABLE = 0,
+ HOST_CMD_CAC_OP_ENABLE = 1,
+ HOST_CMD_CAC_OP_CFG_GET = 2,
+ HOST_CMD_CAC_OP_CFG_SET = 3,
+};
+
+struct host_cmd_cac_change_rule {
+ __le16 arfs;
+ __sle16 threshold_change;
+} __packed;
+
+struct host_cmd_req_cac {
+ struct host_cmd_header hdr;
+ u8 opcode;
+ u8 rule_tot;
+ struct host_cmd_cac_change_rule rule[HOST_CMD_CAC_CFG_CHANGE_RULE_MAX];
+} __packed;
+
+struct host_cmd_resp_cac {
+ struct host_cmd_header hdr;
+ __le32 status;
+ u8 rule_tot;
+ struct host_cmd_cac_change_rule rule[HOST_CMD_CAC_CFG_CHANGE_RULE_MAX];
+} __packed;
+
+struct host_cmd_ocs_driver_req {
+ __le32 op_channel_freq_hz;
+ u8 op_channel_bw_mhz;
+ u8 pri_channel_bw_mhz;
+ u8 pri_1mhz_channel_index;
+} __packed;
+
+struct host_cmd_ocs_driver_resp {
+ u8 running;
+} __packed;
+
+struct host_cmd_req_ocs_driver {
+ struct host_cmd_header hdr;
+ __le32 subcmd;
+ union {
+ u8 opaque[0];
+ struct host_cmd_ocs_driver_req config;
+ };
+} __packed;
+
+struct host_cmd_resp_ocs_driver {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 subcmd;
+ union {
+ u8 opaque[0];
+ struct host_cmd_ocs_driver_resp ocs_status;
+ };
+} __packed;
+
+#define HOST_CMD_IFNAMSIZ 16
+
+struct host_cmd_req_mbssid {
+ struct host_cmd_header hdr;
+ u8 max_bssid_indicator;
+ s8 transmitter_iface[HOST_CMD_IFNAMSIZ];
+} __packed;
+
+#define HOST_CMD_MESH_ID_LEN_MAX 32
+#define HOST_CMD_MESH_BEACONLESS_MODE_DISABLE 0
+#define HOST_CMD_MESH_BEACONLESS_MODE_ENABLE 1
+#define HOST_CMD_MESH_PEER_LINKS_MIN 0
+#define HOST_CMD_MESH_PEER_LINKS_MAX 20
+
+struct host_cmd_req_set_mesh_config {
+ struct host_cmd_header hdr;
+ u8 mesh_id_len;
+ u8 mesh_id[HOST_CMD_MESH_ID_LEN_MAX];
+ u8 mesh_beaconless_mode;
+ u8 max_plinks;
+} __packed;
+
+struct host_cmd_req_set_mcba_conf {
+ struct host_cmd_header hdr;
+ u8 mbca_config;
+ u8 beacon_timing_report_interval;
+ u8 min_beacon_gap_ms;
+ __le16 mbss_start_scan_duration_ms;
+ __le16 tbtt_adj_interval_ms;
+} __packed;
+
+struct host_cmd_req_dynamic_peering_config {
+ struct host_cmd_header hdr;
+ u8 enabled;
+ u8 rssi_margin;
+ __le32 blacklist_timeout;
+} __packed;
+
+#define HOST_CMD_CFG_RAW_FLAG_ENABLE BIT(0)
+#define HOST_CMD_CFG_RAW_FLAG_DELETE BIT(1)
+#define HOST_CMD_CFG_RAW_FLAG_UPDATE BIT(2)
+#define HOST_CMD_CFG_RAW_FLAG_DYNAMIC BIT(3)
+#define HOST_CMD_RAW_RESERVED_AID_DCS 2008
+#define HOST_CMD_RAW_RESERVED_AID_DOWNLINK 2009
+
+enum host_cmd_raw_tlv_tag {
+ HOST_CMD_RAW_TLV_TAG_SLOT_DEF = 0,
+ HOST_CMD_RAW_TLV_TAG_GROUP = 1,
+ HOST_CMD_RAW_TLV_TAG_START_TIME = 2,
+ HOST_CMD_RAW_TLV_TAG_PRAW = 3,
+ HOST_CMD_RAW_TLV_TAG_BCN_SPREAD = 4,
+ HOST_CMD_RAW_TLV_TAG_DYN_GLOBAL = 5,
+ HOST_CMD_RAW_TLV_TAG_DYN_CONFIG = 6,
+ HOST_CMD_RAW_TLV_TAG_LAST = 7,
+};
+
+struct host_cmd_raw_tlv_slot_def {
+ u8 tag;
+ __le32 raw_duration_us;
+ u8 num_slots;
+ u8 cross_slot_bleed;
+} __packed;
+
+struct host_cmd_raw_tlv_group {
+ u8 tag;
+ __le16 aid_start;
+ __le16 aid_end;
+} __packed;
+
+struct host_cmd_raw_tlv_start_time {
+ u8 tag;
+ __le32 start_time_us;
+} __packed;
+
+struct host_cmd_raw_tlv_praw {
+ u8 tag;
+ u8 periodicity;
+ u8 validity;
+ u8 start_offset;
+ u8 refresh_on_expiry;
+} __packed;
+
+struct host_cmd_raw_tlv_bcn_spread {
+ u8 tag;
+ __le16 max_spread;
+ __le16 nominal_sta_per_bcn;
+} __packed;
+
+struct host_cmd_raw_tlv_dyn_global {
+ u8 tag;
+ __le16 num_configs;
+ __le16 num_bcn_indexes;
+} __packed;
+
+struct host_cmd_raw_tlv_dyn_config {
+ u8 tag;
+ __le16 id;
+ __le16 index;
+ __le16 len;
+ u8 variable[];
+} __packed;
+
+union host_cmd_raw_tlvs {
+ u8 tag;
+ struct host_cmd_raw_tlv_slot_def slot_def;
+ struct host_cmd_raw_tlv_group group;
+ struct host_cmd_raw_tlv_start_time start_time;
+ struct host_cmd_raw_tlv_praw praw;
+ struct host_cmd_raw_tlv_bcn_spread bcn_spread;
+ struct host_cmd_raw_tlv_dyn_global dyn_global;
+ struct host_cmd_raw_tlv_dyn_config dyn_config;
+} __packed;
+
+struct host_cmd_req_config_raw {
+ struct host_cmd_header hdr;
+ __le32 flags;
+ __le16 id;
+ u8 variable[];
+} __packed;
+
+struct host_cmd_req_config_bss_stats {
+ struct host_cmd_header hdr;
+ u8 enable;
+ __le32 monitor_window_ms;
+} __packed;
+
+struct host_cmd_req_get_rssi {
+ struct host_cmd_header hdr;
+} __packed;
+
+struct host_cmd_resp_get_rssi {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __sle32 rssi0;
+ __sle32 rssi1;
+ __sle32 rssi2;
+ __sle32 rssi3;
+ __sle32 rssi4;
+ __sle32 rssi5;
+ __sle32 rssi6;
+ __sle32 rssi7;
+} __packed;
+
+#define HOST_CMD_SET_IFS_MIN_USECS 160
+
+struct host_cmd_req_set_ifs {
+ struct host_cmd_header hdr;
+ __le32 period_usecs;
+} __packed;
+
+struct host_cmd_resp_set_ifs {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_fem_settings {
+ struct host_cmd_header hdr;
+ __le32 tx_antenna;
+ __le32 rx_antenna;
+ __le32 lna_enabled;
+ __le32 pa_enabled;
+} __packed;
+
+struct host_cmd_resp_set_fem_settings {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_txop {
+ struct host_cmd_header hdr;
+ u8 min_packet_count;
+} __packed;
+
+struct host_cmd_resp_set_txop {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_control_response {
+ struct host_cmd_header hdr;
+ u8 direction;
+ u8 control_response_1mhz_en;
+} __packed;
+
+struct host_cmd_resp_set_control_response {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_periodic_cal {
+ struct host_cmd_header hdr;
+ __le32 periodic_cal_en_mask;
+} __packed;
+
+struct host_cmd_resp_set_periodic_cal {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_bcn_rssi_threshold {
+ struct host_cmd_header hdr;
+ u8 threshold_db;
+} __packed;
+
+struct host_cmd_resp_set_bcn_rssi_threshold {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_tx_pkt_lifetime_usecs {
+ struct host_cmd_header hdr;
+ __le32 lifetime_usecs;
+} __packed;
+
+struct host_cmd_resp_set_tx_pkt_lifetime_usecs {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_physm_watchdog {
+ struct host_cmd_header hdr;
+ u8 physm_watchdog_en;
+} __packed;
+
+struct host_cmd_req_tx_polar {
+ struct host_cmd_header hdr;
+ u8 enable;
+} __packed;
+
+struct host_cmd_evt_sta_state {
+ struct host_cmd_header hdr;
+ u8 sta_addr[HOST_CMD_MAC_ADDR_LEN];
+ __le16 aid;
+ __le16 state;
+} __packed;
+
+struct host_cmd_evt_beacon_loss {
+ struct host_cmd_header hdr;
+ __le32 num_bcns;
+} __packed;
+
+struct host_cmd_evt_sig_field_error {
+ struct host_cmd_header hdr;
+ __le64 start_timestamp;
+ __le64 end_timestamp;
+} __packed;
+
+#define HOST_CMD_UMAC_TRAFFIC_CONTROL_SOURCE_TWT BIT(0)
+#define HOST_CMD_UMAC_TRAFFIC_CONTROL_SOURCE_DUTY_CYCLE BIT(1)
+
+struct host_cmd_evt_umac_traffic_control {
+ struct host_cmd_header hdr;
+ u8 pause_data_traffic;
+ __le32 sources;
+} __packed;
+
+struct host_cmd_evt_dhcp_lease_update {
+ struct host_cmd_header hdr;
+ __le32 my_ip;
+ __le32 netmask;
+ __le32 router;
+ __le32 dns;
+} __packed;
+
+struct host_cmd_evt_ocs_done {
+ struct host_cmd_header hdr;
+ __le64 time_listen;
+ __le64 time_rx;
+ s8 noise;
+ u8 metric;
+} __packed;
+
+struct host_cmd_evt_hw_scan_done {
+ struct host_cmd_header hdr;
+ u8 aborted;
+} __packed;
+
+struct host_cmd_evt_channel_usage {
+ struct host_cmd_header hdr;
+ __le64 time_listen;
+ __le64 busy_time;
+ __le32 freq_hz;
+ u8 noise;
+ u8 bw_mhz;
+} __packed;
+
+enum host_cmd_connection_loss_reason {
+ HOST_CMD_CONNECTION_LOSS_REASON_TSF_RESET = 0,
+};
+
+struct host_cmd_evt_connection_loss {
+ struct host_cmd_header hdr;
+ __le32 reason;
+} __packed;
+
+struct host_cmd_evt_sched_scan_results {
+ struct host_cmd_header hdr;
+} __packed;
+
+enum host_cmd_cqm_rssi_threshold_event {
+ HOST_CMD_CQM_RSSI_THRESHOLD_EVENT_LOW = 0,
+ HOST_CMD_CQM_RSSI_THRESHOLD_EVENT_HIGH = 1,
+};
+
+struct host_cmd_evt_cqm_rssi_notify {
+ struct host_cmd_header hdr;
+ __sle16 rssi;
+ __le16 event;
+} __packed;
+
+struct host_cmd_evt_ndp_probe_request_received {
+ struct host_cmd_header hdr;
+ u8 rx_bw_mhz;
+ u8 is_pv1;
+} __packed;
+
+struct host_cmd_evt_scan_done {
+ struct host_cmd_header hdr;
+ u8 aborted;
+} __packed;
+
+enum host_cmd_scan_result_frame {
+ HOST_CMD_SCAN_RESULT_FRAME_UNKNOWN = 0,
+ HOST_CMD_SCAN_RESULT_FRAME_BEACON = 1,
+ HOST_CMD_SCAN_RESULT_FRAME_PROBE_RESPONSE = 2,
+};
+
+struct host_cmd_evt_scan_result {
+ struct host_cmd_header hdr;
+ __le32 channel_freq_hz;
+ u8 bw_mhz;
+ u8 frame_type;
+ __sle16 rssi;
+ u8 bssid[HOST_CMD_MAC_ADDR_LEN];
+ __le16 beacon_interval;
+ __le16 capability_info;
+ __le64 tsf;
+ __le16 ies_len;
+ u8 ies[];
+} __packed;
+
+struct host_cmd_evt_connected {
+ struct host_cmd_header hdr;
+ u8 bssid[HOST_CMD_MAC_ADDR_LEN];
+ __sle16 rssi;
+ u8 padding_0[8];
+ __le16 assoc_resp_ies_len;
+ u8 assoc_resp_ies[];
+} __packed;
+
+struct host_cmd_evt_beacon_filter_match {
+ struct host_cmd_header hdr;
+ u8 padding_0[4];
+ __le32 ies_len;
+ u8 ies[];
+} __packed;
+
+struct host_cmd_req_set_capabilities {
+ struct host_cmd_header hdr;
+ struct host_cmd_mm_capabilities capabilities;
+ u8 set_caps;
+ u8 morse_mmss_offset;
+} __packed;
+
+struct host_cmd_resp_set_capabilities {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+struct host_cmd_req_set_transmission_rate {
+ struct host_cmd_header hdr;
+ __sle32 mcs_index;
+ __sle32 bandwidth_mhz;
+ __sle32 tx_80211ah_format;
+ s8 use_traveling_pilots;
+ s8 use_sgi;
+ u8 enabled;
+ s8 nss_idx;
+ s8 use_ldpc;
+ s8 use_stbc;
+} __packed;
+
+struct host_cmd_resp_set_transmission_rate {
+ struct host_cmd_header hdr;
+ __le32 status;
+} __packed;
+
+enum host_cmd_hart_id {
+ HOST_CMD_HART_ID_HOST = 0,
+ HOST_CMD_HART_ID_MAC = 1,
+ HOST_CMD_HART_ID_UPHY = 2,
+ HOST_CMD_HART_ID_LPHY = 3,
+};
+
+struct host_cmd_req_force_assert {
+ struct host_cmd_header hdr;
+ __le32 hart_id;
+ __le32 delay;
+} __packed;
+
+#define HOST_CMD_HOST_BLOCK_TX_FRAMES BIT(0)
+#define HOST_CMD_HOST_BLOCK_TX_CMD BIT(1)
+
+enum host_cmd_param_action {
+ HOST_CMD_PARAM_ACTION_SET = 0,
+ HOST_CMD_PARAM_ACTION_GET = 1,
+ HOST_CMD_PARAM_ACTION_LAST = 2,
+};
+
+enum host_cmd_slow_clock_mode {
+ HOST_CMD_SLOW_CLOCK_MODE_AUTO = 0,
+ HOST_CMD_SLOW_CLOCK_MODE_INTERNAL = 1,
+};
+
+enum host_cmd_param_id {
+ HOST_CMD_PARAM_ID_MAX_TRAFFIC_DELIVERY_WAIT_US = 0,
+ HOST_CMD_PARAM_ID_EXTRA_ACK_TIMEOUT_ADJUST_US = 1,
+ HOST_CMD_PARAM_ID_TX_STATUS_FLUSH_WATERMARK = 2,
+ HOST_CMD_PARAM_ID_TX_STATUS_FLUSH_MIN_AMPDU_SIZE = 3,
+ HOST_CMD_PARAM_ID_POWERSAVE_TYPE = 4,
+ HOST_CMD_PARAM_ID_SNOOZE_DURATION_ADJUST_US = 5,
+ HOST_CMD_PARAM_ID_TX_BLOCK = 6,
+ HOST_CMD_PARAM_ID_FORCED_SNOOZE_PERIOD_US = 7,
+ HOST_CMD_PARAM_ID_WAKE_ACTION_GPIO = 8,
+ HOST_CMD_PARAM_ID_WAKE_ACTION_GPIO_PULSE_MS = 9,
+ HOST_CMD_PARAM_ID_CONNECTION_MONITOR_GPIO = 10,
+ HOST_CMD_PARAM_ID_INPUT_TRIGGER_GPIO = 11,
+ HOST_CMD_PARAM_ID_INPUT_TRIGGER_MODE = 12,
+ HOST_CMD_PARAM_ID_COUNTRY = 13,
+ HOST_CMD_PARAM_ID_RTS_THRESHOLD = 14,
+ HOST_CMD_PARAM_ID_HOST_TX_BLOCK = 15,
+ HOST_CMD_PARAM_ID_MEM_RETENTION_CODE = 16,
+ HOST_CMD_PARAM_ID_NON_TIM_MODE = 17,
+ HOST_CMD_PARAM_ID_DYNAMIC_PS_TIMEOUT_MS = 18,
+ HOST_CMD_PARAM_ID_HOME_CHANNEL_DWELL_MS = 19,
+ HOST_CMD_PARAM_ID_SLOW_CLOCK_MODE = 20,
+ HOST_CMD_PARAM_ID_FRAGMENT_THRESHOLD = 21,
+ HOST_CMD_PARAM_ID_BEACON_LOSS_COUNT = 22,
+ HOST_CMD_PARAM_ID_AP_POWER_SAVE = 23,
+ HOST_CMD_PARAM_ID_BEACON_OFFLOAD = 24,
+ HOST_CMD_PARAM_ID_PROBE_RESP_OFFLOAD = 25,
+ HOST_CMD_PARAM_ID_BSS_MAX_AWAY_DURATION = 26,
+ HOST_CMD_PARAM_ID_DEFAULT_ACTIVE_SCAN_DWELL_MS = 27,
+ HOST_CMD_PARAM_ID_CTS_TO_SELF = 28,
+ HOST_CMD_PARAM_ID_CHANNELIZATION = 29,
+ HOST_CMD_PARAM_ID_CRYPTO_IN_HOST = 30,
+ HOST_CMD_PARAM_ID_AUTOCONNECT = 31,
+ HOST_CMD_PARAM_ID_LAST = 32,
+};
+
+struct host_cmd_req_get_set_generic_param {
+ struct host_cmd_header hdr;
+ __le32 param_id;
+ __le32 action;
+ __le32 flags;
+ __le32 value;
+} __packed;
+
+struct host_cmd_resp_get_set_generic_param {
+ struct host_cmd_header hdr;
+ __le32 status;
+ __le32 flags;
+ __le32 value;
+} __packed;
+
+#endif
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 04/35] wifi: mm81x: add command.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
.../net/wireless/morsemicro/mm81x/command.h | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/command.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/command.h b/drivers/net/wireless/morsemicro/mm81x/command.h
new file mode 100644
index 000000000000..67c4f6962e85
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/command.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_COMMAND_H_
+#define _MM81X_COMMAND_H_
+
+#include <linux/skbuff.h>
+#include <linux/workqueue.h>
+#include "core.h"
+#include "command_defs.h"
+
+#define HOST_CMD_IS_REQ(cmd) (le16_to_cpu((cmd)->hdr.flags) & HOST_CMD_TYPE_REQ)
+#define HOST_CMD_IS_RESP(cmd) \
+ (le16_to_cpu((cmd)->hdr.flags) & HOST_CMD_TYPE_RESP)
+#define HOST_CMD_IS_EVT(cmd) (le16_to_cpu((cmd)->hdr.flags) & HOST_CMD_TYPE_EVT)
+
+struct mm81x_queue_params;
+
+enum mm81x_cmd_return_code {
+ MM81X_RET_SUCCESS = 0,
+ MM81X_RET_EPERM = -1,
+ MM81X_RET_ENOMEM = -12,
+ MM81X_RET_CMD_NOT_HANDLED = -32757,
+};
+
+#define HOST_CMD_HOST_ID_SEQ_MAX 0xFFF
+#define HOST_CMD_HOST_ID_RETRY_MASK 0x000F
+#define HOST_CMD_HOST_ID_SEQ_SHIFT 4
+#define HOST_CMD_HOST_ID_SEQ_MASK 0xFFF0
+
+struct host_cmd_req {
+ struct host_cmd_header hdr;
+ u8 data[];
+} __packed;
+
+struct host_cmd_resp {
+ struct host_cmd_header hdr;
+ __le32 status;
+ u8 data[];
+} __packed;
+
+struct host_cmd_event {
+ struct host_cmd_header hdr;
+ u8 data[];
+} __packed;
+
+int mm81x_cmd_resp_process(struct mm81x *mm, struct sk_buff *skb);
+int mm81x_cmd_add_if(struct mm81x *mm, u16 *vif_id, const u8 *addr,
+ enum nl80211_iftype type);
+int mm81x_cmd_get_capabilities(struct mm81x *mm, u16 vif_id,
+ struct mm81x_fw_caps *capabilities);
+int mm81x_cmd_cfg_qos(struct mm81x *mm, struct mm81x_queue_params *params);
+int mm81x_cmd_config_beacon_timer(struct mm81x *mm, void *mm81x_vif,
+ bool enabled);
+int mm81x_cmd_cfg_bss(struct mm81x *mm, u16 vif_id, u16 beacon_int,
+ u16 dtim_period, u32 cssid);
+int mm81x_cmd_set_channel(struct mm81x *mm, u32 op_chan_freq_hz,
+ u8 pri_1mhz_chan_idx, u8 op_bw_mhz, u8 pri_bw_mhz,
+ s32 *power_mbm);
+int mm81x_cmd_get_max_txpower(struct mm81x *mm, s32 *out_power_mbm);
+int mm81x_cmd_set_txpower(struct mm81x *mm, s32 *out_power_mbm,
+ int txpower_mbm);
+int mm81x_cmd_hw_scan(struct mm81x *mm, struct mm81x_hw_scan_params *params,
+ bool store);
+int mm81x_cmd_set_ps(struct mm81x *mm, bool enabled);
+int mm81x_cmd_cfg_multicast_filter(struct mm81x *mm, struct mm81x_vif *mm_vif);
+int mm81x_cmd_sta_state(struct mm81x *mm, struct mm81x_vif *mm_vif, u16 aid,
+ struct ieee80211_sta *sta,
+ enum ieee80211_sta_state state);
+int mm81x_cmd_install_key(struct mm81x *mm, struct mm81x_vif *mm_vif, u16 aid,
+ struct ieee80211_key_conf *key,
+ enum host_cmd_key_cipher cipher,
+ enum host_cmd_aes_key_len length);
+int mm81x_cmd_disable_key(struct mm81x *mm, struct mm81x_vif *mm_vif, u16 aid,
+ struct ieee80211_key_conf *key);
+int mm81x_cmd_rm_if(struct mm81x *mm, u16 vif_id);
+int mm81x_cmd_set_frag_threshold(struct mm81x *mm, u32 frag_threshold);
+int mm81x_cmd_get_disabled_channels(
+ struct mm81x *mm, struct host_cmd_resp_get_disabled_channels *resp,
+ uint resp_len);
+
+#endif /* !_MM81X_COMMAND_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 05/35] wifi: mm81x: add core.c
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/core.c | 157 +++++++++++++++++++
1 file changed, 157 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/core.c
diff --git a/drivers/net/wireless/morsemicro/mm81x/core.c b/drivers/net/wireless/morsemicro/mm81x/core.c
new file mode 100644
index 000000000000..1bcb9b5a00c9
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/core.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+#include <linux/module.h>
+#include "core.h"
+#include "debug.h"
+#include "bus.h"
+#include "hif.h"
+
+unsigned int mm81x_debug_mask;
+module_param_named(debug_mask, mm81x_debug_mask, uint, 0644);
+MODULE_PARM_DESC(debug_mask, "mm81x debug mask");
+
+char board_config_file[BCF_SIZE_MAX] = "";
+module_param_string(bcf, board_config_file, sizeof(board_config_file), 0644);
+MODULE_PARM_DESC(bcf, "BCF filename to load");
+
+int mm81x_core_attach_regs(struct mm81x *mm)
+{
+ int ret = 0;
+
+ mm81x_claim_bus(mm);
+ ret = mm81x_reg32_read(mm, MM8108_REG_CHIP_ID, &mm->chip_id);
+ mm81x_release_bus(mm);
+
+ if (ret < 0) {
+ mm81x_err(mm, "failed to read chip id %d", ret);
+ return ret;
+ }
+
+ switch (mm->chip_id) {
+ case (MM8108B2_ID):
+ mm->regs = &mm8108_regs;
+ mm->hif.ops = &mm81x_yaps_ops;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ return ret;
+}
+
+static char *mm81x_core_get_revision_string(u32 chip_id)
+{
+ u8 chip_rev = MM81X_DEVICE_GET_CHIP_REV(chip_id);
+
+ switch (chip_rev) {
+ case MM8108B2_REV:
+ return MM8108B2_REV_STRING;
+ default:
+ return "??";
+ }
+}
+
+void mm81x_core_init_mac_addr(struct mm81x *mm)
+{
+ int ret = mm81x_hw_otp_get_mac_addr(mm);
+
+ if (ret || !is_valid_ether_addr(mm->macaddr))
+ eth_random_addr(mm->macaddr);
+}
+
+char *mm81x_core_get_fw_path(u32 chip_id)
+{
+ return kasprintf(GFP_KERNEL,
+ MM81X_FW_DIR "/" MM8108_FW_BASE
+ "%s" FW_ROM_LINKED_STRING MM81X_FW_EXT,
+ mm81x_core_get_revision_string(chip_id));
+}
+
+int mm81x_core_create(struct mm81x *mm)
+{
+ int ret;
+
+ set_bit(MM81X_STATE_CHIP_UNRESPONSIVE, &mm->state_flags);
+ set_bit(MM81X_STATE_RELOAD_FW_AFTER_START, &mm->state_flags);
+
+ mm->chip_wq = create_singlethread_workqueue("chip_wq");
+ if (!mm->chip_wq) {
+ mm81x_err(mm, "create_singlethread_workqueue failed");
+ return -ENOMEM;
+ }
+
+ mm->net_wq = create_singlethread_workqueue("net_wq");
+ if (!mm->net_wq) {
+ mm81x_err(mm, "create_singlethread_workqueue failed");
+ ret = -ENOMEM;
+ goto err_chip_wq;
+ }
+
+ ret = mm81x_hif_init(mm);
+ if (ret) {
+ mm81x_err(mm, "mm81x_hif_init failed: %d", ret);
+ goto err_wqs;
+ }
+
+ return 0;
+
+err_wqs:
+ flush_workqueue(mm->net_wq);
+ destroy_workqueue(mm->net_wq);
+
+err_chip_wq:
+ flush_workqueue(mm->chip_wq);
+ destroy_workqueue(mm->chip_wq);
+
+ return ret;
+}
+
+void mm81x_core_destroy(struct mm81x *mm)
+{
+ mm81x_hif_finish(mm);
+ flush_workqueue(mm->net_wq);
+ destroy_workqueue(mm->net_wq);
+ flush_workqueue(mm->chip_wq);
+ destroy_workqueue(mm->chip_wq);
+}
+
+static int __init mm81x_init(void)
+{
+ int ret = 0;
+
+ pr_info("Morse Micro mm81x driver registration. Version %s\n",
+ DRV_VERSION);
+
+#ifdef CONFIG_MM81X_USB
+ ret = mm81x_usb_init();
+ if (ret)
+ pr_err("mm81x_usb_init() failed: %d\n", ret);
+#endif
+#ifdef CONFIG_MM81X_SDIO
+ ret = mm81x_sdio_init();
+ if (ret)
+ pr_err("mm81x_sdio_init() failed: %d\n", ret);
+#endif
+
+ return ret;
+}
+
+static void __exit mm81x_exit(void)
+{
+#ifdef CONFIG_MM81X_USB
+ mm81x_usb_exit();
+#endif
+#ifdef CONFIG_MM81X_SDIO
+ mm81x_sdio_exit();
+#endif
+}
+
+module_init(mm81x_init);
+module_exit(mm81x_exit);
+
+MODULE_AUTHOR("Morse Micro");
+MODULE_DESCRIPTION("Driver support for Morse Micro MM81X SDIO/USB devices");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_VERSION("1.0");
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 06/35] wifi: mm81x: add core.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/core.h | 499 +++++++++++++++++++
1 file changed, 499 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/core.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/core.h b/drivers/net/wireless/morsemicro/mm81x/core.h
new file mode 100644
index 000000000000..1cd079985ed7
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/core.h
@@ -0,0 +1,499 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_CORE_H_
+#define _MM81X_CORE_H_
+
+#include <net/mac80211.h>
+#include <linux/workqueue.h>
+#include <linux/interrupt.h>
+#include <linux/kfifo.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/crc32.h>
+#include <linux/notifier.h>
+#include <linux/nospec.h>
+#include "yaps.h"
+#include "yaps_hw.h"
+#include "hw.h"
+#include "fw.h"
+#include "rc.h"
+
+#define MM81X_DRIVER_SEMVER_MAJOR 56
+#define MM81X_DRIVER_SEMVER_MINOR 3
+#define MM81X_DRIVER_SEMVER_PATCH 0
+
+#define MM81X_SEMVER_GET_MAJOR(x) (((x) >> 22) & 0x3FF)
+#define MM81X_SEMVER_GET_MINOR(x) (((x) >> 10) & 0xFFF)
+#define MM81X_SEMVER_GET_PATCH(x) ((x) & 0x3FF)
+
+#define DRV_VERSION __stringify(MM81X_VERSION)
+
+#define MM8108_FW_BASE "mm8108"
+
+#define BCF_SIZE_MAX 48
+
+/* Generate a device ID from chip ID, revision, and chip type */
+#define MM81X_DEVICE_ID(chip_id, chip_rev, chip_type) \
+ ((chip_id) | ((chip_rev) << 8) | ((chip_type) << 12))
+
+/* Get constituents of the device ID */
+#define MM81X_DEVICE_GET_CHIP_ID(device_id) ((device_id) & 0xff)
+#define MM81X_DEVICE_GET_CHIP_REV(device_id) ((((device_id) >> 8) & 0xf))
+#define MM81X_DEVICE_GET_CHIP_TYPE(device_id) ((((device_id) >> 12) & 0xf))
+
+#define KHZ_TO_HZ(x) ((x) * 1000)
+#define KHZ100_TO_MHZ(x) ((x) / 10)
+#define KHZ100_TO_KHZ(freq) ((freq) * 100)
+#define KHZ100_TO_HZ(freq) ((freq) * 100000)
+
+#define QDBM_TO_MBM(gain) (((gain) * 100) >> 2)
+#define MBM_TO_QDBM(gain) (((gain) << 2) / 100)
+#define QDBM_TO_DBM(gain) ((gain) / 4)
+
+#define BPS_TO_KBPS(x) ((x) / 1000)
+
+#define UNUSED(x) ((void)x)
+
+#define NSS_IDX_TO_NSS(x) ((x) + 1)
+#define NSS_TO_NSS_IDX(x) ((x) - 1)
+
+#define ROUND_BYTES_TO_WORD(_nbytes) \
+ (((_nbytes) + 3) & ~((typeof(_nbytes))0x03))
+
+static inline u32 mm81x_fle32_to_cpu(u32 v)
+{
+ return le32_to_cpu((__force __le32)v);
+}
+
+static inline u16 mm81x_fle16_to_cpu(u16 v)
+{
+ return le16_to_cpu((__force __le16)v);
+}
+
+struct mm81x_bus_ops;
+struct mm81x_hif_ops;
+
+/* modparam variables */
+extern char board_config_file[];
+
+#define MM81X_CAPS_MAX_FW_VAL (128)
+
+/* Max number of interfaces */
+#define MM81X_MAX_IF (2)
+
+enum mm81x_caps_flags {
+ MM81X_CAPS_FW_START = 0,
+ MM81X_CAPS_2MHZ = MM81X_CAPS_FW_START,
+ MM81X_CAPS_4MHZ,
+ MM81X_CAPS_8MHZ,
+ MM81X_CAPS_16MHZ,
+ MM81X_CAPS_SGI,
+ MM81X_CAPS_S1G_LONG,
+ MM81X_CAPS_TRAVELING_PILOT_ONE_STREAM,
+ MM81X_CAPS_TRAVELING_PILOT_TWO_STREAM,
+ MM81X_CAPS_MU_BEAMFORMEE,
+ MM81X_CAPS_MU_BEAMFORMER,
+ MM81X_CAPS_RD_RESPONDER,
+ MM81X_CAPS_STA_TYPE_SENSOR,
+ MM81X_CAPS_STA_TYPE_NON_SENSOR,
+ MM81X_CAPS_GROUP_AID,
+ MM81X_CAPS_NON_TIM,
+ MM81X_CAPS_TIM_ADE,
+ MM81X_CAPS_BAT,
+ MM81X_CAPS_DYNAMIC_AID,
+ MM81X_CAPS_UPLINK_SYNC,
+ MM81X_CAPS_FLOW_CONTROL,
+ MM81X_CAPS_AMPDU,
+ MM81X_CAPS_AMSDU,
+ MM81X_CAPS_1MHZ_CONTROL_RESPONSE_PREAMBLE,
+ MM81X_CAPS_PAGE_SLICING,
+ MM81X_CAPS_RAW,
+ MM81X_CAPS_MCS8,
+ MM81X_CAPS_MCS9,
+ MM81X_CAPS_ASYMMETRIC_BA_SUPPORT,
+ MM81X_CAPS_DAC,
+ MM81X_CAPS_CAC,
+ MM81X_CAPS_TXOP_SHARING_IMPLICIT_ACK,
+ MM81X_CAPS_NDP_PSPOLL,
+ MM81X_CAPS_FRAGMENT_BA,
+ MM81X_CAPS_OBSS_MITIGATION,
+ MM81X_CAPS_TMP_PS_MODE_SWITCH,
+ MM81X_CAPS_SECTOR_TRAINING,
+ MM81X_CAPS_UNSOLICIT_DYNAMIC_AID,
+ MM81X_CAPS_NDP_BEAMFORMING_REPORT,
+ MM81X_CAPS_MCS_NEGOTIATION,
+ MM81X_CAPS_DUPLICATE_1MHZ,
+ MM81X_CAPS_TACK_AS_PSPOLL,
+ MM81X_CAPS_PV1,
+ MM81X_CAPS_TWT_RESPONDER,
+ MM81X_CAPS_TWT_REQUESTER,
+ MM81X_CAPS_BDT,
+ MM81X_CAPS_TWT_GROUPING,
+ MM81X_CAPS_LINK_ADAPTATION_WO_NDP_CMAC,
+ MM81X_CAPS_LONG_MPDU,
+ MM81X_CAPS_TXOP_SECTORIZATION,
+ MM81X_CAPS_GROUP_SECTORIZATION,
+ MM81X_CAPS_HTC_VHT,
+ MM81X_CAPS_HTC_VHT_MFB,
+ MM81X_CAPS_HTC_VHT_MRQ,
+ MM81X_CAPS_2SS,
+ MM81X_CAPS_3SS,
+ MM81X_CAPS_4SS,
+ MM81X_CAPS_SU_BEAMFORMEE,
+ MM81X_CAPS_SU_BEAMFORMER,
+ MM81X_CAPS_RX_STBC,
+ MM81X_CAPS_TX_STBC,
+ MM81X_CAPS_RX_LDPC,
+ MM81X_CAPS_HW_FRAGMENT,
+
+ MM81X_CAPS_FW_END = MM81X_CAPS_MAX_FW_VAL,
+ MM81X_CAPS_LAST = MM81X_CAPS_FW_END,
+};
+
+struct mm81x_fw_caps {
+ u32 flags[FW_CAPABILITIES_FLAGS_WIDTH];
+ u8 ampdu_mss;
+ u8 beamformee_sts_capability;
+ u8 number_sounding_dimensions;
+ u8 maximum_ampdu_length_exponent;
+ u8 mm81x_mmss_offset;
+};
+
+#define MM81X_FW_SUPP(MM81X_CAPS, CAPABILITY) \
+ mm81x_caps_supported(MM81X_CAPS, MM81X_CAPS_##CAPABILITY)
+
+static inline bool mm81x_caps_supported(struct mm81x_fw_caps *caps,
+ enum mm81x_caps_flags flag)
+{
+ const unsigned long *flags_ptr = (unsigned long *)caps->flags;
+
+ return test_bit(flag, flags_ptr);
+}
+
+struct mm81x_ps {
+ u32 wakers;
+ bool enable;
+ bool suspended;
+ /* PS state lock */
+ struct mutex lock;
+ struct work_struct async_wake_work;
+ struct delayed_work delayed_eval_work;
+ struct completion *awake;
+ /* hardware config supports powersave through hardware GPIOs */
+ bool gpios_supported;
+ struct gpio_desc *wake_gpio;
+ struct gpio_desc *busy_gpio;
+};
+
+enum mm81x_page_aci {
+ MM81X_ACI_BE = 0,
+ MM81X_ACI_BK = 1,
+ MM81X_ACI_VI = 2,
+ MM81X_ACI_VO = 3,
+};
+
+enum mm81x_qos_tid_up_index {
+ MM81X_QOS_TID_UP_BK = 1,
+ MM81X_QOS_TID_UP_XX = 2,
+ MM81X_QOS_TID_UP_BE = 0,
+ MM81X_QOS_TID_UP_EE = 3,
+ MM81X_QOS_TID_UP_CL = 4,
+ MM81X_QOS_TID_UP_VI = 5,
+ MM81X_QOS_TID_UP_VO = 6,
+ MM81X_QOS_TID_UP_NC = 7,
+
+ MM81X_QOS_TID_UP_LOWEST = MM81X_QOS_TID_UP_BK,
+ MM81X_QOS_TID_UP_HIGHEST = MM81X_QOS_TID_UP_NC
+};
+
+struct mm81x_sw_version {
+ u8 major;
+ u8 minor;
+ u8 patch;
+};
+
+struct mm81x_sta {
+ const struct ieee80211_vif *vif;
+ u8 addr[ETH_ALEN];
+ enum ieee80211_sta_state state;
+ bool tid_tx[IEEE80211_NUM_TIDS];
+ bool tid_start_tx[IEEE80211_NUM_TIDS];
+ u8 tid_params[IEEE80211_NUM_TIDS];
+ int max_bw_mhz;
+ struct mm81x_rc_sta rc;
+ struct mmrc_rate last_sta_tx_rate;
+ s16 avg_rssi;
+ bool tx_ps_filter_en;
+};
+
+struct mm81x_vif {
+ struct mm81x *mm;
+ u16 id;
+
+ union {
+ struct {
+ bool is_assoc;
+ } sta;
+ struct {
+ u32 num_stas;
+ struct tasklet_struct beacon_tasklet;
+ bool beaconing_enabled;
+ } ap;
+ } u;
+};
+
+struct mm81x_stale_tx_status {
+ /* Stale Tx lock */
+ spinlock_t lock;
+ struct timer_list timer;
+};
+
+struct mcast_filter {
+ u8 count;
+ /*
+ * Integer representation of the last four bytes of a multicast MAC
+ * address. The first two bytes are always 0x0100 (IPv4) or 0x3333
+ * (IPv6).
+ */
+ __le32 addr_list[];
+};
+
+enum mm81x_hw_scan_op {
+ MM81X_HW_SCAN_OP_START,
+ MM81X_HW_SCAN_OP_STOP,
+};
+
+struct mm81x_hw_scan_params {
+ struct ieee80211_hw *hw;
+
+ /* vif which initiated the scan */
+ struct ieee80211_vif *vif;
+ bool has_directed_ssid;
+ u32 dwell_time_ms;
+ u32 dwell_on_home_ms;
+ enum mm81x_hw_scan_op operation;
+ bool store;
+ struct sk_buff *probe_req;
+ u16 num_chans;
+ u16 allocated_chans;
+
+ struct {
+ struct ieee80211_channel *channel;
+ /* Index into @ref powers_qdbm for the power of this channel */
+ u8 power_idx;
+ } *channels;
+
+ s32 *powers_qdbm;
+ u8 n_powers;
+ bool use_1mhz_probes;
+};
+
+enum mm81x_hw_scan_state {
+ HW_SCAN_STATE_IDLE,
+ HW_SCAN_STATE_RUNNING,
+ HW_SCAN_STATE_ABORTING,
+};
+
+struct mm81x_hw_scan {
+ enum mm81x_hw_scan_state state;
+ struct completion scan_done;
+ struct mm81x_hw_scan_params *params;
+ struct delayed_work timeout;
+ u32 home_dwell_ms;
+};
+
+enum mm81x_hif_event_flags {
+ MM81X_HIF_EVT_RX_PEND,
+ MM81X_HIF_EVT_PAGE_RETURN_PEND,
+ MM81X_HIF_EVT_TX_COMMAND_PEND,
+ MM81X_HIF_EVT_TX_BEACON_PEND,
+ MM81X_HIF_EVT_TX_MGMT_PEND,
+ MM81X_HIF_EVT_TX_DATA_PEND,
+ MM81X_HIF_EVT_TX_PACKET_FREED_UP_PEND,
+ MM81X_HIF_EVT_DATA_TRAFFIC_PAUSE_PEND,
+ MM81X_HIF_EVT_DATA_TRAFFIC_RESUME_PEND,
+ MM81X_HIF_EVT_UPDATE_HW_CLOCK_REFERENCE,
+};
+
+enum mm81x_state_flags {
+ MM81X_STATE_CHIP_UNRESPONSIVE,
+ MM81X_STATE_DATA_QS_STOPPED,
+ MM81X_STATE_DATA_TX_STOPPED,
+ MM81X_STATE_REGDOM_SET_BY_USER,
+ MM81X_STATE_REGDOM_SET_BY_OTP,
+ MM81X_STATE_RELOAD_FW_AFTER_START,
+ MM81X_STATE_HOST_TO_CHIP_TX_BLOCKED,
+ MM81X_STATE_HOST_TO_CHIP_CMD_BLOCKED,
+};
+
+#define MM81X_COUNTRY_LEN (3)
+#define INVALID_VIF_INDEX 0xFF
+
+struct mm81x {
+ u32 chip_id;
+ u32 host_table_ptr;
+
+ /* Refer to @enum mm81x_bus_type */
+ u32 bus_type;
+ u32 bcf_address;
+
+ /* Serialise high-level operations to the mm81x structure */
+ struct mutex lock;
+
+ /*
+ * Parsed from the release tag, which should be in the format
+ * 'rel_<major>_<minor>_<patch>'. If the tag is not in this format
+ * then corresponding version field will be 0.
+ */
+ struct mm81x_sw_version sw_ver;
+ u8 macaddr[ETH_ALEN];
+ u8 country[MM81X_COUNTRY_LEN];
+
+ /* Mask of type @enum host_table_firmware_flags */
+ u32 firmware_flags;
+ struct mm81x_fw_caps fw_caps;
+ bool started;
+ bool chip_was_reset;
+ struct wiphy *wiphy;
+ struct mm81x_hw_scan hw_scan;
+ struct ieee80211_hw *hw;
+ struct device *dev;
+
+ struct ieee80211_vif __rcu *vifs[MM81X_MAX_IF];
+
+ /* @mm81x_state_flags */
+ unsigned long state_flags;
+
+ u16 cmd_seq;
+ struct completion *cmd_comp;
+ /* Serialises commands */
+ struct mutex cmd_lock;
+
+ /* Serialises command completion */
+ struct mutex cmd_wait;
+
+ const struct mm81x_regs *regs;
+
+ struct {
+ union {
+ struct mm81x_yaps yaps;
+ } u;
+ const struct mm81x_hif_ops *ops;
+ /* See @enum mm81x_hif_event_flags for values */
+ unsigned long event_flags;
+ bool validate_skb_checksum;
+ } hif;
+
+ struct workqueue_struct *chip_wq;
+ struct work_struct hif_work;
+ struct work_struct usb_irq_work;
+ struct mm81x_stale_tx_status stale_status;
+ bool config_ps;
+ struct mm81x_ps ps;
+
+ /* Tx power in mBm received from the FW before association */
+ s32 tx_power_mbm;
+ s32 tx_max_power_mbm;
+
+ const struct mm81x_bus_ops *bus_ops;
+ struct mm81x_rc mrc;
+ int rts_threshold;
+ struct workqueue_struct *net_wq;
+ struct work_struct tx_stale_work;
+
+ struct cfg80211_chan_def chandef;
+ struct mcast_filter *mcast_filter;
+ atomic_t num_bcn_vifs;
+ unsigned long beacon_irqs_enabled;
+ u8 drv_priv[] __aligned(sizeof(void *));
+};
+
+/* Map from mac80211 queue to Morse ACI value for page metadata */
+static inline u8 map_mac80211q_2_mm81x_aci(u16 mac80211queue)
+{
+ switch (mac80211queue) {
+ case IEEE80211_AC_VO:
+ return MM81X_ACI_VO;
+ case IEEE80211_AC_VI:
+ return MM81X_ACI_VI;
+ case IEEE80211_AC_BK:
+ return MM81X_ACI_BK;
+ default:
+ return MM81X_ACI_BE;
+ }
+}
+
+static inline enum mm81x_page_aci
+dot11_tid_to_ac(enum mm81x_qos_tid_up_index tid)
+{
+ switch (tid) {
+ case MM81X_QOS_TID_UP_BK:
+ case MM81X_QOS_TID_UP_XX:
+ return MM81X_ACI_BK;
+ case MM81X_QOS_TID_UP_CL:
+ case MM81X_QOS_TID_UP_VI:
+ return MM81X_ACI_VI;
+ case MM81X_QOS_TID_UP_VO:
+ case MM81X_QOS_TID_UP_NC:
+ return MM81X_ACI_VO;
+ case MM81X_QOS_TID_UP_BE:
+ case MM81X_QOS_TID_UP_EE:
+ default:
+ return MM81X_ACI_BE;
+ }
+}
+
+#ifdef CONFIG_MM81X_USB
+int __init mm81x_usb_init(void);
+void __exit mm81x_usb_exit(void);
+#endif
+
+#ifdef CONFIG_MM81X_SDIO
+int __init mm81x_sdio_init(void);
+void __exit mm81x_sdio_exit(void);
+#endif
+
+static inline bool mm81x_is_data_tx_allowed(struct mm81x *mm)
+{
+ return !test_bit(MM81X_STATE_DATA_TX_STOPPED, &mm->state_flags) &&
+ !test_bit(MM81X_HIF_EVT_DATA_TRAFFIC_PAUSE_PEND,
+ &mm->hif.event_flags);
+}
+
+static inline struct ieee80211_vif *
+mm81x_vif_to_ieee80211_vif(struct mm81x_vif *mm_vif)
+{
+ return container_of((void *)mm_vif, struct ieee80211_vif, drv_priv);
+}
+
+static inline struct mm81x_vif *
+ieee80211_vif_to_mm_vif(struct ieee80211_vif *vif)
+{
+ return (struct mm81x_vif *)vif->drv_priv;
+}
+
+static inline struct mm81x *mm81x_vif_to_mm(struct mm81x_vif *mm_vif)
+{
+ return mm_vif->mm;
+}
+
+static inline u32 mm81x_generate_cssid(const u8 *ssid, u8 len)
+{
+ return ~crc32(~0, ssid, len);
+}
+
+int mm81x_beacon_init(struct mm81x_vif *mm_vif);
+void mm81x_beacon_finish(struct mm81x_vif *mm_vif);
+void mm81x_beacon_irq_handle(struct mm81x *mm, u32 status);
+int mm81x_usb_ndr_reset(struct mm81x *mm);
+
+int mm81x_core_attach_regs(struct mm81x *mm);
+void mm81x_core_init_mac_addr(struct mm81x *mm);
+char *mm81x_core_get_fw_path(u32 chip_id);
+int mm81x_core_create(struct mm81x *mm);
+void mm81x_core_destroy(struct mm81x *mm);
+
+#endif /* !_MM81X_MM81X_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 07/35] wifi: mm81x: add debug.c
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/debug.c | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/debug.c
diff --git a/drivers/net/wireless/morsemicro/mm81x/debug.c b/drivers/net/wireless/morsemicro/mm81x/debug.c
new file mode 100644
index 000000000000..6c9720fa452c
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/debug.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+#include <linux/stdarg.h>
+#include "core.h"
+#include "debug.h"
+
+void mm81x_info(struct mm81x *mm, const char *fmt, ...)
+{
+ struct va_format vaf = { .fmt = fmt };
+ va_list args;
+
+ va_start(args, fmt);
+ vaf.va = &args;
+ dev_info(mm->dev, "%pV\n", &vaf);
+ va_end(args);
+}
+
+void mm81x_err(struct mm81x *mm, const char *fmt, ...)
+{
+ struct va_format vaf = { .fmt = fmt };
+ va_list args;
+
+ va_start(args, fmt);
+ vaf.va = &args;
+ dev_err(mm->dev, "%pV\n", &vaf);
+ va_end(args);
+}
+
+void __mm81x_warn(struct device *dev, const char *fmt, ...)
+{
+ struct va_format vaf = { .fmt = fmt };
+ va_list args;
+
+ va_start(args, fmt);
+ vaf.va = &args;
+ dev_warn_ratelimited(dev, "%pV\n", &vaf);
+ va_end(args);
+}
+
+#ifdef CONFIG_MM81X_DEBUG
+void __mm81x_dbg(struct mm81x *mm, enum mm81x_debug_mask mask, const char *fmt,
+ ...)
+{
+ struct va_format vaf;
+ va_list args;
+
+ va_start(args, fmt);
+ vaf.fmt = fmt;
+ vaf.va = &args;
+ dev_dbg(mm->dev, "%pV\n", &vaf);
+ va_end(args);
+}
+
+void mm81x_dbg_dump(struct mm81x *mm, enum mm81x_debug_mask mask,
+ const char *msg, const char *prefix, const void *buf,
+ size_t len)
+{
+ const u8 *ptr = buf;
+ char line[256];
+
+ if (!(mm81x_debug_mask & mask))
+ return;
+
+ if (msg)
+ __mm81x_dbg(mm, mask, "%s", msg);
+
+ if (!buf || !len)
+ return;
+
+ while (ptr < (const u8 *)buf + len) {
+ size_t off = ptr - (const u8 *)buf;
+ size_t n = min_t(size_t, 16, (const u8 *)buf + len - ptr);
+ size_t p = 0;
+
+ p += scnprintf(line + p, sizeof(line) - p,
+ "%s%08zx: ", prefix ? prefix : "", off);
+ hex_dump_to_buffer(ptr, n, 16, 1, line + p, sizeof(line) - p,
+ true);
+ dev_dbg(mm->dev, "%s\n", line);
+ ptr += n;
+ }
+}
+#endif /* CONFIG_MM81X_DEBUG */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 08/35] wifi: mm81x: add debug.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/debug.h | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/debug.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/debug.h b/drivers/net/wireless/morsemicro/mm81x/debug.h
new file mode 100644
index 000000000000..9f78386c3ab1
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/debug.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_DEBUG_H_
+#define _MM81X_DEBUG_H_
+
+#include <linux/device.h>
+#include <linux/printk.h>
+#include <linux/types.h>
+
+struct mm81x;
+
+enum mm81x_debug_mask {
+ MM81X_DBG_FW = BIT(0),
+ MM81X_DBG_MAC = BIT(1),
+ MM81X_DBG_SKBQ = BIT(2),
+ MM81X_DBG_USB = BIT(3),
+ MM81X_DBG_SDIO = BIT(4),
+ MM81X_DBG_ANY = ~0U,
+};
+
+extern unsigned int mm81x_debug_mask;
+
+__printf(2, 3) void mm81x_info(struct mm81x *mm, const char *fmt, ...);
+__printf(2, 3) void mm81x_err(struct mm81x *mm, const char *fmt, ...);
+__printf(2, 3) void __mm81x_warn(struct device *dev, const char *fmt, ...);
+#define mm81x_warn(mm, fmt, ...) __mm81x_warn((mm)->dev, fmt, ##__VA_ARGS__)
+
+#ifdef CONFIG_MM81X_DEBUG
+__printf(3, 4) void __mm81x_dbg(struct mm81x *mm, enum mm81x_debug_mask mask,
+ const char *fmt, ...);
+
+void mm81x_dbg_dump(struct mm81x *mm, enum mm81x_debug_mask mask,
+ const char *msg, const char *prefix, const void *buf,
+ size_t len);
+#else
+static inline void __mm81x_dbg(struct mm81x *mm, enum mm81x_debug_mask mask,
+ const char *fmt, ...)
+{
+}
+
+static inline void mm81x_dbg_dump(struct mm81x *mm, enum mm81x_debug_mask mask,
+ const char *msg, const char *prefix,
+ const void *buf, size_t len)
+{
+}
+#endif
+
+#define mm81x_dbg(mm, dbg_mask, fmt, ...) \
+ do { \
+ typeof(dbg_mask) __mask = (dbg_mask); \
+ if (mm81x_debug_mask & __mask) \
+ __mm81x_dbg((mm), __mask, fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#endif /* _MM81X_DEBUG_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 09/35] wifi: mm81x: add fw.c
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/fw.c | 743 +++++++++++++++++++++
1 file changed, 743 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/fw.c
diff --git a/drivers/net/wireless/morsemicro/mm81x/fw.c b/drivers/net/wireless/morsemicro/mm81x/fw.c
new file mode 100644
index 000000000000..6d138419abce
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/fw.c
@@ -0,0 +1,743 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+#include <linux/kernel.h>
+#include <linux/firmware.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/string_choices.h>
+#include <net/mac80211.h>
+#include <linux/elf.h>
+#include <linux/crc32.h>
+#include "debug.h"
+#include "fw.h"
+#include "mac.h"
+#include "bus.h"
+
+/*
+ * Maximum wait time (milliseconds) for firmware to boot (for host table
+ * pointer to be available)
+ */
+#define MAX_WAIT_FOR_HOST_TABLE_PTR_MS 1200
+
+/* Number of times to attempt flashing FW */
+#define FW_FLASH_ATTEMPT_COUNT 3
+
+static int mm81x_fw_get_header(const u8 *data, mm81x_elf_ehdr *ehdr)
+{
+ mm81x_elf_ehdr *p = (mm81x_elf_ehdr *)data;
+
+ /* Magic check */
+ if (p->e_ident[EI_MAG0] != ELFMAG0 || p->e_ident[EI_MAG1] != ELFMAG1 ||
+ p->e_ident[EI_MAG2] != ELFMAG2 || p->e_ident[EI_MAG3] != ELFMAG3)
+ return -EINVAL;
+
+ /* elf32 and little endian */
+ if (p->e_ident[EI_DATA] != ELFDATA2LSB ||
+ p->e_ident[EI_CLASS] != ELFCLASS32)
+ return -EINVAL;
+
+ ehdr->e_phoff = mm81x_fle32_to_cpu(p->e_phoff);
+ ehdr->e_phentsize = mm81x_fle16_to_cpu(p->e_phentsize);
+ ehdr->e_phnum = mm81x_fle16_to_cpu(p->e_phnum);
+ ehdr->e_shoff = mm81x_fle32_to_cpu(p->e_shoff);
+ ehdr->e_shentsize = mm81x_fle16_to_cpu(p->e_shentsize);
+ ehdr->e_shnum = mm81x_fle16_to_cpu(p->e_shnum);
+ ehdr->e_shstrndx = mm81x_fle16_to_cpu(p->e_shstrndx);
+ ehdr->e_entry = mm81x_fle32_to_cpu(p->e_entry);
+
+ return 0;
+}
+
+static void mm81x_fw_parse_info(struct mm81x *mm, const u8 *data, int length)
+{
+ const struct mm81x_fw_info_tlv *tlv =
+ (const struct mm81x_fw_info_tlv *)data;
+
+ while ((u8 *)tlv < (data + length)) {
+ switch (le16_to_cpu(tlv->type)) {
+ case MM81X_FW_INFO_TLV_BCF_ADDR:
+ mm->bcf_address =
+ get_unaligned_le32((__force __le32 *)tlv->val);
+ break;
+ default:
+ break;
+ }
+ tlv = (const struct mm81x_fw_info_tlv *)((u8 *)tlv +
+ le16_to_cpu(
+ tlv->length) +
+ sizeof(*tlv));
+ }
+}
+
+static int mm81x_fw_get_section_header(const u8 *data, mm81x_elf_ehdr *ehdr,
+ mm81x_elf_shdr *shdr, int i)
+{
+ mm81x_elf_shdr *p = (mm81x_elf_shdr *)(data + ehdr->e_shoff +
+ (i * ehdr->e_shentsize));
+
+ shdr->sh_name = mm81x_fle32_to_cpu(p->sh_name);
+ shdr->sh_type = mm81x_fle32_to_cpu(p->sh_type);
+ shdr->sh_offset = mm81x_fle32_to_cpu(p->sh_offset);
+ shdr->sh_addr = mm81x_fle32_to_cpu(p->sh_addr);
+ shdr->sh_size = mm81x_fle32_to_cpu(p->sh_size);
+ shdr->sh_flags = mm81x_fle32_to_cpu(p->sh_flags);
+
+ return 0;
+}
+
+static int mm81x_fw_set_boot_addr(struct mm81x *mm, uint32_t addr)
+{
+ int status;
+
+ mm81x_dbg(mm, MM81X_DBG_FW, "Overwriting boot address to 0x%x", addr);
+ mm81x_claim_bus(mm);
+ status = mm81x_reg32_write(mm, MM81X_REG_BOOT_ADDR(mm), addr);
+ mm81x_release_bus(mm);
+ return status;
+}
+
+static int mm81x_fw_load_fw(struct mm81x *mm, const struct firmware *fw)
+{
+ int i;
+ int ret = 0;
+ mm81x_elf_ehdr ehdr;
+ mm81x_elf_phdr phdr;
+ mm81x_elf_shdr shdr;
+ mm81x_elf_shdr sh_strtab;
+ const char *sh_strs;
+
+ u8 *fw_buf = devm_kmalloc(mm->dev, ROUND_BYTES_TO_WORD(fw->size),
+ GFP_KERNEL);
+
+ if (!fw_buf)
+ return -ENOMEM;
+
+ if (mm81x_fw_get_header(fw->data, &ehdr)) {
+ mm81x_err(mm, "Wrong file format");
+ return -EINVAL;
+ }
+
+ if (mm81x_fw_get_section_header(fw->data, &ehdr, &sh_strtab,
+ ehdr.e_shstrndx)) {
+ mm81x_err(mm, "Invalid firmware. Missing string table");
+ return -ENOENT;
+ }
+
+ sh_strs = (const char *)fw->data + sh_strtab.sh_offset;
+
+ for (i = 0; i < ehdr.e_phnum; i++) {
+ int status;
+ int address;
+
+ mm81x_elf_phdr *p = (mm81x_elf_phdr *)(fw->data + ehdr.e_phoff +
+ i * ehdr.e_phentsize);
+
+ phdr.p_type = le32_to_cpu((__force __le32)p->p_type);
+ phdr.p_offset = le32_to_cpu((__force __le32)p->p_offset);
+ phdr.p_paddr = le32_to_cpu((__force __le32)p->p_paddr);
+ phdr.p_filesz = le32_to_cpu((__force __le32)p->p_filesz);
+ phdr.p_memsz = le32_to_cpu((__force __le32)p->p_memsz);
+
+ address = phdr.p_paddr;
+ if (address == IFLASH_BASE_ADDR || address == DFLASH_BASE_ADDR)
+ continue;
+
+ if (phdr.p_type != PT_LOAD || !phdr.p_memsz)
+ continue;
+
+ if (phdr.p_filesz && phdr.p_offset &&
+ (phdr.p_offset + phdr.p_filesz) < fw->size) {
+ u32 padded_size = ROUND_BYTES_TO_WORD(phdr.p_filesz);
+
+ memcpy(fw_buf, fw->data + phdr.p_offset, padded_size);
+ /* Set padding to 0xff */
+ memset(fw_buf + phdr.p_filesz, 0xff,
+ padded_size - phdr.p_filesz);
+ mm81x_claim_bus(mm);
+ status = mm81x_dm_write(mm, address, fw_buf,
+ padded_size);
+ mm81x_release_bus(mm);
+ if (status) {
+ ret = -EIO;
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < ehdr.e_shnum; i++) {
+ if (mm81x_fw_get_section_header(fw->data, &ehdr, &shdr, i))
+ continue;
+
+ /* This is the firmware info. Parse it */
+ if (!strncmp(sh_strs + shdr.sh_name, ".fw_info",
+ sizeof(".fw_info")))
+ mm81x_fw_parse_info(mm, fw->data + shdr.sh_offset,
+ shdr.sh_size);
+ }
+
+ if (ehdr.e_entry)
+ ret = mm81x_fw_set_boot_addr(mm, ehdr.e_entry);
+
+ devm_kfree(mm->dev, fw_buf);
+ return ret;
+}
+
+static int __mm81x_fw_load_bcf(struct mm81x *mm, unsigned int addr,
+ const void *src, size_t src_len, u8 *scratch,
+ size_t scratch_cap)
+{
+ size_t rounded = ROUND_BYTES_TO_WORD(src_len);
+ int st;
+
+ if (rounded > scratch_cap)
+ return -EINVAL;
+ if (rounded > BCF_DATABASE_SIZE)
+ return -EFBIG;
+
+ memcpy(scratch, src, src_len);
+ if (rounded > src_len)
+ memset(scratch + src_len, 0xff, rounded - src_len);
+
+ mm81x_claim_bus(mm);
+ st = mm81x_dm_write(mm, addr, scratch, rounded);
+ mm81x_release_bus(mm);
+
+ return st ? -EIO : 0;
+}
+
+static int mm81x_fw_load_bcf(struct mm81x *mm, const struct firmware *bcf,
+ unsigned int bcf_address)
+{
+ int i, ret = 0;
+ size_t reg_prefix_len, cfg_len_rounded = 0, reg_len_rounded;
+ mm81x_elf_ehdr ehdr;
+ mm81x_elf_shdr shdr, sh_strtab;
+ const char *sh_strs, *reg_prefix = ".regdom_", *reg_src;
+ size_t reg_len;
+ u8 *bcf_buf;
+
+ bcf_buf = devm_kmalloc(mm->dev, ROUND_BYTES_TO_WORD(bcf->size),
+ GFP_KERNEL);
+ if (!bcf_buf)
+ return -ENOMEM;
+
+ if (mm81x_fw_get_header(bcf->data, &ehdr)) {
+ mm81x_err(mm, "Wrong file format");
+ ret = -EINVAL;
+ goto out_free;
+ }
+
+ if (mm81x_fw_get_section_header(bcf->data, &ehdr, &sh_strtab,
+ ehdr.e_shstrndx)) {
+ mm81x_err(mm, "Invalid BCF - missing string table");
+ ret = -ENOENT;
+ goto out_free;
+ }
+
+ sh_strs = (const char *)bcf->data + sh_strtab.sh_offset;
+ reg_prefix_len = strlen(reg_prefix);
+
+ for (i = 0; i < ehdr.e_shnum; i++) {
+ if (mm81x_fw_get_section_header(bcf->data, &ehdr, &shdr, i))
+ continue;
+ if (strcmp(sh_strs + shdr.sh_name, ".board_config"))
+ continue;
+
+ cfg_len_rounded = ROUND_BYTES_TO_WORD(shdr.sh_size);
+ mm81x_dbg(mm, MM81X_DBG_FW,
+ "Write BCF board_config - addr 0x%x size %zu",
+ bcf_address, cfg_len_rounded);
+
+ ret = __mm81x_fw_load_bcf(mm, bcf_address,
+ bcf->data + shdr.sh_offset,
+ shdr.sh_size, bcf_buf,
+ ROUND_BYTES_TO_WORD(bcf->size));
+ if (ret)
+ goto out_free;
+
+ bcf_address += cfg_len_rounded;
+ break;
+ }
+
+ ret = -EINVAL;
+ for (; i < ehdr.e_shnum; i++) {
+ if (mm81x_fw_get_section_header(bcf->data, &ehdr, &shdr, i))
+ continue;
+ if (strncmp(sh_strs + shdr.sh_name, reg_prefix, reg_prefix_len))
+ continue;
+ if (strncmp(sh_strs + shdr.sh_name + reg_prefix_len,
+ mm->country, 2))
+ continue;
+
+ reg_src = bcf->data + shdr.sh_offset;
+ reg_len = shdr.sh_size;
+ mm81x_dbg(mm, MM81X_DBG_FW, "Write BCF %s - addr 0x%x size %zu",
+ sh_strs + shdr.sh_name, bcf_address,
+ ROUND_BYTES_TO_WORD(reg_len));
+ ret = 0;
+ break;
+ }
+
+ if (ret)
+ goto out_free;
+
+ reg_len_rounded = ROUND_BYTES_TO_WORD(reg_len);
+ if ((cfg_len_rounded + reg_len_rounded) > BCF_DATABASE_SIZE) {
+ ret = -EFBIG;
+ goto out_free;
+ }
+
+ ret = __mm81x_fw_load_bcf(mm, bcf_address, reg_src, reg_len, bcf_buf,
+ ROUND_BYTES_TO_WORD(bcf->size));
+
+out_free:
+ devm_kfree(mm->dev, bcf_buf);
+ return ret;
+}
+
+static void mm81x_fw_clear_aon(struct mm81x *mm)
+{
+ int idx;
+ u8 count = MM81X_REG_AON_COUNT(mm);
+ u32 address = MM81X_REG_AON_ADDR(mm);
+
+ if (address) {
+ for (idx = 0; idx < count; idx++, address += 4) {
+ if (mm->bus_type == MM81X_BUS_TYPE_USB && idx == 0)
+ /* Keep the USB power domain enabled in AON. */
+ mm81x_reg32_write(mm, address,
+ MM81X_REG_AON_USB_RESET(mm));
+ else
+ /* clear AON */
+ mm81x_reg32_write(mm, address, 0x0);
+ }
+ }
+
+ mm81x_hw_toggle_aon_latch(mm);
+}
+
+static void mm81x_fw_trigger(struct mm81x *mm)
+{
+ const unsigned int wait_after_msi_trigger_ms = 1;
+
+ mm81x_claim_bus(mm);
+ /*
+ * If not coming from a full reset, some AON flags may be latched.
+ * Make sure to clear any hanging AON bits (can affect booting).
+ */
+ mm81x_fw_clear_aon(mm);
+
+ if (MM81X_REG_CLK_CTRL(mm))
+ mm81x_reg32_write(mm, MM81X_REG_CLK_CTRL(mm),
+ MM81X_REG_CLK_CTRL_VALUE(mm));
+
+ mm81x_reg32_write(mm, MM81X_REG_MSI(mm), MM81X_REG_MSI_HOST_INT(mm));
+ mm81x_release_bus(mm);
+
+ /* Give the chip a chance to boot */
+ mdelay(wait_after_msi_trigger_ms);
+}
+
+static int mm81x_fw_verify_magic(struct mm81x *mm)
+{
+ int ret = 0;
+ int magic = ~MM81X_REG_HOST_MAGIC_VALUE(mm);
+
+ mm81x_claim_bus(mm);
+ mm81x_reg32_read(mm,
+ mm->host_table_ptr +
+ offsetof(struct host_table, magic_number),
+ &magic);
+
+ if (magic != MM81X_REG_HOST_MAGIC_VALUE(mm)) {
+ mm81x_err(mm, "FW magic mismatch 0x%08x:0x%08x",
+ MM81X_REG_HOST_MAGIC_VALUE(mm), magic);
+ ret = -EIO;
+ }
+
+ mm81x_release_bus(mm);
+ return ret;
+}
+
+static int mm81x_fw_get_flags(struct mm81x *mm)
+{
+ int ret = 0;
+ int fw_flags = 0;
+
+ mm81x_claim_bus(mm);
+ ret = mm81x_reg32_read(mm,
+ mm->host_table_ptr + offsetof(struct host_table,
+ firmware_flags),
+ &fw_flags);
+ mm->firmware_flags = fw_flags;
+ mm81x_release_bus(mm);
+
+ return ret;
+}
+
+static int mm81x_fw_check_compatibility(struct mm81x *mm)
+{
+ int ret = 0;
+ u32 fw_version;
+ u32 major;
+ u32 minor;
+ u32 patch;
+
+ mm81x_claim_bus(mm);
+ ret = mm81x_reg32_read(mm,
+ mm->host_table_ptr + offsetof(struct host_table,
+ fw_version_number),
+ &fw_version);
+ mm81x_release_bus(mm);
+
+ major = MM81X_SEMVER_GET_MAJOR(fw_version);
+ minor = MM81X_SEMVER_GET_MINOR(fw_version);
+ patch = MM81X_SEMVER_GET_PATCH(fw_version);
+
+ /* Firmware on device must be recent enough for driver */
+ if (ret == 0 && major != HOST_CMD_SEMVER_MAJOR) {
+ mm81x_err(
+ mm,
+ "Incompatible FW version: (Driver) %d.%d.%d, (Chip) %d.%d.%d\n",
+ HOST_CMD_SEMVER_MAJOR, HOST_CMD_SEMVER_MINOR,
+ HOST_CMD_SEMVER_PATCH, major, minor, patch);
+ ret = -EPERM;
+ } else if (ret == 0 && minor != HOST_CMD_SEMVER_MINOR) {
+ mm81x_warn(
+ mm,
+ "FW version mismatch, some features might not be supported: (Driver) %d.%d.%d, (Chip) %d.%d.%d",
+ HOST_CMD_SEMVER_MAJOR, HOST_CMD_SEMVER_MINOR,
+ HOST_CMD_SEMVER_PATCH, major, minor, patch);
+ }
+
+ return ret;
+}
+
+static int mm81x_fw_invalidate_host_ptr(struct mm81x *mm)
+{
+ int ret;
+
+ mm->host_table_ptr = 0;
+ mm81x_claim_bus(mm);
+ ret = mm81x_reg32_write(mm, MM81X_REG_HOST_MANIFEST_PTR(mm), 0);
+ mm81x_release_bus(mm);
+ return ret;
+}
+
+static int mm81x_fw_get_host_table_ptr(struct mm81x *mm)
+{
+ int ret = 0;
+ unsigned long timeout =
+ jiffies + msecs_to_jiffies(MAX_WAIT_FOR_HOST_TABLE_PTR_MS);
+
+ mm81x_claim_bus(mm);
+ while (1) {
+ ret = mm81x_reg32_read(mm, MM81X_REG_HOST_MANIFEST_PTR(mm),
+ &mm->host_table_ptr);
+
+ if (mm->host_table_ptr)
+ break;
+
+ if (time_after(jiffies, timeout)) {
+ ret = -EIO;
+ break;
+ }
+
+ usleep_range(5000, 10000);
+ }
+
+ mm81x_release_bus(mm);
+ return ret;
+}
+
+static int mm81x_fw_read_ext_host_table(struct mm81x *mm,
+ struct ext_host_tbl **ext_host_table)
+{
+ int ret = 0;
+ u32 host_tbl_ptr = mm->host_table_ptr;
+ u32 ext_host_tbl_ptr;
+ u32 ext_host_tbl_ptr_addr =
+ host_tbl_ptr + offsetof(struct host_table, ext_host_tbl_addr);
+ u32 ext_host_tbl_len;
+ u32 ext_host_tbl_len_ptr_addr;
+ struct ext_host_tbl *host_tbl = NULL;
+
+ mm81x_claim_bus(mm);
+ ret = mm81x_reg32_read(mm, ext_host_tbl_ptr_addr, &ext_host_tbl_ptr);
+ if (ret)
+ goto exit;
+
+ if (!ext_host_tbl_ptr) {
+ ret = -ENXIO;
+ goto exit;
+ }
+
+ ext_host_tbl_len_ptr_addr =
+ ext_host_tbl_ptr +
+ offsetof(struct ext_host_tbl, ext_host_tbl_length);
+
+ ret = mm81x_reg32_read(mm, ext_host_tbl_len_ptr_addr,
+ &ext_host_tbl_len);
+ if (ret)
+ goto exit;
+
+ ext_host_tbl_len = ROUND_BYTES_TO_WORD(ext_host_tbl_len);
+ if (WARN_ON(ext_host_tbl_len == 0 || ext_host_tbl_len > INT_MAX)) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ host_tbl = kmalloc(ext_host_tbl_len, GFP_KERNEL);
+ if (!host_tbl) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ ret = mm81x_dm_read(mm, ext_host_tbl_ptr, (u8 *)host_tbl,
+ (int)ext_host_tbl_len);
+ if (ret)
+ goto exit;
+
+ mm81x_release_bus(mm);
+ *ext_host_table = host_tbl;
+ return ret;
+
+exit:
+ mm81x_release_bus(mm);
+ kfree(host_tbl);
+ return ret;
+}
+
+static void mm81x_fw_update_capabilities(struct mm81x *mm,
+ struct ext_host_tbl_s1g_caps *caps)
+{
+ int i;
+
+ for (i = 0; i < FW_CAPABILITIES_FLAGS_WIDTH; i++) {
+ mm->fw_caps.flags[i] = le32_to_cpu(caps->flags[i]);
+ mm81x_dbg(mm, MM81X_DBG_FW, "Firmware Manifest Flags%d: 0x%x",
+ i, le32_to_cpu(caps->flags[i]));
+ }
+ mm->fw_caps.ampdu_mss = caps->ampdu_mss;
+ mm->fw_caps.mm81x_mmss_offset = caps->mm81x_mmss_offset;
+ mm->fw_caps.beamformee_sts_capability = caps->beamformee_sts_capability;
+ mm->fw_caps.maximum_ampdu_length_exponent = caps->maximum_ampdu_length;
+ mm->fw_caps.number_sounding_dimensions =
+ caps->number_sounding_dimensions;
+
+ mm81x_dbg(mm, MM81X_DBG_FW, "\tAMPDU Minimum start spacing: %u",
+ caps->ampdu_mss);
+ mm81x_dbg(mm, MM81X_DBG_FW, "\tMorse Minimum Start Spacing offset: %u",
+ caps->mm81x_mmss_offset);
+ mm81x_dbg(mm, MM81X_DBG_FW, "\tBeamformee STS Capability: %u",
+ caps->beamformee_sts_capability);
+ mm81x_dbg(mm, MM81X_DBG_FW, "\tNumber of Sounding Dimensions: %u",
+ caps->number_sounding_dimensions);
+ mm81x_dbg(mm, MM81X_DBG_FW, "\tMaximum AMPDU Length Exponent: %u",
+ caps->maximum_ampdu_length);
+}
+
+static void mm81x_fw_update_validate_skb_checksum(
+ struct mm81x *mm,
+ struct ext_host_tbl_insert_skb_checksum *validate_checksum)
+{
+ mm->hif.validate_skb_checksum =
+ validate_checksum->insert_and_validate_checksum;
+ mm81x_dbg(mm, MM81X_DBG_ANY, "Validate checksum inserted by fw %s",
+ str_enabled_disabled(mm->hif.validate_skb_checksum));
+}
+
+int mm81x_fw_parse_ext_host_tbl(struct mm81x *mm)
+{
+ int ret;
+ u8 *head;
+ u8 *end;
+ struct ext_host_tbl *ext_host_table = NULL;
+
+ ret = mm81x_fw_read_ext_host_table(mm, &ext_host_table);
+ if (ret || !ext_host_table)
+ goto exit;
+
+ /* Parse the TLVs */
+ head = ext_host_table->ext_host_table_data_tlvs;
+ end = ((u8 *)ext_host_table) +
+ le32_to_cpu(ext_host_table->ext_host_tbl_length);
+
+ while (head < end) {
+ struct ext_host_tbl_tlv_hdr *hdr =
+ (struct ext_host_tbl_tlv_hdr *)head;
+
+ switch (le16_to_cpu(hdr->tag)) {
+ case MM81X_FW_HOST_TABLE_TAG_S1G_CAPABILITIES:
+ mm81x_fw_update_capabilities(
+ mm, (struct ext_host_tbl_s1g_caps *)hdr);
+ break;
+
+ case MM81X_FW_HOST_TABLE_TAG_INSERT_SKB_CHECKSUM:
+ mm81x_fw_update_validate_skb_checksum(
+ mm,
+ (struct ext_host_tbl_insert_skb_checksum *)hdr);
+ break;
+
+ case MM81X_FW_HOST_TABLE_TAG_YAPS_TABLE:
+ mm81x_yaps_hw_read_table(
+ mm, &((struct ext_host_tbl_yaps_table *)hdr)
+ ->yaps_table);
+ break;
+ default:
+ break;
+ }
+
+ head += le16_to_cpu(hdr->length);
+ if (!hdr->length)
+ break;
+ }
+
+ kfree(ext_host_table);
+ return ret;
+exit:
+ mm81x_err(mm, "failed to parse ext host table %d", ret);
+ return ret;
+}
+
+static int __mm81x_fw_flash(struct mm81x *mm, const struct firmware *fw,
+ const struct firmware *bcf, bool reset)
+{
+ int ret;
+
+ if (reset || !mm->chip_was_reset) {
+ ret = mm81x_hw_digital_reset(mm);
+ if (ret)
+ return ret;
+ }
+
+ mm81x_hw_pre_firmware_ndr_hook(mm);
+
+ ret = mm81x_fw_invalidate_host_ptr(mm);
+ if (ret)
+ return ret;
+
+ ret = mm81x_fw_load_fw(mm, fw);
+ if (ret)
+ return ret;
+
+ ret = mm81x_fw_load_bcf(mm, bcf, mm->bcf_address);
+ if (ret)
+ return ret;
+
+ mm81x_fw_trigger(mm);
+ mm81x_hw_post_firmware_ndr_hook(mm);
+
+ ret = mm81x_fw_get_host_table_ptr(mm);
+ if (ret)
+ return ret;
+
+ ret = mm81x_fw_verify_magic(mm);
+ if (ret)
+ return ret;
+
+ return mm81x_fw_check_compatibility(mm);
+}
+
+static int mm81x_fw_flash(struct mm81x *mm, const struct firmware *fw,
+ const struct firmware *bcf, bool reset)
+{
+ int ret;
+ int retries = FW_FLASH_ATTEMPT_COUNT;
+
+ while (retries--) {
+ ret = __mm81x_fw_flash(mm, fw, bcf, reset);
+ if (!ret)
+ return 0;
+
+ mm->chip_was_reset = false;
+ }
+
+ return ret;
+}
+
+static uint32_t binary_crc(const struct firmware *fw)
+{
+ return ~crc32_le(~0, (unsigned char const *)fw->data, fw->size) &
+ 0xffffffff;
+}
+
+int mm81x_fw_init(struct mm81x *mm, bool reset)
+{
+ int ret;
+ int n;
+ int board_id;
+ char *fw_path;
+ char bcf_path[MAX_BCF_NAME_LEN];
+ const struct firmware *fw = NULL;
+ const struct firmware *bcf = NULL;
+
+ fw_path = mm81x_core_get_fw_path(mm->chip_id);
+ if (!fw_path)
+ return -ENOMEM;
+
+ board_id = mm81x_hw_otp_get_board_type(mm);
+
+ if (strlen(board_config_file) > 0) {
+ n = snprintf(bcf_path, sizeof(bcf_path), "%s/%s", MM81X_FW_DIR,
+ board_config_file);
+ } else if (mm81x_hw_otp_valid_board_type(board_id)) {
+ mm81x_dbg(mm, MM81X_DBG_FW, "Using board type 0x%04x from OTP",
+ board_id);
+ n = snprintf(bcf_path, sizeof(bcf_path),
+ "%s/bcf_boardtype_%04x.bin", MM81X_FW_DIR,
+ board_id);
+ } else {
+ mm81x_err(mm, "BCF or Serial parameters are not defined");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (n < 0 || n >= sizeof(bcf_path)) {
+ mm81x_err(mm, "Failed to create BCF path");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = request_firmware(&fw, fw_path, mm->dev);
+ if (ret) {
+ if (ret == -ENOENT)
+ dev_err(mm->dev, "Firmware %s not found\n", fw_path);
+ goto out;
+ }
+
+ dev_info(mm->dev, "Loaded firmware from %s, size %zu, crc32 0x%08x\n",
+ fw_path, fw->size, binary_crc(fw));
+
+ ret = request_firmware(&bcf, bcf_path, mm->dev);
+ if (ret) {
+ if (ret == -ENOENT)
+ dev_err(mm->dev, "BCF %s not found\n", bcf_path);
+ goto out;
+ }
+
+ dev_info(mm->dev, "Loaded BCF from %s, size %zu, crc32 0x%08x\n",
+ bcf_path, bcf->size, binary_crc(bcf));
+
+ ret = mm81x_fw_flash(mm, fw, bcf, reset);
+ if (ret) {
+ mm81x_err(mm, "failed to flash firmware: %d", ret);
+ goto out;
+ }
+
+ ret = mm81x_fw_get_flags(mm);
+
+out:
+ release_firmware(fw);
+ release_firmware(bcf);
+ kfree(fw_path);
+
+ if (ret)
+ mm81x_err(mm, "failed to init firmware: %d", ret);
+ else
+ mm81x_dbg(mm, MM81X_DBG_FW, "firmware initialised");
+
+ return ret;
+}
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 10/35] wifi: mm81x: add fw.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/fw.h | 107 +++++++++++++++++++++
1 file changed, 107 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/fw.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/fw.h b/drivers/net/wireless/morsemicro/mm81x/fw.h
new file mode 100644
index 000000000000..6d1e66934248
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/fw.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_FW_H_
+#define _MM81X_FW_H_
+
+#include <linux/firmware.h>
+#include <linux/completion.h>
+#include "yaps_hw.h"
+
+#define BCF_DATABASE_SIZE (1024)
+#define MM81X_FW_DIR "morsemicro"
+#define MM81X_FW_EXT ".bin"
+
+#define IFLASH_BASE_ADDR 0x400000
+#define DFLASH_BASE_ADDR 0xC00000
+
+#define MAX_BCF_NAME_LEN 64
+
+/* FW_CAPABILITIES_FLAGS_WIDTH = ceil(MM81X_CAPS_MAX_HW_LEN / 32) */
+#define FW_CAPABILITIES_FLAGS_WIDTH (4)
+
+/* Checkpatch does not like Camel Case */
+#define mm81x_elf_ehdr Elf32_Ehdr
+#define mm81x_elf_shdr Elf32_Shdr
+#define mm81x_elf_phdr Elf32_Phdr
+
+enum mm81x_fw_info_tlv_type {
+ MM81X_FW_INFO_TLV_BCF_ADDR = 1,
+};
+
+struct mm81x_fw_info_tlv {
+ __le16 type;
+ __le16 length;
+ u8 val[];
+} __packed;
+
+enum mm81x_fw_ext_host_tbl_tag {
+ /* The S1G capability tag */
+ MM81X_FW_HOST_TABLE_TAG_S1G_CAPABILITIES = 0,
+ MM81X_FW_HOST_TABLE_TAG_PAGER_BYPASS_TX_STATUS = 1,
+ MM81X_FW_HOST_TABLE_TAG_INSERT_SKB_CHECKSUM = 2,
+ MM81X_FW_HOST_TABLE_TAG_YAPS_TABLE = 3,
+ MM81X_FW_HOST_TABLE_TAG_PAGER_PKT_MEMORY = 4,
+ MM81X_FW_HOST_TABLE_TAG_PAGER_BYPASS_CMD_RESP = 5,
+};
+
+struct ext_host_tbl_tlv_hdr {
+ /* The tag used to identify which capability this represents */
+ __le16 tag;
+ /* The length of the capability structure including this header */
+ __le16 length;
+} __packed;
+
+struct ext_host_tbl_s1g_caps {
+ struct ext_host_tbl_tlv_hdr header;
+ __le32 flags[FW_CAPABILITIES_FLAGS_WIDTH];
+ /*
+ * The minimum A-MPDU start spacing required by firmware.
+ * Value | Description
+ * ------|------------
+ * 0 | No restriction
+ * 1 | 1/4 us
+ * 2 | 1/2 us
+ * 3 | 1 us
+ * 4 | 2 us
+ * 5 | 4 us
+ * 6 | 8 us
+ * 7 | 16 us
+ */
+ u8 ampdu_mss;
+ u8 beamformee_sts_capability;
+ u8 number_sounding_dimensions;
+ /*
+ * The maximum A-MPDU length. This is the exponent value such that
+ * (2^(13 + exponent) - 1) is the length
+ */
+ u8 maximum_ampdu_length;
+ /*
+ * Offset to apply to the specification's MMSS table to signal further
+ * minimum MPDU start spacing.
+ */
+ u8 mm81x_mmss_offset;
+} __packed;
+
+struct ext_host_tbl_insert_skb_checksum {
+ struct ext_host_tbl_tlv_hdr header;
+ u8 insert_and_validate_checksum;
+};
+
+struct ext_host_tbl_yaps_table {
+ struct ext_host_tbl_tlv_hdr header;
+ struct mm81x_yaps_hw_table yaps_table;
+} __packed;
+
+struct ext_host_tbl {
+ __le32 ext_host_tbl_length;
+ u8 dev_mac_addr[6];
+ u8 ext_host_table_data_tlvs[];
+} __packed;
+
+int mm81x_fw_init(struct mm81x *mm, bool reset);
+int mm81x_fw_parse_ext_host_tbl(struct mm81x *mm);
+
+#endif /* !_MM81X_FW_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 11/35] wifi: mm81x: add hif.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/hif.h | 116 ++++++++++++++++++++
1 file changed, 116 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/hif.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/hif.h b/drivers/net/wireless/morsemicro/mm81x/hif.h
new file mode 100644
index 000000000000..73c23a39d14b
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/hif.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_HIF_H_
+#define _MM81X_HIF_H_
+
+#include "core.h"
+
+struct mm81x_skbq;
+
+#define MM81X_HIF_BYPASS_TX_STATUS_IRQ_NUM (15)
+#define MM81X_HIF_BYPASS_CMD_RESP_IRQ_NUM (29)
+#define MM81X_HIF_IRQ_BYPASS_TX_STATUS_AVAILABLE \
+ BIT(MM81X_HIF_BYPASS_TX_STATUS_IRQ_NUM)
+#define MM81X_HIF_IRQ_BYPASS_CMD_RESP_AVAILABLE \
+ BIT(MM81X_HIF_BYPASS_CMD_RESP_IRQ_NUM)
+
+/* Hardware IF interrupt mask. We may use any interrupts in this range */
+#define MM81X_HIF_IRQ_MASK_ALL \
+ (GENMASK(13, 0) | MM81X_HIF_IRQ_BYPASS_TX_STATUS_AVAILABLE | \
+ MM81X_HIF_IRQ_BYPASS_CMD_RESP_AVAILABLE)
+
+enum mm81x_hif_flags {
+ MM81X_HIF_FLAGS_DIR_TO_HOST = BIT(0),
+ MM81X_HIF_FLAGS_DIR_TO_CHIP = BIT(1),
+ MM81X_HIF_FLAGS_COMMAND = BIT(2),
+ MM81X_HIF_FLAGS_BEACON = BIT(3),
+ MM81X_HIF_FLAGS_DATA = BIT(4)
+};
+
+struct mm81x_hif_ops {
+ int (*init)(struct mm81x *mm);
+ void (*flush_tx_data)(struct mm81x *mm);
+ void (*flush_cmds)(struct mm81x *mm);
+ void (*finish)(struct mm81x *mm);
+ void (*skbq_get_tx_qs)(struct mm81x *mm, struct mm81x_skbq **qs,
+ int *num_qs);
+ struct mm81x_skbq *(*get_tx_cmd_queue)(struct mm81x *mm);
+ struct mm81x_skbq *(*get_tx_beacon_queue)(struct mm81x *mm);
+ struct mm81x_skbq *(*get_tx_mgmt_queue)(struct mm81x *mm);
+ struct mm81x_skbq *(*get_tx_data_queue)(struct mm81x *mm, int aci);
+ int (*handle_irq)(struct mm81x *mm, u32 status);
+ int (*get_tx_buffered_count)(struct mm81x *mm);
+ int (*get_tx_status_pending_count)(struct mm81x *mm);
+};
+
+static inline void mm81x_hif_clear_events(struct mm81x *mm)
+{
+ mm->hif.event_flags = 0;
+}
+
+static inline int mm81x_hif_init(struct mm81x *mm)
+{
+ return mm->hif.ops->init(mm);
+}
+
+static inline void mm81x_hif_flush_tx_data(struct mm81x *mm)
+{
+ mm->hif.ops->flush_tx_data(mm);
+}
+
+static inline void mm81x_hif_flush_cmds(struct mm81x *mm)
+{
+ mm->hif.ops->flush_cmds(mm);
+}
+
+static inline void mm81x_hif_finish(struct mm81x *mm)
+{
+ mm->hif.ops->finish(mm);
+}
+
+static inline void mm81x_hif_skbq_get_tx_qs(struct mm81x *mm,
+ struct mm81x_skbq **qs, int *num_qs)
+{
+ mm->hif.ops->skbq_get_tx_qs(mm, qs, num_qs);
+}
+
+static inline struct mm81x_skbq *mm81x_hif_get_tx_cmd_queue(struct mm81x *mm)
+{
+ return mm->hif.ops->get_tx_cmd_queue(mm);
+}
+
+static inline struct mm81x_skbq *mm81x_hif_get_tx_beacon_queue(struct mm81x *mm)
+{
+ return mm->hif.ops->get_tx_beacon_queue(mm);
+}
+
+static inline struct mm81x_skbq *mm81x_hif_get_tx_mgmt_queue(struct mm81x *mm)
+{
+ return mm->hif.ops->get_tx_mgmt_queue(mm);
+}
+
+static inline struct mm81x_skbq *mm81x_hif_get_tx_data_queue(struct mm81x *mm,
+ int aci)
+{
+ return mm->hif.ops->get_tx_data_queue(mm, aci);
+}
+
+static inline int mm81x_hif_handle_irq(struct mm81x *mm, u32 status)
+{
+ return mm->hif.ops->handle_irq(mm, status);
+}
+
+static inline int mm81x_hif_get_tx_buffered_count(struct mm81x *mm)
+{
+ return mm->hif.ops->get_tx_buffered_count(mm);
+}
+
+static inline int mm81x_hif_get_tx_status_pending_count(struct mm81x *mm)
+{
+ return mm->hif.ops->get_tx_status_pending_count(mm);
+}
+
+#endif /* _MM81X_HIF_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 12/35] wifi: mm81x: add hw.c
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/hw.c | 372 +++++++++++++++++++++
1 file changed, 372 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/hw.c
diff --git a/drivers/net/wireless/morsemicro/mm81x/hw.c b/drivers/net/wireless/morsemicro/mm81x/hw.c
new file mode 100644
index 000000000000..83cfc2c693af
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/hw.c
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+#include <linux/firmware.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include "hif.h"
+#include "debug.h"
+#include "mac.h"
+#include "bus.h"
+#include "core.h"
+#include "fw.h"
+#include "yaps.h"
+
+#define MM8108_REG_HOST_MAGIC_VALUE 0xDEADBEEF
+#define MM8108_REG_RESET_VALUE 0xDEAD
+
+#define MM8108_REG_SDIO_DEVICE_ADDR 0x0000207C
+
+#define MM8108_REG_SDIO_DEVICE_BURST_OFFSET 9
+#define MM8108_REG_TRGR_BASE 0x00003c00
+#define MM8108_REG_INT_BASE 0x00003c50
+#define MM8108_REG_MSI_ADDRESS 0x00004100
+#define MM8108_REG_MSI_VALUE 0x1
+#define MM8108_REG_MANIFEST_PTR_ADDRESS 0x00002d40
+#define MM8108_REG_APPS_BOOT_ADDR 0x00002084
+#define MM8108_REG_RESET 0x000020AC
+#define MM8108_REG_AON_COUNT 2
+
+#define MM8108_REG_AON_ADDR 0x00002114
+#define MM8108_REG_AON_LATCH_ADDR 0x00405020
+#define MM8108_REG_AON_LATCH_MASK 0x1
+#define MM8108_REG_AON_RESET_USB_VALUE 0x8
+#define MM8108_APPS_MAC_DMEM_ADDR_START 0x00100000
+
+#define MM8108_REG_RC_CLK_POWER_OFF_ADDR 0x00405020
+#define MM8108_REG_RC_CLK_POWER_OFF_MASK 0x00000040
+#define MM8108_SLOW_RC_POWER_ON_DELAY_MS 2
+
+#define MM8108_RESET_DELAY_TIME_MS 400
+
+#define MM8108_REG_OTPCTRL_PLDO 0x00004014
+#define MM8108_REG_OTPCTRL_PENVDD2 0x00004010
+#define MM8108_REG_OTPCTRL_PDSTB 0x00004018
+#define MM8108_REG_OTPCTRL_PTM 0x0000401c
+#define MM8108_REG_OTPCTRL_PCE 0x00004020
+#define MM8108_REG_OTPCTRL_PA 0x00004034
+#define MM8108_REG_OTPCTRL_PECCRDB 0x00004048
+#define MM8108_REG_OTPCTRL_ACTION_AUTO_RD_START 0x0000400c
+#define MM8108_REG_OTPCTRL_PDOUT 0x00004040
+
+#define MM81X_OTP_MAC_ADDR_2_BANK_NUM 27
+#define MM81X_OTP_MAC_ADDR_1_BANK_NUM 26
+#define MM81X_OTP_MAC_ADDR_1_MASK GENMASK(31, 16)
+#define MM81X_OTP_BOARD_TYPE_BANK_NUM 26
+#define MM81X_OTP_BOARD_TYPE_MASK GENMASK(15, 0)
+
+#define MM810X_BOARD_TYPE_MAX_VALUE (MM81X_OTP_BOARD_TYPE_MASK - 1)
+
+static void mm81x_hw_otp_power_up(struct mm81x *mm)
+{
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PENVDD2, 1);
+ udelay(2);
+
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PLDO, 1);
+ usleep_range(10, 20);
+
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PDSTB, 1);
+ udelay(3);
+}
+
+static void mm81x_hw_otp_power_down(struct mm81x *mm)
+{
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PDSTB, 0);
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PLDO, 0);
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PENVDD2, 0);
+}
+
+static void mm81x_hw_otp_read_enable(struct mm81x *mm)
+{
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PTM, 0);
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PCE, 1);
+ usleep_range(10, 20);
+}
+
+static void mm81x_hw_otp_read_disable(struct mm81x *mm)
+{
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PCE, 0);
+ udelay(1);
+}
+
+static int mm81x_hw_otp_read(struct mm81x *mm, u8 bank_num, u32 *buf,
+ u8 ignore_ecc)
+{
+ u32 auto_rd_start_tmp;
+ u32 auto_rd_start = 1;
+ int i;
+
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PA, bank_num);
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_PECCRDB, ignore_ecc);
+
+ mm81x_reg32_read(mm, MM8108_REG_OTPCTRL_ACTION_AUTO_RD_START,
+ &auto_rd_start_tmp);
+ auto_rd_start_tmp &= 0xfffffffe;
+
+ mm81x_reg32_write(mm, MM8108_REG_OTPCTRL_ACTION_AUTO_RD_START,
+ auto_rd_start | auto_rd_start_tmp);
+
+ /* Attempt reading up to 5 times. */
+ for (i = 0; i < 5 && auto_rd_start; i++) {
+ usleep_range(15, 20);
+ mm81x_reg32_read(mm, MM8108_REG_OTPCTRL_ACTION_AUTO_RD_START,
+ &auto_rd_start_tmp);
+ auto_rd_start = auto_rd_start_tmp & 0x1;
+ }
+
+ if (i == 5)
+ return -EIO;
+
+ mm81x_reg32_read(mm, MM8108_REG_OTPCTRL_PDOUT, buf);
+
+ return 0;
+}
+
+int mm81x_hw_otp_get_board_type(struct mm81x *mm)
+{
+ int board_type = 0;
+ u32 otp_word = 0;
+ int ret;
+
+ mm81x_claim_bus(mm);
+ mm81x_hw_otp_power_up(mm);
+ mm81x_hw_otp_read_enable(mm);
+
+ ret = mm81x_hw_otp_read(mm, MM81X_OTP_BOARD_TYPE_BANK_NUM, &otp_word,
+ 1);
+
+ mm81x_hw_otp_read_disable(mm);
+ mm81x_hw_otp_power_down(mm);
+ mm81x_release_bus(mm);
+
+ if (ret)
+ return -EINVAL;
+
+ board_type = otp_word & MM81X_OTP_BOARD_TYPE_MASK;
+
+ return board_type;
+}
+
+bool mm81x_hw_otp_valid_board_type(u32 board_type)
+{
+ return board_type > 0 && board_type < MM810X_BOARD_TYPE_MAX_VALUE;
+}
+
+int mm81x_hw_otp_get_mac_addr(struct mm81x *mm)
+{
+ u32 mac1 = 0;
+ u32 mac2 = 0;
+ int ret = 0;
+
+ mm81x_claim_bus(mm);
+ mm81x_hw_otp_power_up(mm);
+ mm81x_hw_otp_read_enable(mm);
+
+ ret = mm81x_hw_otp_read(mm, MM81X_OTP_MAC_ADDR_1_BANK_NUM, &mac1, 1);
+ if (ret)
+ goto exit;
+
+ ret = mm81x_hw_otp_read(mm, MM81X_OTP_MAC_ADDR_2_BANK_NUM, &mac2, 1);
+ if (ret)
+ goto exit;
+
+ *((u16 *)&mm->macaddr[0]) = (mac1 & MM81X_OTP_MAC_ADDR_1_MASK) >> 16;
+ *((u32 *)&mm->macaddr[2]) = mac2;
+
+exit:
+ mm81x_hw_otp_read_disable(mm);
+ mm81x_hw_otp_power_down(mm);
+ mm81x_release_bus(mm);
+
+ return ret;
+}
+
+void mm81x_hw_irq_enable(struct mm81x *mm, u32 irq, bool enable)
+{
+ u32 irq_en, irq_en_addr = irq < 32 ? MM81X_REG_INT1_EN(mm) :
+ MM81X_REG_INT2_EN(mm);
+ u32 irq_clr_addr = irq < 32 ? MM81X_REG_INT1_CLR(mm) :
+ MM81X_REG_INT2_CLR(mm);
+ u32 mask = irq < 32 ? (1 << irq) : (1 << (irq - 32));
+
+ mm81x_claim_bus(mm);
+ mm81x_reg32_read(mm, irq_en_addr, &irq_en);
+ if (enable)
+ irq_en |= (mask);
+ else
+ irq_en &= ~(mask);
+ mm81x_reg32_write(mm, irq_clr_addr, mask);
+ mm81x_reg32_write(mm, irq_en_addr, irq_en);
+ mm81x_release_bus(mm);
+}
+
+int mm81x_hw_irq_handle(struct mm81x *mm)
+{
+ u32 status1 = 0;
+
+ mm81x_reg32_read(mm, MM81X_REG_INT1_STS(mm), &status1);
+
+ if (status1 & MM81X_HIF_IRQ_MASK_ALL)
+ mm81x_hif_handle_irq(mm, status1);
+
+ if (status1 & MM81X_INT_BEACON_VIF_MASK_ALL)
+ mm81x_mac_beacon_irq_handle(mm, status1);
+
+ mm81x_reg32_write(mm, MM81X_REG_INT1_CLR(mm), status1);
+
+ return status1 ? 1 : 0;
+}
+
+void mm81x_hw_irq_clear(struct mm81x *mm)
+{
+ mm81x_claim_bus(mm);
+ mm81x_reg32_write(mm, MM81X_REG_INT1_CLR(mm), 0xFFFFFFFF);
+ mm81x_reg32_write(mm, MM81X_REG_INT2_CLR(mm), 0xFFFFFFFF);
+ mm81x_release_bus(mm);
+}
+
+int mm81x_hw_toggle_aon_latch(struct mm81x *mm)
+{
+ u32 address = MM81X_REG_AON_LATCH_ADDR(mm);
+ u32 mask = MM81X_REG_AON_LATCH_MASK(mm);
+ u32 latch;
+
+ if (address) {
+ mm81x_reg32_read(mm, address, &latch);
+ mm81x_reg32_write(mm, address, latch & ~(mask));
+ mdelay(5);
+ mm81x_reg32_write(mm, address, latch | mask);
+ mdelay(5);
+ mm81x_reg32_write(mm, address, latch & ~(mask));
+ mdelay(5);
+ }
+
+ return 0;
+}
+
+void mm81x_hw_enable_stop_notifications(struct mm81x *mm, bool enable)
+{
+ mm81x_hw_irq_enable(mm, MM81X_INT_HW_STOP_NOTIFICATION_NUM, enable);
+}
+
+void mm81x_hw_enable_burst_mode(struct mm81x *mm, const u8 burst_mode)
+{
+ u32 reg32_value;
+
+ mm81x_claim_bus(mm);
+ if (mm81x_reg32_read(mm, MM8108_REG_SDIO_DEVICE_ADDR, ®32_value))
+ goto end;
+
+ reg32_value &= ~(u32)(SDIO_WORD_BURST_MASK
+ << MM8108_REG_SDIO_DEVICE_BURST_OFFSET);
+ reg32_value |= (u32)(burst_mode << MM8108_REG_SDIO_DEVICE_BURST_OFFSET);
+
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "Setting Burst mode to %d Writing 0x%08X to the register",
+ burst_mode, reg32_value);
+
+ if (mm81x_reg32_write(mm, MM8108_REG_SDIO_DEVICE_ADDR, reg32_value))
+ goto end;
+
+end:
+ mm81x_release_bus(mm);
+}
+
+static int mm81x_hw_enable_internal_slow_clock(struct mm81x *mm)
+{
+ u32 rc_clock_reg_value;
+ int ret = 0;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "Enabling internal slow clock");
+
+ ret = mm81x_reg32_read(mm, MM8108_REG_RC_CLK_POWER_OFF_ADDR,
+ &rc_clock_reg_value);
+ if (ret)
+ goto exit;
+
+ rc_clock_reg_value &= ~MM8108_REG_RC_CLK_POWER_OFF_MASK;
+ ret = mm81x_reg32_write(mm, MM8108_REG_RC_CLK_POWER_OFF_ADDR,
+ rc_clock_reg_value);
+ if (ret)
+ goto exit;
+
+ ret = mm81x_hw_toggle_aon_latch(mm);
+ if (ret)
+ goto exit;
+
+ /* Wait for the clock to turn on and settle */
+ mdelay(MM8108_SLOW_RC_POWER_ON_DELAY_MS);
+exit:
+ return ret;
+}
+
+int mm81x_hw_digital_reset(struct mm81x *mm)
+{
+ int ret = 0;
+
+ mm81x_claim_bus(mm);
+
+ /* This should be the first step in digital reset, do not reorder */
+ ret = mm81x_hw_enable_internal_slow_clock(mm);
+ if (ret)
+ goto exit;
+
+ if (mm->bus_type == MM81X_BUS_TYPE_USB) {
+#ifdef CONFIG_MM81X_USB
+ ret = mm81x_usb_ndr_reset(mm);
+#endif
+ goto usb_done;
+ }
+
+ if (MM81X_REG_RESET(mm) != 0)
+ ret = mm81x_reg32_write(mm, MM81X_REG_RESET(mm),
+ MM81X_REG_RESET_VALUE(mm));
+
+usb_done:
+ msleep(MM8108_RESET_DELAY_TIME_MS);
+exit:
+ mm81x_release_bus(mm);
+
+ if (!ret)
+ mm->chip_was_reset = true;
+
+ return ret;
+}
+
+void mm81x_hw_pre_firmware_ndr_hook(struct mm81x *mm)
+{
+ /* We need disable bursting for firmware download/init procedure */
+ mm81x_bus_config_burst_mode(mm, false);
+}
+
+void mm81x_hw_post_firmware_ndr_hook(struct mm81x *mm)
+{
+ /* We are safe here to reenable bursting again, if supported */
+ mm81x_bus_config_burst_mode(mm, true);
+}
+
+const struct mm81x_regs mm8108_regs = {
+ .chip_id_address = MM8108_REG_CHIP_ID,
+ .irq_base_address = MM8108_REG_INT_BASE,
+ .trgr_base_address = MM8108_REG_TRGR_BASE,
+ .cpu_reset_address = MM8108_REG_RESET,
+ .cpu_reset_value = MM8108_REG_RESET_VALUE,
+ .manifest_ptr_address = MM8108_REG_MANIFEST_PTR_ADDRESS,
+ .msi_address = MM8108_REG_MSI_ADDRESS,
+ .msi_value = MM8108_REG_MSI_VALUE,
+ .magic_num_value = MM8108_REG_HOST_MAGIC_VALUE,
+ .early_clk_ctrl_value = 0,
+ .pager_base_address = MM8108_APPS_MAC_DMEM_ADDR_START,
+ .aon_latch = MM8108_REG_AON_LATCH_ADDR,
+ .aon_latch_mask = MM8108_REG_AON_LATCH_MASK,
+ .aon_reset_usb_value = MM8108_REG_AON_RESET_USB_VALUE,
+ .aon = MM8108_REG_AON_ADDR,
+ .aon_count = MM8108_REG_AON_COUNT,
+ .boot_address = MM8108_REG_APPS_BOOT_ADDR,
+};
+
+/* B2 ROM_LINKED */
+MODULE_FIRMWARE(MM81X_FW_DIR "/" MM8108_FW_BASE MM8108B2_REV_STRING
+ FW_ROM_LINKED_STRING MM81X_FW_EXT);
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 13/35] wifi: mm81x: add hw.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/hw.h | 175 +++++++++++++++++++++
1 file changed, 175 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/hw.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/hw.h b/drivers/net/wireless/morsemicro/mm81x/hw.h
new file mode 100644
index 000000000000..3087bd9c73b0
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/hw.h
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_HW_H_
+#define _MM81X_HW_H_
+
+#include <linux/gpio/consumer.h>
+#include "core.h"
+#include "command_defs.h"
+
+/* This should be at a fixed location for a family of chipset */
+#define MM8108_REG_CHIP_ID 0x00002d20
+
+#define MM81X_SDIO_RW_ADDR_BOUNDARY_MASK ((u32)0xFFFF0000)
+
+#define MM81X_CONFIG_ACCESS_1BYTE 0
+#define MM81X_CONFIG_ACCESS_2BYTE 1
+#define MM81X_CONFIG_ACCESS_4BYTE 2
+
+#define MM81X_REG_TRGR_BASE(mm) ((mm)->regs->trgr_base_address)
+#define MM81X_REG_TRGR1_STS(mm) (MM81X_REG_TRGR_BASE(mm) + 0x00)
+#define MM81X_REG_TRGR1_SET(mm) (MM81X_REG_TRGR_BASE(mm) + 0x04)
+#define MM81X_REG_TRGR1_CLR(mm) (MM81X_REG_TRGR_BASE(mm) + 0x08)
+#define MM81X_REG_TRGR1_EN(mm) (MM81X_REG_TRGR_BASE(mm) + 0x0C)
+#define MM81X_REG_TRGR2_STS(mm) (MM81X_REG_TRGR_BASE(mm) + 0x10)
+#define MM81X_REG_TRGR2_SET(mm) (MM81X_REG_TRGR_BASE(mm) + 0x14)
+#define MM81X_REG_TRGR2_CLR(mm) (MM81X_REG_TRGR_BASE(mm) + 0x18)
+#define MM81X_REG_TRGR2_EN(mm) (MM81X_REG_TRGR_BASE(mm) + 0x1C)
+
+#define MM81X_REG_INT_BASE(mm) ((mm)->regs->irq_base_address)
+#define MM81X_REG_INT1_STS(mm) (MM81X_REG_INT_BASE(mm) + 0x00)
+#define MM81X_REG_INT1_SET(mm) (MM81X_REG_INT_BASE(mm) + 0x04)
+#define MM81X_REG_INT1_CLR(mm) (MM81X_REG_INT_BASE(mm) + 0x08)
+#define MM81X_REG_INT1_EN(mm) (MM81X_REG_INT_BASE(mm) + 0x0C)
+#define MM81X_REG_INT2_STS(mm) (MM81X_REG_INT_BASE(mm) + 0x10)
+#define MM81X_REG_INT2_SET(mm) (MM81X_REG_INT_BASE(mm) + 0x14)
+#define MM81X_REG_INT2_CLR(mm) (MM81X_REG_INT_BASE(mm) + 0x18)
+#define MM81X_REG_INT2_EN(mm) (MM81X_REG_INT_BASE(mm) + 0x1C)
+
+#define MM81X_REG_CHIP_ID(mm) ((mm)->regs->chip_id_address)
+
+#define MM81X_REG_MSI(mm) ((mm)->regs->msi_address)
+#define MM81X_REG_MSI_HOST_INT(mm) ((mm)->regs->msi_value)
+
+#define MM81X_REG_HOST_MAGIC_VALUE(mm) ((mm)->regs->magic_num_value)
+
+#define MM81X_REG_RESET(mm) ((mm)->regs->cpu_reset_address)
+#define MM81X_REG_RESET_VALUE(mm) ((mm)->regs->cpu_reset_value)
+
+#define MM81X_REG_HOST_MANIFEST_PTR(mm) ((mm)->regs->manifest_ptr_address)
+
+#define MM81X_REG_EARLY_CLK_CTRL_VALUE(mm) ((mm)->regs->early_clk_ctrl_value)
+
+#define MM81X_REG_CLK_CTRL(mm) ((mm)->regs->clk_ctrl_address)
+#define MM81X_REG_CLK_CTRL_VALUE(mm) ((mm)->regs->clk_ctrl_value)
+
+#define MM81X_REG_BOOT_ADDR(mm) ((mm)->regs->boot_address)
+#define MM81X_REG_BOOT_ADDR_VALUE(mm) ((mm)->regs->boot_value)
+
+#define MM81X_REG_AON_ADDR(mm) ((mm)->regs->aon)
+#define MM81X_REG_AON_COUNT(mm) ((mm)->regs->aon_count)
+#define MM81X_REG_AON_LATCH_ADDR(mm) ((mm)->regs->aon_latch)
+#define MM81X_REG_AON_LATCH_MASK(mm) ((mm)->regs->aon_latch_mask)
+#define MM81X_REG_AON_USB_RESET(mm) ((mm)->regs->aon_reset_usb_value)
+
+/* Bit 17 to 24 reserved for the beacon VIF 0 to 7 interrupts */
+#define MM81X_INT_BEACON_VIF_MASK_ALL (GENMASK(24, 17))
+#define MM81X_INT_BEACON_BASE_NUM (17)
+
+/* PV0 NDP probe interrupts (VIF 0 and 1). */
+#define MM81X_INT_NDP_PROBE_REQ_PV0_VIF_MASK_ALL (GENMASK(26, 25))
+#define MM81X_INT_NDP_PROBE_REQ_PV0_BASE_NUM (25)
+
+/* Bit 27 Chip to Host stop notify */
+#define MM81X_INT_HW_STOP_NOTIFICATION_NUM (27)
+#define MM81X_INT_HW_STOP_NOTIFICATION BIT(MM81X_INT_HW_STOP_NOTIFICATION_NUM)
+
+#define CHIP_TYPE_SILICON 0x0
+
+/* Chip ID */
+#define MM8108XX_ID 0x9
+
+/* Chip Rev */
+#define MM8108B2_REV 0x8
+
+/* Chip Rev String */
+#define MM8108B_STRING "b"
+#define MM8108B2_REV_STRING MM8108B_STRING "2"
+
+/* Chip ID for MM8108 */
+#define MM8108B2_ID \
+ MM81X_DEVICE_ID(MM8108XX_ID, MM8108B2_REV, CHIP_TYPE_SILICON)
+
+#define FW_RAM_ONLY_STRING ""
+#define FW_ROM_LINKED_STRING "-rl"
+#define FW_ROM_ALL_STRING "-ro"
+
+/*
+ * Minimum time we must wait between attempting to reload the HW after a
+ * stop notification
+ */
+#define HW_RELOAD_AFTER_STOP_WINDOW 5
+
+enum host_table_firmware_flags {
+ MM81X_FW_FLAGS_SUPPORT_S1G = BIT(0),
+ MM81X_FW_FLAGS_BUSY_ACTIVE_LOW = BIT(1),
+ MM81X_FW_FLAGS_REPORTS_TX_BEACON_COMPLETION = BIT(2),
+ MM81X_FW_FLAGS_SUPPORT_HW_SCAN = BIT(3),
+ MM81X_FW_FLAGS_SUPPORT_CHIP_HALT_IRQ = BIT(4),
+};
+
+struct host_table {
+ __le32 magic_number;
+ __le32 fw_version_number;
+ __le32 host_flags;
+ __le32 firmware_flags;
+ __le32 memcmd_cmd_addr;
+ __le32 memcmd_resp_addr;
+ __le32 ext_host_tbl_addr;
+} __packed;
+
+struct mm81x_regs {
+ u32 chip_id_address;
+ u32 irq_base_address;
+ u32 trgr_base_address;
+ u32 cpu_reset_address;
+ u32 cpu_reset_value;
+ u32 msi_address;
+ u32 msi_value;
+ u32 manifest_ptr_address;
+ u32 magic_num_value;
+ u32 clk_ctrl_address;
+ u32 clk_ctrl_value;
+ u32 early_clk_ctrl_value;
+ u32 boot_address;
+ u32 boot_value;
+ u32 pager_base_address;
+ u32 aon_latch;
+ u32 aon_latch_mask;
+ u32 aon_reset_usb_value;
+ u32 aon;
+ u8 aon_count;
+};
+
+int mm81x_hw_otp_get_board_type(struct mm81x *mm);
+bool mm81x_hw_otp_valid_board_type(u32 board_type);
+int mm81x_hw_otp_get_mac_addr(struct mm81x *mm);
+
+void mm81x_hw_irq_enable(struct mm81x *mm, u32 irq, bool enable);
+int mm81x_hw_irq_handle(struct mm81x *mm);
+void mm81x_hw_irq_clear(struct mm81x *mm);
+int mm81x_hw_toggle_aon_latch(struct mm81x *mm);
+void mm81x_hw_enable_burst_mode(struct mm81x *mm, const u8 burst_mode);
+int mm81x_hw_digital_reset(struct mm81x *mm);
+void mm81x_hw_pre_firmware_ndr_hook(struct mm81x *mm);
+void mm81x_hw_post_firmware_ndr_hook(struct mm81x *mm);
+
+enum sdio_burst_mode {
+ SDIO_WORD_BURST_DISABLE =
+ 0, /* Intentionally duplicate to make it clear it's disabled */
+ SDIO_WORD_BURST_SIZE_0 = 0, /* 000: no bursting (single 32bit word) */
+ SDIO_WORD_BURST_SIZE_2 = 1, /* 001: bursts of 2 words */
+ SDIO_WORD_BURST_SIZE_4 = 2, /* 010: bursts of 4 words */
+ SDIO_WORD_BURST_SIZE_8 = 3, /* 011: bursts of 8 words */
+ SDIO_WORD_BURST_SIZE_16 = 4, /* 100: bursts of 16 words */
+ SDIO_WORD_BURST_MASK = 7,
+};
+
+extern const struct mm81x_regs mm8108_regs;
+
+void mm81x_hw_enable_stop_notifications(struct mm81x *mm, bool enable);
+
+#endif /* !_MM81X_HW_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 14/35] wifi: mm81x: add mac.c
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge,
Nathan Chancellor, Nick Desaulniers, Bill Wendling, Justin Stitt
Cc: ayman.grais, linux-wireless, linux-kernel, llvm
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/mac.c | 2642 +++++++++++++++++++
1 file changed, 2642 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/mac.c
diff --git a/drivers/net/wireless/morsemicro/mm81x/mac.c b/drivers/net/wireless/morsemicro/mm81x/mac.c
new file mode 100644
index 000000000000..2465a99c8048
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/mac.c
@@ -0,0 +1,2642 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+#include "core.h"
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/crc32.h>
+#include <net/mac80211.h>
+#include <asm/div64.h>
+#include <linux/kernel.h>
+#include "hif.h"
+#include "mac.h"
+#include "bus.h"
+#include "ps.h"
+#include "debug.h"
+#include "rc.h"
+
+/*
+ * Arbitrary size limit for the filter command address list, to ensure that
+ * the command does not exceed page/MTU size. This will be far greater than
+ * the number of filters supported by the firmware.
+ */
+#define MCAST_FILTER_COUNT_MAX (1024 / sizeof(filter->addr_list[0]))
+
+/* Calculate average RSSI for Rx status */
+#define CALC_AVG_RSSI(_avg, _sample) ((((_avg) * 9 + (_sample)) / 10))
+
+/*
+ * When automatically trying MCS0 before MCS10, this is how many
+ * MCS0 attempts to make
+ */
+#define MCS0_BEFORE_MCS10_COUNT (1)
+
+/* Maximum TX power (default) */
+#define MAX_TX_POWER_MBM (2200)
+
+/* Default queue count */
+#define MM81X_HW_QUEUE_COUNT (4)
+
+/* Max rates per skb */
+#define MM81X_HW_MAX_RATES (4)
+
+/* Max reported rates */
+#define MM81X_HW_MAX_REPORT_RATES (4)
+
+/* Max rate attempts */
+#define MM81X_HW_MAX_RATE_TRIES (1)
+
+/* Max sk pacing shift */
+#define MM81X_HW_TX_SK_PACING_SHIFT (3)
+
+/* NSS/MCS map values */
+#define MM81X_NSS_MCS_BYTE_0 0xfe /* 1SS */
+#define MM81X_NSS_MCS_BYTE_1 0x00
+#define MM81X_NSS_MCS_BYTE_2 0xfc /* 1SS */
+#define MM81X_NSS_MCS_BYTE_3 0x01
+#define MM81X_NSS_MCS_BYTE_4 0x00
+
+/* HW restart delay time before terminating hardware IF work items */
+#define MM81X_HW_RESTART_DELAY_MS 20
+
+/* clang-format off */
+
+/* mm81x chips do not support 16MHz */
+#define CHANS1G(channel, frequency, offset) \
+{ \
+ .band = NL80211_BAND_S1GHZ, \
+ .center_freq = (frequency), \
+ .freq_offset = (offset), \
+ .hw_value = (channel), \
+ .flags = IEEE80211_CHAN_NO_16MHZ, \
+ .max_antenna_gain = 0, \
+ .max_power = 30, \
+}
+
+static struct ieee80211_channel mm_s1ghz_channels[] = {
+ CHANS1G(1, 902, 500),
+ CHANS1G(3, 903, 500),
+ CHANS1G(5, 904, 500),
+ CHANS1G(7, 905, 500),
+ CHANS1G(9, 906, 500),
+ CHANS1G(11, 907, 500),
+ CHANS1G(13, 908, 500),
+ CHANS1G(15, 909, 500),
+ CHANS1G(17, 910, 500),
+ CHANS1G(19, 911, 500),
+ CHANS1G(21, 912, 500),
+ CHANS1G(23, 913, 500),
+ CHANS1G(25, 914, 500),
+ CHANS1G(27, 915, 500),
+ CHANS1G(29, 916, 500),
+ CHANS1G(31, 917, 500),
+ CHANS1G(33, 918, 500),
+ CHANS1G(35, 919, 500),
+ CHANS1G(37, 920, 500),
+ CHANS1G(39, 921, 500),
+ CHANS1G(41, 922, 500),
+ CHANS1G(43, 923, 500),
+ CHANS1G(45, 924, 500),
+ CHANS1G(47, 925, 500),
+ CHANS1G(49, 926, 500),
+ CHANS1G(51, 927, 500),
+};
+
+/* clang-format on */
+
+static struct ieee80211_supported_band mm_band_s1ghz = {
+ .band = NL80211_BAND_S1GHZ,
+ .s1g_cap.s1g = true,
+ .channels = mm_s1ghz_channels,
+ .n_channels = ARRAY_SIZE(mm_s1ghz_channels),
+ .bitrates = NULL,
+ .n_bitrates = 0,
+ .s1g_cap.cap[4] = 0x80 /* STA type sensor only for AP & STA */
+};
+
+static struct ieee80211_iface_limit mm_if_limits[] = {
+ {
+ .max = MM81X_MAX_IF,
+ .types = BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP),
+ },
+};
+
+static struct ieee80211_iface_combination mm_if_combs[] = {
+ {
+ .limits = mm_if_limits,
+ .n_limits = ARRAY_SIZE(mm_if_limits),
+ .max_interfaces = MM81X_MAX_IF,
+ .num_different_channels = 1,
+ },
+};
+
+/* Convert from a time in time units (1024us) to us */
+#define MM81X_TU_TO_US(x) ((x) * 1024UL)
+
+/* Convert from a time in time units (1024us) to ms */
+#define MM81X_TU_TO_MS(x) (MM81X_TU_TO_US(x) / 1000UL)
+
+/* Default time to dwell on a scan channel */
+#define MM81X_HWSCAN_DEFAULT_DWELL_TIME_MS (30)
+
+/* Default time to dwell on a scan channel for passive scan */
+#define MM81X_HWSCAN_DEFAULT_PASSIVE_DWELL_TIME_MS (110)
+
+/* Default time to dwell on home channel, in between scan channels */
+#define MM81X_HWSCAN_DEFAULT_DWELL_ON_HOME_MS (200)
+
+/* Typical time it takes to send the probe */
+#define MM81X_HWSCAN_PROBE_DELAY_MS (30)
+
+/* A margin to account for event/command processing */
+#define MM81X_HWSCAN_TIMEOUT_OVERHEAD_MS (2000)
+
+/* Scan channel frequency mask */
+#define HW_SCAN_CH_LIST_FREQ_KHZ GENMASK(19, 0)
+
+/*
+ * Scan channel bandwidth mask.
+ * Encoded as: 0 = 1MHz, 1 = 2MHz, 2 = 4MHz, 3 = 8MHz
+ */
+#define HW_SCAN_CH_LIST_OP_BW GENMASK(21, 20)
+
+/*
+ * Scan channel primary channel width.
+ * Encoded as: 0 = 1MHz, 1 = 2MHz
+ */
+#define HW_SCAN_CH_LIST_PRIM_CH_WIDTH BIT(22)
+
+/* Index into power_list for tx power of channel */
+#define HW_SCAN_CH_LIST_PWR_LIST_IDX GENMASK(31, 26)
+
+struct hw_scan_tlv_hdr {
+ __le16 tag;
+ __le16 len;
+} __packed;
+
+struct hw_scan_tlv_channel_list {
+ struct hw_scan_tlv_hdr hdr;
+ __le32 channels[];
+} __packed;
+
+struct hw_scan_tlv_power_list {
+ struct hw_scan_tlv_hdr hdr;
+ s32 tx_power_qdbm[];
+} __packed;
+
+struct hw_scan_tlv_probe_req {
+ struct hw_scan_tlv_hdr hdr;
+ /* Probe request frame template (including SSIDs) */
+ u8 buf[];
+} __packed;
+
+struct hw_scan_tlv_dwell_on_home {
+ struct hw_scan_tlv_hdr hdr;
+ /* Time to dwell on home between scan channels */
+ __le32 home_dwell_time_ms;
+} __packed;
+
+#define DOT11AH_BA_MAX_MPDU_PER_AMPDU (32)
+
+/* wiphy scan params */
+#define MM81X_MAX_SCAN_IE_LEN 512
+#define MM81X_MAX_SCAN_SSIDS 1
+#define MM81X_MAX_REMAIN_ON_CHAN_DURATION 10000
+
+static int mm81x_tx_h_get_prim_bw(struct cfg80211_chan_def *chandef)
+{
+ return chandef->s1g_primary_2mhz ? 2 : 1;
+}
+
+static bool mm81x_reg_h_cc_equal(const char *cc1, const char *cc2)
+{
+ return (cc1[0] == cc2[0]) && (cc1[1] == cc2[1]);
+}
+
+static bool mm81x_tx_h_pkt_over_rts_threshold(struct mm81x *mm,
+ struct ieee80211_tx_info *info,
+ struct sk_buff *skb)
+{
+ u8 ccmp_len;
+
+ if (!info->control.hw_key)
+ return ((skb->len + FCS_LEN) > mm->rts_threshold);
+
+ if (info->control.hw_key->keylen == 32)
+ ccmp_len =
+ IEEE80211_CCMP_256_HDR_LEN + IEEE80211_CCMP_256_MIC_LEN;
+ else if (info->control.hw_key->keylen == 16)
+ ccmp_len = IEEE80211_CCMP_HDR_LEN + IEEE80211_CCMP_MIC_LEN;
+ else
+ ccmp_len = 0;
+
+ return ((skb->len + FCS_LEN + ccmp_len) > mm->rts_threshold);
+}
+
+static bool mm81x_tx_h_ps_filtered_for_sta(struct mm81x *mm,
+ struct sk_buff *skb,
+ struct ieee80211_sta *sta)
+{
+ struct mm81x_sta *mm_sta;
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+
+ if (!sta)
+ return false;
+
+ mm_sta = (struct mm81x_sta *)sta->drv_priv;
+
+ if (!mm_sta->tx_ps_filter_en)
+ return false;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "Frame for sta[%pM] PS filtered",
+ mm_sta->addr);
+
+ info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
+ info->flags &= ~IEEE80211_TX_CTL_AMPDU;
+
+ ieee80211_tx_status_skb(mm->hw, skb);
+ return true;
+}
+
+static void mm81x_mac_check_fw_disabled_chans(struct ieee80211_hw *hw)
+{
+ int ret = 0;
+ u32 i;
+ struct mm81x *mm = hw->priv;
+ struct host_cmd_resp_get_disabled_channels *resp;
+ u32 resp_len = sizeof(struct host_cmd_disabled_channel_entry) *
+ ARRAY_SIZE(mm_s1ghz_channels) +
+ sizeof(*resp);
+
+ lockdep_assert_held(&mm->lock);
+
+ resp = kzalloc(resp_len, GFP_KERNEL);
+ if (!resp) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = mm81x_cmd_get_disabled_channels(mm, resp, resp_len);
+ if (ret)
+ goto out;
+
+ for (i = 0; i < ARRAY_SIZE(mm_s1ghz_channels); i++) {
+ struct ieee80211_channel *ch = &mm_s1ghz_channels[i];
+
+ if (ch->flags & IEEE80211_CHAN_DISABLED)
+ continue;
+
+ ch->flags &= ~IEEE80211_CHAN_S1G_NO_PRIMARY;
+ }
+
+ for (i = 0; i < le32_to_cpu(resp->n_channels); i++) {
+ struct ieee80211_channel *ch;
+ struct host_cmd_disabled_channel_entry *entry =
+ &resp->channels[i];
+
+ if (entry->bw_mhz != 1)
+ continue;
+
+ ch = ieee80211_get_channel_khz(
+ hw->wiphy,
+ KHZ100_TO_KHZ(le16_to_cpu(entry->freq_100khz)));
+ if (!ch)
+ continue;
+
+ ch->flags |= IEEE80211_CHAN_S1G_NO_PRIMARY;
+ mm81x_dbg(mm, MM81X_DBG_MAC, "set NO_PRIMARY on %u KHz",
+ ieee80211_channel_to_khz(ch));
+ }
+
+out:
+ if (ret)
+ mm81x_err(mm, "failed to set disabled primary channels");
+
+ kfree(resp);
+}
+
+static int mm81x_mac_ops_start(struct ieee80211_hw *hw)
+{
+ struct mm81x *mm = hw->priv;
+
+ mm->started = true;
+ return 0;
+}
+
+static int mm81x_tx_h_get_max_bw(struct mm81x *mm)
+{
+ return MM81X_FW_SUPP(&mm->fw_caps, 8MHZ) ? 8 :
+ MM81X_FW_SUPP(&mm->fw_caps, 4MHZ) ? 4 :
+ MM81X_FW_SUPP(&mm->fw_caps, 2MHZ) ? 2 :
+ 1;
+}
+
+static void mm81x_mac_caps_init(struct mm81x *mm)
+{
+ struct mm81x_fw_caps *fw_caps = &mm->fw_caps;
+ struct ieee80211_sta_s1g_cap *s1g = &mm_band_s1ghz.s1g_cap;
+
+#define __FW_CAP_N(_n, _cap, _bit) \
+ do { \
+ if (MM81X_FW_SUPP(fw_caps, _cap)) \
+ s1g->cap[_n] |= (_bit); \
+ } while (0)
+
+#define FW_CAP0(_cap, _bit) __FW_CAP_N(0, _cap, _bit)
+#define FW_CAP3(_cap, _bit) __FW_CAP_N(3, _cap, _bit)
+#define FW_CAP5(_cap, _bit) __FW_CAP_N(5, _cap, _bit)
+#define FW_CAP6(_cap, _bit) __FW_CAP_N(6, _cap, _bit)
+#define FW_CAP7(_cap, _bit) __FW_CAP_N(7, _cap, _bit)
+#define FW_CAP8(_cap, _bit) __FW_CAP_N(8, _cap, _bit)
+#define FW_CAP9(_cap, _bit) __FW_CAP_N(9, _cap, _bit)
+
+ FW_CAP0(S1G_LONG, S1G_CAP0_S1G_LONG);
+
+ s1g->cap[0] |= S1G_CAP0_SGI_1MHZ;
+ if (MM81X_FW_SUPP(fw_caps, SGI)) {
+ FW_CAP0(2MHZ, S1G_CAP0_SGI_2MHZ);
+ FW_CAP0(4MHZ, S1G_CAP0_SGI_4MHZ);
+ FW_CAP0(8MHZ, S1G_CAP0_SGI_8MHZ);
+ }
+
+ if (MM81X_FW_SUPP(fw_caps, 8MHZ))
+ s1g->cap[0] |= S1G_SUPP_CH_WIDTH_8;
+ else if (MM81X_FW_SUPP(fw_caps, 4MHZ))
+ s1g->cap[0] |= S1G_SUPP_CH_WIDTH_4;
+ else if (MM81X_FW_SUPP(fw_caps, 2MHZ))
+ s1g->cap[0] |= S1G_SUPP_CH_WIDTH_2;
+
+ FW_CAP3(RD_RESPONDER, S1G_CAP3_RD_RESPONDER);
+ FW_CAP3(LONG_MPDU, S1G_CAP3_MAX_MPDU_LEN);
+
+ FW_CAP5(AMSDU, S1G_CAP5_AMSDU);
+ FW_CAP5(AMPDU, S1G_CAP5_AMPDU);
+ FW_CAP5(ASYMMETRIC_BA_SUPPORT, S1G_CAP5_ASYMMETRIC_BA);
+ FW_CAP5(FLOW_CONTROL, S1G_CAP5_FLOW_CONTROL);
+
+ FW_CAP6(OBSS_MITIGATION, S1G_CAP6_OBSS_MITIGATION);
+ FW_CAP6(FRAGMENT_BA, S1G_CAP6_FRAGMENT_BA);
+ FW_CAP6(NDP_PSPOLL, S1G_CAP6_NDP_PS_POLL);
+ FW_CAP6(TXOP_SHARING_IMPLICIT_ACK, S1G_CAP6_TXOP_SHARING_IMP_ACK);
+ FW_CAP6(HTC_VHT_MFB, S1G_CAP6_VHT_LINK_ADAPT);
+
+ FW_CAP7(TACK_AS_PSPOLL, S1G_CAP7_TACK_AS_PS_POLL);
+ FW_CAP7(DUPLICATE_1MHZ, S1G_CAP7_DUP_1MHZ);
+ FW_CAP7(MCS_NEGOTIATION, S1G_CAP7_MCS_NEGOTIATION);
+ FW_CAP7(1MHZ_CONTROL_RESPONSE_PREAMBLE,
+ S1G_CAP7_1MHZ_CTL_RESPONSE_PREAMBLE);
+ FW_CAP7(SECTOR_TRAINING, S1G_CAP7_SECTOR_TRAINING_OPERATION);
+ FW_CAP7(TMP_PS_MODE_SWITCH, S1G_CAP7_TEMP_PS_MODE_SWITCH);
+
+ FW_CAP8(BDT, S1G_CAP8_BDT);
+
+ FW_CAP9(LINK_ADAPTATION_WO_NDP_CMAC,
+ S1G_CAP9_LINK_ADAPT_PER_CONTROL_RESPONSE);
+
+ /* 1SS MCS 9 for Rx / Tx map */
+ s1g->nss_mcs[0] = MM81X_NSS_MCS_BYTE_0;
+ s1g->nss_mcs[1] = MM81X_NSS_MCS_BYTE_1;
+ s1g->nss_mcs[2] = MM81X_NSS_MCS_BYTE_2;
+ s1g->nss_mcs[3] = MM81X_NSS_MCS_BYTE_3;
+ s1g->nss_mcs[4] = MM81X_NSS_MCS_BYTE_4;
+
+#undef FW_CAP0
+#undef FW_CAP3
+#undef FW_CAP5
+#undef FW_CAP6
+#undef FW_CAP7
+#undef FW_CAP8
+#undef FW_CAP9
+#undef __FW_CAP_N
+}
+
+static void mm81x_mac_beacon_irq_enable(struct mm81x_vif *mm_vif, bool enable)
+{
+ struct mm81x *mm = mm81x_vif_to_mm(mm_vif);
+ u8 beacon_irq_num = MM81X_INT_BEACON_BASE_NUM + mm_vif->id;
+
+ enable ? set_bit(beacon_irq_num, &mm->beacon_irqs_enabled) :
+ clear_bit(beacon_irq_num, &mm->beacon_irqs_enabled);
+
+ mm81x_hw_irq_enable(mm, beacon_irq_num, enable);
+}
+
+static void mm81x_beacon_h_fill_tx_info(struct mm81x *mm,
+ struct mm81x_skb_tx_info *tx_info,
+ struct mm81x_vif *mm_vif, int tx_bw_mhz)
+{
+ enum dot11_bandwidth bw_idx =
+ mm81x_ratecode_bw_mhz_to_bw_index(tx_bw_mhz);
+ enum mm81x_rate_preamble pream = MM81X_RATE_PREAMBLE_S1G_SHORT;
+
+ tx_info->flags |=
+ cpu_to_le32(MM81X_TX_CONF_FLAGS_VIF_ID_SET(mm_vif->id));
+
+ if (bw_idx == DOT11_BANDWIDTH_1MHZ)
+ pream = MM81X_RATE_PREAMBLE_S1G_1M;
+
+ tx_info->rates[0].count = 1;
+ tx_info->rates[1].count = 0;
+ tx_info->rates[0].mm81x_ratecode =
+ mm81x_ratecode_init(bw_idx, 0, 0, pream);
+
+ if (mm->firmware_flags & MM81X_FW_FLAGS_REPORTS_TX_BEACON_COMPLETION)
+ tx_info->flags |=
+ cpu_to_le32(MM81X_TX_CONF_FLAGS_IMMEDIATE_REPORT);
+}
+
+static void mm81x_mac_beacon_tasklet(unsigned long data)
+{
+ struct mm81x_vif *mm_vif = (struct mm81x_vif *)data;
+ struct mm81x *mm = mm81x_vif_to_mm(mm_vif);
+ struct mm81x_skbq *mq;
+ struct sk_buff *beacon;
+ struct ieee80211_vif *vif = mm81x_vif_to_ieee80211_vif(mm_vif);
+ struct mm81x_skb_tx_info tx_info = { 0 };
+ int num_bcn_vifs = atomic_read(&mm->num_bcn_vifs);
+
+ mq = mm81x_hif_get_tx_beacon_queue(mm);
+ if (!mq) {
+ mm81x_err(mm, "no matching beacon Q found");
+ return;
+ }
+
+ if (mm81x_skbq_count(mq) >= num_bcn_vifs) {
+ mm81x_err(mm,
+ "previous beacon not consumed, dropping req [id:%d]",
+ mm_vif->id);
+ return;
+ }
+
+ beacon = ieee80211_beacon_get(mm->hw, vif, false);
+ if (!beacon) {
+ mm81x_err(mm, "failed to retrieve beacon");
+ return;
+ }
+
+ mm81x_beacon_h_fill_tx_info(mm, &tx_info, mm_vif,
+ mm81x_tx_h_get_prim_bw(&mm->chandef));
+ mm81x_skbq_skb_tx(mq, &beacon, &tx_info, MM81X_SKB_CHAN_BEACON);
+}
+
+void mm81x_mac_beacon_irq_handle(struct mm81x *mm, u32 status)
+{
+ int vif_id;
+ unsigned long masked_status = (status & mm->beacon_irqs_enabled) >>
+ MM81X_INT_BEACON_BASE_NUM;
+
+ guard(rcu)();
+ for_each_set_bit(vif_id, &masked_status, MM81X_MAX_IF) {
+ struct mm81x_vif *mm_vif;
+ struct ieee80211_vif *vif;
+
+ vif = mm81x_rcu_dereference_vif_id(mm, vif_id, true);
+ if (!vif)
+ continue;
+
+ mm_vif = ieee80211_vif_to_mm_vif(vif);
+ tasklet_schedule(&mm_vif->u.ap.beacon_tasklet);
+ }
+}
+
+static void mm81x_mac_beacon_init(struct mm81x_vif *mm_vif)
+{
+ struct mm81x *mm = mm81x_vif_to_mm(mm_vif);
+
+ tasklet_init(&mm_vif->u.ap.beacon_tasklet, mm81x_mac_beacon_tasklet,
+ (unsigned long)mm_vif);
+
+ mm81x_mac_beacon_irq_enable(mm_vif, true);
+ atomic_inc(&mm->num_bcn_vifs);
+}
+
+static struct hw_scan_tlv_hdr mm81x_hw_scan_h_pack_tlv_hdr(u16 tag, u16 len)
+{
+ struct hw_scan_tlv_hdr hdr = { .tag = cpu_to_le16(tag),
+ .len = cpu_to_le16(len) };
+ return hdr;
+}
+
+static __le32 mm81x_hw_scan_h_pack_channel(struct ieee80211_channel *chan,
+ u8 pwr_idx)
+{
+ __le32 packed = 0;
+ u32 freq_khz = ieee80211_channel_to_khz(chan);
+
+ packed |= le32_encode_bits(freq_khz, HW_SCAN_CH_LIST_FREQ_KHZ);
+ packed |= le32_encode_bits(mm81x_ratecode_bw_mhz_to_bw_index(1),
+ HW_SCAN_CH_LIST_OP_BW);
+ packed |= le32_encode_bits(mm81x_ratecode_bw_mhz_to_bw_index(1),
+ HW_SCAN_CH_LIST_PRIM_CH_WIDTH);
+ packed |= le32_encode_bits(pwr_idx, HW_SCAN_CH_LIST_PWR_LIST_IDX);
+
+ return packed;
+}
+
+static u8 *
+mm81x_hw_scan_h_add_channel_list_tlv(u8 *buf,
+ struct mm81x_hw_scan_params *params)
+{
+ int i;
+ struct hw_scan_tlv_channel_list *ch_list =
+ (struct hw_scan_tlv_channel_list *)buf;
+
+ ch_list->hdr = mm81x_hw_scan_h_pack_tlv_hdr(
+ HOST_CMD_HW_SCAN_TLV_TAG_CHAN_LIST,
+ params->num_chans * sizeof(ch_list->channels[0]));
+
+ for (i = 0; i < params->num_chans; i++) {
+ struct ieee80211_channel *chan = params->channels[i].channel;
+
+ ch_list->channels[i] = mm81x_hw_scan_h_pack_channel(
+ chan, params->channels[i].power_idx);
+ }
+
+ return (u8 *)&ch_list->channels[i];
+}
+
+static u8 *
+mm81x_hw_scan_h_add_power_list_tlv(u8 *buf, struct mm81x_hw_scan_params *params)
+{
+ int i;
+ struct hw_scan_tlv_power_list *pwr_list =
+ (struct hw_scan_tlv_power_list *)buf;
+ size_t size = sizeof(pwr_list->tx_power_qdbm[0]) * params->n_powers;
+
+ pwr_list->hdr = mm81x_hw_scan_h_pack_tlv_hdr(
+ HOST_CMD_HW_SCAN_TLV_TAG_POWER_LIST, size);
+
+ for (i = 0; i < params->n_powers; i++)
+ pwr_list->tx_power_qdbm[i] = params->powers_qdbm[i];
+
+ return (u8 *)&pwr_list->tx_power_qdbm[i];
+}
+
+static u8 *
+mm81x_hw_scan_h_add_probe_req_tlv(u8 *buf, struct mm81x_hw_scan_params *params)
+{
+ struct sk_buff *skb = params->probe_req;
+ struct hw_scan_tlv_probe_req *probe_req =
+ (struct hw_scan_tlv_probe_req *)buf;
+
+ probe_req->hdr = mm81x_hw_scan_h_pack_tlv_hdr(
+ HOST_CMD_HW_SCAN_TLV_TAG_PROBE_REQ, skb->len);
+ memcpy(probe_req->buf, skb->data, skb->len);
+
+ return buf + sizeof(*probe_req) + skb->len;
+}
+
+static u8 *
+mm81x_hw_scan_h_insert_dwell_time_tlv(u8 *buf,
+ struct mm81x_hw_scan_params *params)
+{
+ struct hw_scan_tlv_dwell_on_home *dwell =
+ (struct hw_scan_tlv_dwell_on_home *)buf;
+
+ dwell->hdr = mm81x_hw_scan_h_pack_tlv_hdr(
+ HOST_CMD_HW_SCAN_TLV_TAG_DWELL_ON_HOME,
+ sizeof(*dwell) - sizeof(dwell->hdr));
+ dwell->home_dwell_time_ms = cpu_to_le32(params->dwell_on_home_ms);
+
+ return buf + sizeof(*dwell);
+}
+
+static int __mm81x_hw_scan_h_init_probe_req(struct mm81x_hw_scan_params *params,
+ u8 *ssid, u8 ssid_len,
+ struct ieee80211_scan_ies *ies)
+{
+ u8 *pos;
+ struct sk_buff *probe_req;
+ struct ieee80211_tx_info *info;
+ u16 ies_len = ies->len[NL80211_BAND_S1GHZ] + ies->common_ie_len;
+
+ probe_req = ieee80211_probereq_get(params->hw, params->vif->addr, ssid,
+ ssid_len, ies_len);
+ if (!probe_req)
+ return -ENOMEM;
+
+ pos = skb_put(probe_req, ies_len);
+ memcpy(pos, ies->common_ies, ies->common_ie_len);
+ pos += ies->common_ie_len;
+ memcpy(pos, ies->ies[NL80211_BAND_S1GHZ], ies->len[NL80211_BAND_S1GHZ]);
+
+ info = IEEE80211_SKB_CB(probe_req);
+ info->control.vif = params->vif;
+ params->probe_req = probe_req;
+
+ return 0;
+}
+
+static void mm81x_hw_scan_h_init_ssid(struct mm81x *mm,
+ struct cfg80211_ssid *ssids, int n_ssids,
+ u8 **out_ssid, u8 *out_ssid_len)
+{
+ *out_ssid = NULL;
+ *out_ssid_len = 0;
+
+ if (n_ssids > 0) {
+ if (n_ssids > 1) {
+ mm81x_warn(
+ mm,
+ "Multiple SSIDs found when only one supported. Using the first only.");
+ }
+ *out_ssid_len = ssids[0].ssid_len;
+ *out_ssid = ssids[0].ssid;
+ }
+}
+
+static int
+mm81x_hw_scan_h_init_probe_req(struct mm81x_hw_scan_params *params,
+ struct ieee80211_scan_request *scan_req)
+{
+ struct mm81x *mm = params->hw->priv;
+ struct cfg80211_scan_request *req = &scan_req->req;
+ struct ieee80211_scan_ies *ies = &scan_req->ies;
+ u8 ssid_len = 0;
+ u8 *ssid = NULL;
+
+ mm81x_hw_scan_h_init_ssid(mm, req->ssids, req->n_ssids, &ssid,
+ &ssid_len);
+
+ return __mm81x_hw_scan_h_init_probe_req(params, ssid, ssid_len, ies);
+}
+
+static bool
+mm81x_hw_scan_h_is_chan_present(const struct mm81x_hw_scan_params *params,
+ const struct ieee80211_channel *chan)
+{
+ int channel;
+
+ for (channel = 0; channel < params->num_chans; channel++) {
+ if (params->channels[channel].channel == chan)
+ return true;
+ }
+
+ return false;
+}
+
+static int mm81x_hw_scan_h_insert_chan(struct mm81x_hw_scan_params *params,
+ struct ieee80211_channel *chan)
+{
+ if (!params->channels)
+ return -EFAULT;
+
+ if (!chan)
+ return -EFAULT;
+
+ if (params->num_chans >= params->allocated_chans)
+ return -ENOMEM;
+
+ if (mm81x_hw_scan_h_is_chan_present(params, chan))
+ return 0;
+
+ params->channels[params->num_chans].channel = chan;
+ params->num_chans++;
+ return 0;
+}
+
+static int mm81x_hw_scan_h_init_chan_list(struct mm81x_hw_scan_params *params,
+ struct ieee80211_channel **chans,
+ u32 n_channels)
+{
+ int i, j;
+ int num_pwrs_coarse = 0;
+ int last_pwr = INT_MIN;
+ int chans_to_allocate = 0;
+
+ for (i = 0; i < n_channels; i++)
+ if (chans[i])
+ chans_to_allocate++;
+
+ params->num_chans = 0;
+ params->allocated_chans = 0;
+ params->channels = kcalloc(chans_to_allocate, sizeof(*params->channels),
+ GFP_KERNEL);
+ if (!params->channels)
+ return -ENOMEM;
+
+ params->allocated_chans = chans_to_allocate;
+
+ for (i = 0; i < n_channels; i++)
+ if (chans[i])
+ mm81x_hw_scan_h_insert_chan(params, chans[i]);
+
+ /*
+ * Calculate a rough estimate of number of different channel
+ * powers required
+ */
+ for (i = 0; i < params->num_chans; i++) {
+ if (chans[i]->max_reg_power != last_pwr) {
+ last_pwr = chans[i]->max_reg_power;
+ num_pwrs_coarse++;
+ }
+ }
+
+ params->powers_qdbm = kmalloc_array(
+ num_pwrs_coarse, sizeof(*params->powers_qdbm), GFP_KERNEL);
+ if (!params->powers_qdbm)
+ return -ENOMEM;
+
+ params->n_powers = 0;
+
+ for (i = 0; i < params->num_chans; i++) {
+ s32 power_qdbm =
+ MBM_TO_QDBM(DBM_TO_MBM(chans[i]->max_reg_power));
+
+ /* Try and find the power in the list */
+ for (j = 0; j < params->n_powers; j++)
+ if (params->powers_qdbm[j] == power_qdbm)
+ break;
+
+ /* Reached the end of the list - add the new power option */
+ if (j == params->n_powers) {
+ params->powers_qdbm[j] = power_qdbm;
+ params->n_powers++;
+ if (params->n_powers > num_pwrs_coarse) {
+ WARN_ON(1);
+ return -EFAULT;
+ }
+ }
+
+ /* Give the index of the power level to the channel */
+ params->channels[i].power_idx = j;
+ }
+ return 0;
+}
+
+static void mm81x_hw_scan_h_clean_params(struct mm81x_hw_scan_params *params)
+{
+ if (params->probe_req)
+ dev_kfree_skb_any(params->probe_req);
+ kfree(params->channels);
+ kfree(params->powers_qdbm);
+
+ params->num_chans = 0;
+ params->allocated_chans = 0;
+}
+
+size_t mm81x_hw_scan_h_get_cmd_size(struct mm81x_hw_scan_params *params)
+{
+ struct hw_scan_tlv_channel_list *ch_list;
+ struct hw_scan_tlv_power_list *pwr_list;
+ struct hw_scan_tlv_probe_req *probe_req;
+ struct hw_scan_tlv_dwell_on_home *dwell;
+ struct host_cmd_req_hw_scan *req;
+ size_t cmd_size = sizeof(*req);
+
+ /* No TLVs if simple abort command */
+ if (params->operation != MM81X_HW_SCAN_OP_START)
+ return cmd_size;
+
+ cmd_size += struct_size(ch_list, channels, params->num_chans);
+ cmd_size += struct_size(pwr_list, tx_power_qdbm, params->n_powers);
+
+ if (params->probe_req)
+ cmd_size += struct_size(probe_req, buf, params->probe_req->len);
+ if (params->dwell_on_home_ms)
+ cmd_size += sizeof(*dwell);
+
+ return cmd_size;
+}
+
+u8 *mm81x_hw_scan_h_insert_tlvs(struct mm81x_hw_scan_params *params, u8 *buf)
+{
+ buf = mm81x_hw_scan_h_add_channel_list_tlv(buf, params);
+ buf = mm81x_hw_scan_h_add_power_list_tlv(buf, params);
+
+ if (params->dwell_on_home_ms)
+ buf = mm81x_hw_scan_h_insert_dwell_time_tlv(buf, params);
+ if (params->probe_req)
+ buf = mm81x_hw_scan_h_add_probe_req_tlv(buf, params);
+
+ return buf;
+}
+
+static u32 mm81x_hw_scan_h_get_dwell_on_home(struct mm81x *mm,
+ struct ieee80211_vif *vif)
+{
+ if (vif->type == NL80211_IFTYPE_STATION &&
+ mm81x_mac_is_sta_vif_associated(vif))
+ return mm->hw_scan.home_dwell_ms;
+ return 0;
+}
+
+static struct mm81x_hw_scan_params *
+__mm81x_hw_scan_h_init_params(struct mm81x *mm)
+{
+ struct mm81x_hw_scan_params *params = mm->hw_scan.params;
+
+ if (!params) {
+ params = kzalloc_obj(*params, GFP_KERNEL);
+ if (params)
+ mm->hw_scan.params = params;
+ } else {
+ mm81x_hw_scan_h_clean_params(params);
+ memset(params, 0, sizeof(*params));
+ }
+
+ return params;
+}
+
+static int mm81x_hw_scan_h_init_params(struct mm81x *mm,
+ struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct cfg80211_scan_request *req)
+{
+ struct mm81x_hw_scan_params *params = mm->hw_scan.params;
+
+ lockdep_assert_held(&mm->lock);
+
+ params = __mm81x_hw_scan_h_init_params(mm);
+ if (!params) {
+ mm->hw_scan.state = HW_SCAN_STATE_IDLE;
+ return -ENOMEM;
+ }
+
+ params->hw = hw;
+ params->vif = vif;
+ params->has_directed_ssid = (req->ssids && req->ssids[0].ssid_len > 0);
+ params->operation = MM81X_HW_SCAN_OP_START;
+ params->dwell_on_home_ms = mm81x_hw_scan_h_get_dwell_on_home(mm, vif);
+ params->use_1mhz_probes = true;
+
+ if (req->duration)
+ params->dwell_time_ms = MM81X_TU_TO_MS(req->duration);
+ else if (req->n_ssids == 0)
+ params->dwell_time_ms =
+ MM81X_HWSCAN_DEFAULT_PASSIVE_DWELL_TIME_MS;
+ else
+ params->dwell_time_ms = MM81X_HWSCAN_DEFAULT_DWELL_TIME_MS;
+
+ return 0;
+}
+
+static u32 mm81x_hw_scan_h_calc_timeout(struct mm81x_hw_scan_params *params)
+{
+ u32 ret = 0;
+
+ ret = params->dwell_time_ms + params->dwell_on_home_ms;
+ if (params->probe_req)
+ ret += MM81X_HWSCAN_PROBE_DELAY_MS;
+
+ ret *= params->num_chans;
+ ret += MM81X_HWSCAN_TIMEOUT_OVERHEAD_MS;
+
+ return ret;
+}
+
+static int mm81x_mac_ops_hw_scan(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_scan_request *hw_req)
+{
+ int ret = 0;
+ struct mm81x *mm = hw->priv;
+ struct cfg80211_scan_request *req = &hw_req->req;
+ struct mm81x_hw_scan_params *params;
+ struct ieee80211_channel **chans = hw_req->req.channels;
+
+ mutex_lock(&mm->lock);
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "state %d", mm->hw_scan.state);
+
+ if (!mm->started) {
+ mm81x_warn(mm, "device not ready");
+ ret = -ENODEV;
+ goto exit;
+ }
+
+ switch (mm->hw_scan.state) {
+ case HW_SCAN_STATE_IDLE:
+ mm->hw_scan.state = HW_SCAN_STATE_RUNNING;
+ reinit_completion(&mm->hw_scan.scan_done);
+ break;
+ case HW_SCAN_STATE_RUNNING:
+ case HW_SCAN_STATE_ABORTING:
+ ret = -EBUSY;
+ goto exit;
+ }
+
+ ret = mm81x_hw_scan_h_init_params(mm, hw, vif, req);
+ if (ret)
+ goto exit;
+
+ params = mm->hw_scan.params;
+
+ ret = mm81x_hw_scan_h_init_chan_list(params, chans,
+ hw_req->req.n_channels);
+ if (ret)
+ goto exit;
+
+ /* Only init the probe request template if this is an active scan */
+ if (req->n_ssids > 0) {
+ ret = mm81x_hw_scan_h_init_probe_req(params, hw_req);
+ if (ret) {
+ mm81x_err(mm, "Failed to init probe req %d", ret);
+ goto exit;
+ }
+ }
+
+ ret = mm81x_cmd_hw_scan(mm, params, false);
+ if (ret) {
+ mm->hw_scan.state = HW_SCAN_STATE_IDLE;
+ goto exit;
+ }
+
+ ieee80211_queue_delayed_work(
+ mm->hw, &mm->hw_scan.timeout,
+ msecs_to_jiffies(mm81x_hw_scan_h_calc_timeout(params)));
+exit:
+ mutex_unlock(&mm->lock);
+ return ret;
+}
+
+static void mm81x_hw_scan_h_cancel(struct mm81x *mm)
+{
+ int ret;
+ struct mm81x_hw_scan_params params = { 0 };
+
+ mutex_lock(&mm->lock);
+ cancel_delayed_work_sync(&mm->hw_scan.timeout);
+
+ switch (mm->hw_scan.state) {
+ case HW_SCAN_STATE_IDLE:
+ case HW_SCAN_STATE_ABORTING:
+ /* scan not running */
+ mutex_unlock(&mm->lock);
+ return;
+ case HW_SCAN_STATE_RUNNING:
+ mm->hw_scan.state = HW_SCAN_STATE_ABORTING;
+ break;
+ }
+
+ params.operation = MM81X_HW_SCAN_OP_STOP;
+
+ ret = mm81x_cmd_hw_scan(mm, ¶ms, false);
+
+ mutex_unlock(&mm->lock);
+
+ if (ret || !mm->started ||
+ !wait_for_completion_timeout(&mm->hw_scan.scan_done, 1 * HZ)) {
+ /*
+ * We may have lost the event on the bus, the chip could be
+ * wedged, or the cmd failed for another reason. Nevertheless,
+ * we should call the done event so mac80211 knows to unblock
+ * itself.
+ */
+ struct cfg80211_scan_info info = { .aborted = true };
+
+ mutex_lock(&mm->lock);
+ ieee80211_scan_completed(mm->hw, &info);
+ mm->hw_scan.state = HW_SCAN_STATE_IDLE;
+
+ mutex_unlock(&mm->lock);
+ }
+}
+
+static void mm81x_mac_ops_cancel_hw_scan(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+ struct mm81x *mm = hw->priv;
+
+ cancel_delayed_work_sync(&mm->hw_scan.timeout);
+ mm81x_hw_scan_h_cancel(mm);
+}
+
+static void mm81x_mac_hw_scan_done_event(struct ieee80211_hw *hw)
+{
+ struct mm81x *mm = hw->priv;
+ struct cfg80211_scan_info info = { 0 };
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "completing hw scan");
+
+ mutex_lock(&mm->lock);
+
+ switch (mm->hw_scan.state) {
+ case HW_SCAN_STATE_IDLE:
+ /* Scan has already been stopped. Just continue */
+ goto exit;
+ case HW_SCAN_STATE_RUNNING:
+ case HW_SCAN_STATE_ABORTING:
+ mm->hw_scan.state = HW_SCAN_STATE_IDLE;
+ info.aborted = (mm->hw_scan.state == HW_SCAN_STATE_ABORTING);
+ }
+
+ ieee80211_scan_completed(mm->hw, &info);
+exit:
+ complete(&mm->hw_scan.scan_done);
+ mutex_unlock(&mm->lock);
+ cancel_delayed_work_sync(&mm->hw_scan.timeout);
+}
+
+static void mm81x_mac_hw_scan_timeout_work(struct work_struct *work)
+{
+ struct mm81x *mm =
+ container_of(work, struct mm81x, hw_scan.timeout.work);
+
+ mm81x_err(mm, "hw scan timed out, aborting");
+ mm81x_hw_scan_h_cancel(mm);
+}
+
+static void mm81x_mac_hw_scan_init(struct mm81x *mm)
+{
+ mm->hw_scan.state = HW_SCAN_STATE_IDLE;
+ mm->hw_scan.params = NULL;
+ mm->hw_scan.home_dwell_ms = MM81X_HWSCAN_DEFAULT_DWELL_ON_HOME_MS;
+
+ init_completion(&mm->hw_scan.scan_done);
+ INIT_DELAYED_WORK(&mm->hw_scan.timeout, mm81x_mac_hw_scan_timeout_work);
+}
+
+static void mm81x_mac_hw_scan_destroy(struct mm81x *mm)
+{
+ cancel_delayed_work_sync(&mm->hw_scan.timeout);
+ if (mm->hw_scan.params)
+ mm81x_hw_scan_h_clean_params(mm->hw_scan.params);
+ kfree(mm->hw_scan.params);
+ mm->hw_scan.params = NULL;
+}
+
+static void mm81x_mac_hw_scan_finish(struct mm81x *mm)
+{
+ struct cfg80211_scan_info info = {
+ .aborted = true,
+ };
+ lockdep_assert_held(&mm->lock);
+
+ if (mm->hw_scan.state == HW_SCAN_STATE_IDLE)
+ return;
+
+ ieee80211_scan_completed(mm->hw, &info);
+ complete(&mm->hw_scan.scan_done);
+ mm->hw_scan.state = HW_SCAN_STATE_IDLE;
+ cancel_delayed_work_sync(&mm->hw_scan.timeout);
+}
+
+int mm81x_mac_event_recv(struct mm81x *mm, struct sk_buff *skb)
+{
+ int ret;
+ struct host_cmd_event *event = (struct host_cmd_event *)(skb->data);
+ u16 event_id = le16_to_cpu(event->hdr.message_id);
+ u16 event_iid = le16_to_cpu(event->hdr.host_id);
+
+ if (!HOST_CMD_IS_EVT(event) || event_iid != 0) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ switch (event_id) {
+ case HOST_CMD_ID_EVT_HW_SCAN_DONE: {
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "Event: HOST_CMD_ID_EVT_HW_SCAN_DONE Received.");
+ mm81x_mac_hw_scan_done_event(mm->hw);
+ ret = 0;
+ break;
+ }
+ default:
+ ret = 0;
+ break;
+ }
+
+exit:
+ return ret;
+}
+
+static void mm81x_tx_h_apply_mcs10(struct mm81x *mm,
+ struct mm81x_skb_tx_info *tx_info)
+{
+ u8 i;
+ u8 j;
+ int mcs0_first_idx = -1;
+ int mcs0_last_idx = -1;
+
+ /* Find out where our first and last MCS0 entries are. */
+ for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
+ enum dot11_bandwidth bw_idx = mm81x_ratecode_bw_index_get(
+ tx_info->rates[i].mm81x_ratecode);
+
+ if (bw_idx == DOT11_BANDWIDTH_1MHZ) {
+ mcs0_last_idx = i;
+ if (mcs0_first_idx == -1)
+ mcs0_first_idx = i;
+ }
+
+ /*
+ * If the count is 0 then we are at the end of the table.
+ * Break to allow us to reuse i indicating the end of the
+ * table.
+ */
+ if (tx_info->rates[i].count == 0)
+ break;
+ }
+
+ /* If there aren't any MCS0 (at 1MHz) entries we are done. */
+ if (mcs0_first_idx < 0)
+ return;
+
+ /*
+ * If we are in MCS10_MODE_AUTO add MCS10 counts to the table if they
+ * will fit. There should be three cases:
+ *
+ * - There is one MSC0 entry and the table is full -> do nothing
+ * - There is one MSC0 entry and the table has space -> adjust MSC0
+ * down and add MCS 10
+ * - There are multiple MCS0 entries -> replace entries after the first
+ * with MCS 10
+ */
+ /* Case 3 - replace additional entries. */
+ if (mcs0_last_idx > mcs0_first_idx) {
+ for (j = mcs0_first_idx + 1; j < i; j++) {
+ enum dot11_bandwidth bw_idx =
+ mm81x_ratecode_bw_index_get(
+ tx_info->rates[j].mm81x_ratecode);
+ u8 mcs_index = mm81x_ratecode_mcs_index_get(
+ tx_info->rates[j].mm81x_ratecode);
+ if (mcs_index == 0 && bw_idx == DOT11_BANDWIDTH_1MHZ) {
+ mm81x_ratecode_mcs_index_set(
+ &tx_info->rates[j].mm81x_ratecode, 10);
+ }
+ }
+ /* Case 2 - add additional MCS10 entry. */
+ } else if (mcs0_last_idx == mcs0_first_idx &&
+ i < (IEEE80211_TX_MAX_RATES)) {
+ int pre_mcs10_mcs0_count =
+ min_t(u8, tx_info->rates[mcs0_last_idx].count,
+ MCS0_BEFORE_MCS10_COUNT);
+ int mcs10_count = tx_info->rates[mcs0_last_idx].count -
+ pre_mcs10_mcs0_count;
+
+ /*
+ * If there were less retries than our desired minimum MCS0 we
+ * don't add MCS10 retries.
+ */
+ if (mcs10_count > 0) {
+ /* Use the same flags for MCS10 as MCS0. */
+ tx_info->rates[i].mm81x_ratecode =
+ tx_info->rates[mcs0_last_idx].mm81x_ratecode;
+ mm81x_ratecode_mcs_index_set(
+ &tx_info->rates[i].mm81x_ratecode, 10);
+ tx_info->rates[mcs0_last_idx].count =
+ pre_mcs10_mcs0_count;
+ tx_info->rates[i].count = mcs10_count;
+ }
+ }
+}
+
+void mm81x_tx_h_check_aggr(struct ieee80211_sta *pubsta, struct sk_buff *skb)
+{
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ struct mm81x_sta *mm_sta = (struct mm81x_sta *)pubsta->drv_priv;
+ u8 tid = ieee80211_get_tid(hdr);
+
+ /* we are already aggregating */
+ if (mm_sta->tid_tx[tid] || mm_sta->tid_start_tx[tid])
+ return;
+
+ if (mm_sta->state < IEEE80211_STA_AUTHORIZED)
+ return;
+
+ if (skb_get_queue_mapping(skb) == IEEE80211_AC_VO)
+ return;
+
+ if (unlikely(!ieee80211_is_data_qos(hdr->frame_control)))
+ return;
+
+ if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE)))
+ return;
+
+ mm_sta->tid_start_tx[tid] = true;
+ ieee80211_start_tx_ba_session(pubsta, tid, 0);
+}
+
+int mm81x_tx_h_get_attempts(struct mm81x *mm,
+ struct mm81x_skb_tx_status *tx_sts)
+{
+ int attempts = 0;
+ int i;
+ int count = min_t(int, MM81X_SKB_MAX_RATES, IEEE80211_TX_MAX_RATES);
+
+ for (i = 0; i < count; i++) {
+ if (tx_sts->rates[i].count > 0)
+ attempts += tx_sts->rates[i].count;
+ else
+ break;
+ }
+
+ return attempts;
+}
+
+static void mm81x_tx_h_fill_info(struct mm81x *mm,
+ struct mm81x_skb_tx_info *tx_info,
+ struct sk_buff *skb, struct ieee80211_vif *vif,
+ int tx_bw_mhz, struct ieee80211_sta *sta)
+{
+ int i;
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ struct mm81x_vif *mm_vif = ieee80211_vif_to_mm_vif(vif);
+ struct mm81x_sta *mm_sta = NULL;
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ int op_bw_mhz = cfg80211_chandef_get_width(&mm->chandef);
+ u8 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
+ bool rts_allowed = op_bw_mhz < 8;
+
+ if (sta)
+ mm_sta = (struct mm81x_sta *)sta->drv_priv;
+
+ rts_allowed &= mm81x_tx_h_pkt_over_rts_threshold(mm, info, skb);
+
+ mm81x_rc_sta_fill_tx_rates(mm, tx_info, skb, sta, tx_bw_mhz,
+ rts_allowed);
+
+ for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
+ if (rts_allowed)
+ mm81x_ratecode_enable_rts(
+ &tx_info->rates[i].mm81x_ratecode);
+
+ if (info->control.rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
+ mm81x_ratecode_enable_sgi(
+ &tx_info->rates[i].mm81x_ratecode);
+ }
+
+ /* Apply change of MCS0 to MCS10 if required. */
+ mm81x_tx_h_apply_mcs10(mm, tx_info);
+
+ tx_info->flags |=
+ cpu_to_le32(MM81X_TX_CONF_FLAGS_VIF_ID_SET(mm_vif->id));
+
+ if (info->flags & IEEE80211_TX_CTL_AMPDU)
+ tx_info->flags |= cpu_to_le32(MM81X_TX_CONF_FLAGS_CTL_AMPDU);
+
+ if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM)
+ tx_info->flags |=
+ cpu_to_le32(MM81X_TX_CONF_FLAGS_SEND_AFTER_DTIM);
+
+ if (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER) {
+ tx_info->flags |= cpu_to_le32(MM81X_TX_CONF_NO_PS_BUFFER);
+
+ if (info->flags & IEEE80211_TX_STATUS_EOSP)
+ tx_info->flags |= cpu_to_le32(
+ MM81X_TX_CONF_FLAGS_IMMEDIATE_REPORT);
+ } else if (ieee80211_is_mgmt(hdr->frame_control) &&
+ !ieee80211_is_bufferable_mmpdu(skb)) {
+ tx_info->flags |= cpu_to_le32(MM81X_TX_CONF_NO_PS_BUFFER);
+ }
+
+ if (info->control.hw_key) {
+ tx_info->flags |= cpu_to_le32(MM81X_TX_CONF_FLAGS_HW_ENCRYPT);
+ tx_info->flags |= cpu_to_le32(MM81X_TX_CONF_FLAGS_KEY_IDX_SET(
+ info->control.hw_key->hw_key_idx));
+ }
+
+ tx_info->tid = tid;
+ if (mm_sta) {
+ tx_info->tid_params = mm_sta->tid_params[tid];
+
+ if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) {
+ if (mm_sta->tx_ps_filter_en)
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "TX ps filter cleared sta[%pM]",
+ mm_sta->addr);
+ mm_sta->tx_ps_filter_en = false;
+ }
+ }
+}
+
+static void mm81x_mac_ops_tx(struct ieee80211_hw *hw,
+ struct ieee80211_tx_control *control,
+ struct sk_buff *skb)
+{
+ struct mm81x *mm = hw->priv;
+ struct mm81x_skbq *mq = NULL;
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ struct ieee80211_vif *vif = info->control.vif;
+ struct mm81x_skb_tx_info tx_info = { 0 };
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ bool is_mgmt = ieee80211_is_mgmt(hdr->frame_control);
+ int tx_bw_mhz = cfg80211_chandef_get_width(&mm->chandef);
+ struct ieee80211_sta *sta = control->sta;
+ int max_tx_bw = 0, sta_max_bw_mhz = 0;
+
+ if (sta) {
+ struct mm81x_sta *mm_sta = (struct mm81x_sta *)sta->drv_priv;
+
+ sta_max_bw_mhz = mm_sta->max_bw_mhz;
+ }
+
+ max_tx_bw = mm81x_tx_h_get_max_bw(mm);
+ tx_bw_mhz = min(max_tx_bw, tx_bw_mhz);
+
+ if (is_mgmt)
+ tx_bw_mhz = mm81x_tx_h_get_prim_bw(&mm->chandef);
+ if (sta_max_bw_mhz)
+ tx_bw_mhz = min(tx_bw_mhz, sta_max_bw_mhz);
+ if (ieee80211_is_probe_resp(hdr->frame_control))
+ tx_bw_mhz = 1;
+
+ mm81x_tx_h_fill_info(mm, &tx_info, skb, vif, tx_bw_mhz, sta);
+
+ if (mm81x_tx_h_ps_filtered_for_sta(mm, skb, sta))
+ return;
+
+ if (is_mgmt)
+ mq = mm81x_hif_get_tx_mgmt_queue(mm);
+ else
+ mq = mm81x_hif_get_tx_data_queue(mm,
+ dot11_tid_to_ac(tx_info.tid));
+
+ mm81x_skbq_skb_tx(mq, &skb, &tx_info,
+ (is_mgmt) ? MM81X_SKB_CHAN_MGMT :
+ MM81X_SKB_CHAN_DATA);
+}
+
+static void mm81x_mac_ops_stop(struct ieee80211_hw *hw, bool suspend)
+{
+ struct mm81x *mm = hw->priv;
+
+ mutex_lock(&mm->lock);
+ mm->started = false;
+ mutex_unlock(&mm->lock);
+}
+
+static void mm81x_mac_beacon_finish(struct mm81x_vif *mm_vif)
+{
+ struct mm81x *mm = mm81x_vif_to_mm(mm_vif);
+
+ mm81x_mac_beacon_irq_enable(mm_vif, false);
+ tasklet_kill(&mm_vif->u.ap.beacon_tasklet);
+ /*
+ * Side effect of the restarting required when
+ * reacting to regdom changes...
+ */
+ atomic_add_unless(&mm->num_bcn_vifs, -1, 0);
+}
+
+static void mm81x_mac_ops_remove_interface(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+ int ret;
+ struct mm81x *mm = hw->priv;
+ struct mm81x_vif *mm_vif = (struct mm81x_vif *)vif->drv_priv;
+
+ mutex_lock(&mm->lock);
+
+ if (vif->type == NL80211_IFTYPE_AP)
+ mm81x_mac_beacon_finish(mm_vif);
+
+ ret = mm81x_cmd_rm_if(mm, mm_vif->id);
+ if (ret)
+ mm81x_err(mm, "mm81x_cmd_rm_if failed %d", ret);
+
+ RCU_INIT_POINTER(mm->vifs[mm_vif->id], NULL);
+ mutex_unlock(&mm->lock);
+}
+
+static s32 mm81x_mac_get_max_txpower(struct mm81x *mm)
+{
+ int ret;
+ s32 power_mbm;
+
+ /* Retrieve maximum TX power the chip can transmit */
+ ret = mm81x_cmd_get_max_txpower(mm, &power_mbm);
+ if (ret) {
+ mm81x_err(mm, "using default tx max power %d mBm",
+ MAX_TX_POWER_MBM);
+ return MAX_TX_POWER_MBM;
+ }
+
+ mm81x_dbg(mm, MM81X_DBG_MAC, "Max tx power detected %d mBm", power_mbm);
+ return power_mbm;
+}
+
+static s32 mm81x_mac_set_txpower(struct mm81x *mm, s32 power_mbm)
+{
+ int ret;
+ s32 out_power_mbm;
+
+ if (mm->tx_max_power_mbm == INT_MAX)
+ mm->tx_max_power_mbm = mm81x_mac_get_max_txpower(mm);
+
+ power_mbm = min(power_mbm, mm->tx_max_power_mbm);
+ if (power_mbm == mm->tx_power_mbm)
+ return mm->tx_power_mbm;
+
+ ret = mm81x_cmd_set_txpower(mm, &out_power_mbm, power_mbm);
+ if (ret) {
+ mm81x_err(mm, "failed, power %d mBm ret %d", power_mbm, ret);
+ return mm->tx_power_mbm;
+ }
+
+ if (out_power_mbm != mm->tx_power_mbm) {
+ mm81x_dbg(mm, MM81X_DBG_MAC, "%d -> %d mBm", mm->tx_power_mbm,
+ out_power_mbm);
+ mm->tx_power_mbm = out_power_mbm;
+ }
+
+ return mm->tx_power_mbm;
+}
+
+static int mm81x_mac_set_channel(struct mm81x *mm, u32 op_chan_freq_hz,
+ u8 pri_1mhz_chan_idx, u8 op_bw_mhz,
+ u8 pri_bw_mhz)
+{
+ int ret;
+
+ ret = mm81x_cmd_set_channel(mm, op_chan_freq_hz, pri_1mhz_chan_idx,
+ op_bw_mhz, pri_bw_mhz, &mm->tx_power_mbm);
+ if (ret) {
+ mm81x_err(mm, "mm81x_cmd_set_channel() failed, ret %d", ret);
+ return ret;
+ }
+
+ mm81x_mac_set_txpower(mm, mm->tx_power_mbm);
+ return 0;
+}
+
+static u8 mm81x_mac_pri_chan_to_index(const struct cfg80211_chan_def *chandef)
+{
+ u32 bw_mhz = cfg80211_chandef_get_width(chandef);
+ u32 op_center_khz = ieee80211_chandef_to_khz(chandef);
+ u32 first_1mhz_center_khz = op_center_khz - (bw_mhz * 500) + 500;
+ u32 pri_1mhz_khz = ieee80211_channel_to_khz(chandef->chan);
+
+ return (pri_1mhz_khz - first_1mhz_center_khz) / 1000;
+}
+
+static int mm81x_mac_ops_change_channel(struct ieee80211_hw *hw,
+ struct ieee80211_chanctx_conf *ctx)
+{
+ int ret;
+ struct mm81x *mm = hw->priv;
+ struct cfg80211_chan_def *chandef = &ctx->def;
+ u64 freq_hz = KHZ_TO_HZ(ieee80211_chandef_to_khz(chandef));
+ u8 op_bw_mhz = cfg80211_chandef_get_width(chandef);
+ u8 pri_1mhz_idx = mm81x_mac_pri_chan_to_index(chandef);
+ int pri_chan_width_mhz = mm81x_tx_h_get_prim_bw(chandef);
+
+ mm81x_dbg(mm, MM81X_DBG_MAC,
+ "ch: freq=%llu Hz bw=%u pri_idx=%d pri_bw=%d", freq_hz,
+ op_bw_mhz, pri_1mhz_idx, pri_chan_width_mhz);
+
+ ret = mm81x_mac_set_channel(mm, freq_hz, (u8)pri_1mhz_idx, op_bw_mhz,
+ pri_chan_width_mhz);
+ if (ret)
+ return ret;
+
+ memcpy(&mm->chandef, chandef, sizeof(mm->chandef));
+ return 0;
+}
+
+static int mm81x_mac_ops_add_chanctx(struct ieee80211_hw *hw,
+ struct ieee80211_chanctx_conf *ctx)
+{
+ int err = 0;
+ struct mm81x *mm = hw->priv;
+
+ mutex_lock(&mm->lock);
+ err = mm81x_mac_ops_change_channel(hw, ctx);
+ mutex_unlock(&mm->lock);
+ return err;
+}
+
+static void mm81x_mac_ops_remove_chanctx(struct ieee80211_hw *hw,
+ struct ieee80211_chanctx_conf *ctx)
+{
+ /* mm81x only supports a single chanctx */
+ UNUSED(hw);
+ UNUSED(ctx);
+}
+
+static void mm81x_mac_ops_change_chanctx(struct ieee80211_hw *hw,
+ struct ieee80211_chanctx_conf *ctx,
+ u32 changed)
+{
+ struct mm81x *mm = hw->priv;
+
+ UNUSED(ctx);
+
+ if (!mm->started)
+ return;
+
+ /*
+ * mm81x only support changing/setting the channel
+ * when we create an interface.
+ */
+ if (WARN_ON(changed & IEEE80211_CHANCTX_CHANGE_CHANNEL))
+ mm81x_err(mm, "Changing channel via chanctx not supported");
+}
+
+static int
+mm81x_mac_ops_assign_vif_chanctx(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *link_conf,
+ struct ieee80211_chanctx_conf *ctx)
+{
+ /* mm81x only supports a single chanctx */
+ UNUSED(hw);
+ UNUSED(vif);
+ UNUSED(link_conf);
+ UNUSED(ctx);
+
+ return 0;
+}
+
+static void
+mm81x_mac_ops_unassign_vif_chanctx(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *link_conf,
+ struct ieee80211_chanctx_conf *ctx)
+{
+ /* mm81x only supports a single chanctx */
+ UNUSED(hw);
+ UNUSED(vif);
+ UNUSED(link_conf);
+ UNUSED(ctx);
+}
+
+static int mm81x_mac_ops_config(struct ieee80211_hw *hw, int radio_idx,
+ u32 changed)
+{
+ struct mm81x *mm = hw->priv;
+ struct ieee80211_conf *conf = &hw->conf;
+ struct ieee80211_channel *channel = conf->chandef.chan;
+
+ if (!mm->started)
+ return 0;
+
+ mutex_lock(&mm->lock);
+
+ if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
+ !(conf->flags & IEEE80211_CONF_MONITOR)) {
+ s32 power_mbm = DBM_TO_MBM(conf->power_level);
+
+ power_mbm = min(channel->max_reg_power, power_mbm);
+ power_mbm = mm81x_mac_set_txpower(mm, power_mbm);
+ conf->power_level = MBM_TO_DBM(power_mbm);
+ }
+
+ mutex_unlock(&mm->lock);
+ return 0;
+}
+
+static int mm81x_mac_ops_get_txpower(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ unsigned int link_id, int *dbm)
+{
+ struct mm81x *mm = hw->priv;
+ struct ieee80211_chanctx_conf *chanctx_conf;
+ struct cfg80211_chan_def *chandef = &vif->bss_conf.chanreq.oper;
+
+ scoped_guard(rcu) {
+ chanctx_conf = rcu_access_pointer(vif->bss_conf.chanctx_conf);
+ if (!chanctx_conf ||
+ !cfg80211_chandef_identical(chandef, &chanctx_conf->def))
+ return -ENODATA;
+ }
+
+ mutex_lock(&mm->lock);
+ *dbm = MBM_TO_DBM(mm->tx_power_mbm);
+ mutex_unlock(&mm->lock);
+ return 0;
+}
+
+static void mm81x_mac_config_ps(struct mm81x *mm, struct ieee80211_vif *vif)
+{
+ bool en_ps = vif->cfg.ps;
+
+ if (vif->type == NL80211_IFTYPE_AP)
+ return;
+
+ if (mm->config_ps == en_ps)
+ return;
+
+ mm81x_dbg(mm, MM81X_DBG_MAC, "change powersave mode: %d (current %d)",
+ en_ps, mm->config_ps);
+
+ mm->config_ps = en_ps;
+
+ /*
+ * If we have GPIO pins wired. Let's control host-to-chip PS
+ * mechanism. Otherwise, ignore the command altogether.
+ */
+ if (en_ps) {
+ mm81x_cmd_set_ps(mm, true);
+ mm81x_ps_enable(mm);
+ } else {
+ mm81x_ps_disable(mm);
+ mm81x_cmd_set_ps(mm, false);
+ }
+}
+
+static void mm81x_mac_ops_bss_info_changed(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *info,
+ u64 changed)
+{
+ int ret;
+ struct mm81x *mm = hw->priv;
+ struct mm81x_vif *mm_vif = (struct mm81x_vif *)vif->drv_priv;
+
+ mutex_lock(&mm->lock);
+
+ if (changed & BSS_CHANGED_PS)
+ mm81x_mac_config_ps(mm, vif);
+
+ if (changed & BSS_CHANGED_BEACON_ENABLED) {
+ /* start command is sent, only if it was previously stopped */
+ if ((mm_vif->u.ap.beaconing_enabled && info->enable_beacon) ||
+ !info->enable_beacon)
+ mm81x_cmd_config_beacon_timer(mm, mm_vif,
+ info->enable_beacon);
+
+ mm_vif->u.ap.beaconing_enabled = true;
+ }
+
+ if (changed & BSS_CHANGED_BEACON_INT || changed & BSS_CHANGED_SSID) {
+ ret = mm81x_cmd_cfg_bss(mm, mm_vif->id, info->beacon_int,
+ info->dtim_period,
+ mm81x_vif_generate_cssid(vif));
+ if (ret)
+ mm81x_err(mm, "mm81x_cmd_cfg_bss failed %d", ret);
+ }
+
+ mutex_unlock(&mm->lock);
+}
+
+static u64 mm81x_mac_ops_prepare_multicast(struct ieee80211_hw *hw,
+ struct netdev_hw_addr_list *mc_list)
+{
+ struct mm81x *mm = hw->priv;
+ struct mcast_filter *filter;
+ struct netdev_hw_addr *addr;
+ u16 addr_count = netdev_hw_addr_list_count(mc_list);
+ u16 len = sizeof(*filter) + addr_count * sizeof(filter->addr_list[0]);
+
+ filter = kzalloc(len, GFP_ATOMIC);
+ if (!filter)
+ return 0;
+
+ if (addr_count > MCAST_FILTER_COUNT_MAX) {
+ mm81x_warn(
+ mm,
+ "Multicast filtering disabled - too many groups (%d) > %u",
+ addr_count, (u16)MCAST_FILTER_COUNT_MAX);
+ filter->count = 0;
+ } else {
+ netdev_hw_addr_list_for_each(addr, mc_list) {
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "mcast whitelist (%d): %pM", filter->count,
+ addr->addr);
+ filter->addr_list[filter->count++] =
+ mac2leuint32(addr->addr);
+ }
+ }
+
+ return (u64)(unsigned long)filter;
+}
+
+static void mm81x_mac_ops_configure_filter(struct ieee80211_hw *hw,
+ unsigned int changed_flags,
+ unsigned int *total_flags,
+ u64 multicast)
+{
+ struct mm81x *mm = hw->priv;
+ struct mcast_filter *cmd = (void *)(unsigned long)multicast;
+ struct mm81x_vif *mm_vif = NULL;
+ struct ieee80211_vif *vif = NULL;
+ int vif_id = 0;
+ int ret = 0;
+
+ if (!cmd)
+ goto out;
+
+ mutex_lock(&mm->lock);
+ kfree(mm->mcast_filter);
+ mm->mcast_filter = cmd;
+
+ for (vif_id = 0; vif_id < ARRAY_SIZE(mm->vifs); vif_id++) {
+ vif = mm81x_rcu_dereference_vif_id(mm, vif_id, false);
+ if (!vif)
+ continue;
+
+ mm_vif = ieee80211_vif_to_mm_vif(vif);
+
+ ret = mm81x_cmd_cfg_multicast_filter(mm, mm_vif);
+ if (!ret)
+ continue;
+
+ mm81x_err(mm, "Multicast filtering failed - rc=%d", ret);
+ mm->mcast_filter = NULL;
+ kfree(cmd);
+ break;
+ }
+
+out:
+ mutex_unlock(&mm->lock);
+ *total_flags &= 0;
+}
+
+static int mm81x_mac_ops_conf_tx(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ unsigned int link_id, u16 ac,
+ const struct ieee80211_tx_queue_params *params)
+{
+ int ret;
+ struct mm81x *mm = hw->priv;
+ struct mm81x_queue_params mqp;
+
+ mutex_lock(&mm->lock);
+ mqp.aci = map_mac80211q_2_mm81x_aci(ac);
+ mqp.aifs = params->aifs;
+ mqp.cw_max = params->cw_max;
+ mqp.cw_min = params->cw_min;
+ mqp.uapsd = params->uapsd;
+ mqp.txop = params->txop << 5;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "queue:%d txop:%d cw_min:%d cw_max:%d aifs:%d", mqp.aci,
+ mqp.txop, mqp.cw_min, mqp.cw_max, mqp.aifs);
+
+ ret = mm81x_cmd_cfg_qos(mm, &mqp);
+ if (ret)
+ mm81x_dbg(mm, MM81X_DBG_ANY, "mm81x_cmd_cfg_qos failed %d",
+ ret);
+
+ mutex_unlock(&mm->lock);
+ return ret;
+}
+
+static int mm81x_mac_ops_sta_state(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ enum ieee80211_sta_state old_state,
+ enum ieee80211_sta_state new_state)
+{
+ u16 aid;
+ int ret = 0;
+ struct mm81x *mm = hw->priv;
+ struct mm81x_vif *mm_vif = (struct mm81x_vif *)vif->drv_priv;
+ struct mm81x_sta *mm_sta = (struct mm81x_sta *)sta->drv_priv;
+
+ /* Ignore both NOTEXIST to NONE and NONE to NOTEXIST */
+ if ((old_state == IEEE80211_STA_NOTEXIST &&
+ new_state == IEEE80211_STA_NONE) ||
+ (old_state == IEEE80211_STA_NONE &&
+ new_state == IEEE80211_STA_NOTEXIST))
+ return 0;
+
+ if (vif->type == NL80211_IFTYPE_STATION)
+ aid = mm81x_mac_sta_aid(vif);
+ else
+ aid = sta->aid;
+
+ mutex_lock(&mm->lock);
+ ret = mm81x_cmd_sta_state(mm, mm_vif, aid, sta, new_state);
+ if (ret < 0)
+ goto exit;
+
+ ether_addr_copy(mm_sta->addr, sta->addr);
+ mm_sta->state = new_state;
+
+ if (new_state > old_state && new_state == IEEE80211_STA_ASSOC) {
+ if (vif->type == NL80211_IFTYPE_AP)
+ mm_vif->u.ap.num_stas++;
+ else if (vif->type == NL80211_IFTYPE_STATION)
+ mm_vif->u.sta.is_assoc = true;
+ }
+
+ if (new_state < old_state && new_state == IEEE80211_STA_NONE) {
+ if (vif->type == NL80211_IFTYPE_AP)
+ mm_vif->u.ap.num_stas--;
+ else if (vif->type == NL80211_IFTYPE_STATION)
+ mm_vif->u.sta.is_assoc = false;
+ }
+
+exit:
+ /*
+ * Always update our mmrc sta state even on failure to ensure
+ * we don't hold a dangling sta on error
+ */
+ mm81x_rc_sta_state_check(mm, vif, sta, old_state, new_state);
+ mutex_unlock(&mm->lock);
+ return new_state < old_state ? 0 : ret;
+}
+
+static int mm81x_mac_ops_ampdu_action(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_ampdu_params *params)
+{
+ u16 tid = params->tid;
+ struct mm81x *mm = hw->priv;
+ struct ieee80211_sta *sta = params->sta;
+ struct mm81x_sta *mm_sta = (struct mm81x_sta *)sta->drv_priv;
+ u16 buf_size =
+ min_t(u16, params->buf_size, DOT11AH_BA_MAX_MPDU_PER_AMPDU);
+
+ mutex_lock(&mm->lock);
+ switch (params->action) {
+ case IEEE80211_AMPDU_TX_START:
+ mm81x_dbg(mm, MM81X_DBG_ANY, "%pM.%d A-MPDU TX start",
+ mm_sta->addr, tid);
+ ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+ break;
+ case IEEE80211_AMPDU_TX_STOP_CONT:
+ case IEEE80211_AMPDU_TX_STOP_FLUSH:
+ case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
+ mm81x_dbg(mm, MM81X_DBG_ANY, "%pM.%d A-MPDU TX flush",
+ mm_sta->addr, tid);
+ mm_sta->tid_start_tx[tid] = false;
+ mm_sta->tid_tx[tid] = false;
+ mm_sta->tid_params[tid] = 0;
+ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+ break;
+ case IEEE80211_AMPDU_TX_OPERATIONAL:
+ mm81x_dbg(mm, MM81X_DBG_ANY, "%pM.%d A-MPDU TX oper",
+ mm_sta->addr, tid);
+ mm_sta->tid_tx[tid] = true;
+ if (!buf_size) {
+ mm81x_err(mm, "%pM.%d A-MPDU Invalid buf size",
+ mm_sta->addr, tid);
+ break;
+ }
+ mm_sta->tid_params[tid] =
+ u8_encode_bits(buf_size - 1,
+ TX_INFO_TID_PARAMS_MAX_REORDER_BUF) |
+ u8_encode_bits(1, TX_INFO_TID_PARAMS_AMPDU_ENABLED) |
+ u8_encode_bits(params->amsdu,
+ TX_INFO_TID_PARAMS_AMSDU_SUPPORTED);
+ break;
+ default:
+ break;
+ }
+
+ mutex_unlock(&mm->lock);
+ return 0;
+}
+
+static int mm81x_mac_ops_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct ieee80211_key_conf *key)
+{
+ u16 aid;
+ int ret = -EOPNOTSUPP;
+ struct mm81x *mm = hw->priv;
+ struct mm81x_vif *mm_vif = (struct mm81x_vif *)vif->drv_priv;
+ enum host_cmd_key_cipher cipher;
+ enum host_cmd_aes_key_len length;
+
+ mutex_lock(&mm->lock);
+
+ if (vif->type == NL80211_IFTYPE_STATION) {
+ aid = mm81x_mac_sta_aid(vif);
+ } else if (sta) {
+ aid = sta->aid;
+ } else {
+ /* Is a group key - AID is unused */
+ WARN_ON((key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
+ aid = 0;
+ }
+
+ switch (cmd) {
+ case SET_KEY: {
+ switch (key->cipher) {
+ case WLAN_CIPHER_SUITE_CCMP:
+ case WLAN_CIPHER_SUITE_CCMP_256:
+ cipher = HOST_CMD_KEY_CIPHER_AES_CCM;
+ break;
+ case WLAN_CIPHER_SUITE_GCMP:
+ case WLAN_CIPHER_SUITE_GCMP_256:
+ cipher = HOST_CMD_KEY_CIPHER_AES_GCM;
+ break;
+ default:
+ /* Cipher suite currently not supported */
+ ret = -EOPNOTSUPP;
+ goto exit;
+ }
+
+ switch (key->keylen) {
+ case 16:
+ length = HOST_CMD_AES_KEY_LEN_LENGTH_128;
+ break;
+ case 32:
+ length = HOST_CMD_AES_KEY_LEN_LENGTH_256;
+ break;
+ default:
+ /* Key length not supported */
+ ret = -EOPNOTSUPP;
+ goto exit;
+ }
+
+ ret = mm81x_cmd_install_key(mm, mm_vif, aid, key, cipher,
+ length);
+ break;
+ }
+ case DISABLE_KEY:
+ ret = mm81x_cmd_disable_key(mm, mm_vif, aid, key);
+ if (ret) {
+ /* Must return 0 */
+ mm81x_warn(mm, "Failed to remove key");
+ ret = 0;
+ }
+ break;
+ default:
+ WARN_ON(1);
+ }
+
+ if (ret) {
+ mm81x_dbg(mm, MM81X_DBG_ANY, "Falling back to software crypto");
+ ret = 1;
+ }
+
+exit:
+ mutex_unlock(&mm->lock);
+ return ret;
+}
+
+static int mm81x_mac_set_frag_threshold(struct ieee80211_hw *hw, int radio_idx,
+ u32 value)
+{
+ int ret = -EINVAL;
+ struct mm81x *mm = hw->priv;
+
+ mutex_lock(&mm->lock);
+ ret = mm81x_cmd_set_frag_threshold(mm, value);
+ mutex_unlock(&mm->lock);
+ return ret;
+}
+
+static void mm81x_rx_h_fill_status(struct mm81x *mm,
+ struct mm81x_skb_rx_status *hdr_rx_status,
+ struct ieee80211_rx_status *rx_status,
+ struct sk_buff *skb)
+{
+ u8 mcs_index;
+ u32 flags = le32_to_cpu(hdr_rx_status->flags);
+ u16 freq_100khz = le16_to_cpu(hdr_rx_status->freq_100khz);
+ __le32 ratecode = hdr_rx_status->mm81x_ratecode;
+
+ rx_status->signal = le16_to_cpu(hdr_rx_status->rssi);
+ rx_status->encoding = RX_ENC_VHT;
+ rx_status->band = NL80211_BAND_S1GHZ;
+ rx_status->freq = KHZ100_TO_MHZ(freq_100khz);
+ rx_status->freq_offset = (freq_100khz % 10) ? 1 : 0;
+ rx_status->nss = NSS_IDX_TO_NSS(mm81x_ratecode_nss_index_get(ratecode));
+
+ if (flags & MM81X_RX_STATUS_FLAGS_DECRYPTED)
+ rx_status->flag |= RX_FLAG_DECRYPTED;
+
+ mcs_index = mm81x_ratecode_mcs_index_get(ratecode);
+ rx_status->rate_idx = (mcs_index == 10) ? 0 : mcs_index;
+
+ if (mm81x_ratecode_sgi_get(ratecode))
+ rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
+}
+
+/*
+ * The firmware passes up NULL vifs for broadcast management frames. Find
+ * the first interface that best fits the frame we are rx'ing. This
+ * has the clear downside if we have two vifs with the same interface type
+ * the 2nd vif will never be targeted. For now, this will have to do.
+ */
+static struct ieee80211_vif *mm81x_rx_h_find_bcast_vif(struct mm81x *mm,
+ struct sk_buff *skb)
+{
+ int vif_id;
+ struct ieee80211_vif *vif;
+ const struct ieee80211_hdr *hdr = (void *)skb->data;
+
+ lockdep_assert_in_rcu_read_lock();
+
+ for (vif_id = 0; vif_id < ARRAY_SIZE(mm->vifs); vif_id++) {
+ vif = mm81x_rcu_dereference_vif_id(mm, vif_id, true);
+ if (!vif)
+ continue;
+
+ if (!ieee80211_is_mgmt(hdr->frame_control))
+ return vif;
+
+ switch (le16_to_cpu(hdr->frame_control) &
+ IEEE80211_FCTL_STYPE) {
+ case IEEE80211_STYPE_BEACON:
+ if (vif->type == NL80211_IFTYPE_STATION)
+ return vif;
+ break;
+ case IEEE80211_STYPE_PROBE_RESP:
+ if (vif->type == NL80211_IFTYPE_STATION)
+ return vif;
+ break;
+ case IEEE80211_STYPE_PROBE_REQ:
+ if (vif->type == NL80211_IFTYPE_AP)
+ return vif;
+ break;
+ default:
+ return vif;
+ }
+ }
+
+ return NULL;
+}
+
+static void mm81x_rx_h_update_sta(struct ieee80211_vif *vif,
+ struct ieee80211_hdr *hdr,
+ struct ieee80211_rx_status *rx_status)
+{
+ struct ieee80211_sta *sta;
+ struct mm81x_sta *msta;
+ u8 *lookup = ieee80211_is_s1g_beacon(hdr->frame_control) ? hdr->addr1 :
+ hdr->addr2;
+
+ lockdep_assert_in_rcu_read_lock();
+
+ sta = ieee80211_find_sta(vif, lookup);
+ if (!sta)
+ return;
+
+ msta = (void *)sta->drv_priv;
+ if (msta->avg_rssi) {
+ msta->avg_rssi =
+ CALC_AVG_RSSI(msta->avg_rssi, rx_status->signal);
+ } else {
+ msta->avg_rssi = rx_status->signal;
+ }
+}
+
+static struct ieee80211_vif *
+mm81x_rx_h_skb_get_vif(struct mm81x *mm, struct sk_buff *skb,
+ struct mm81x_skb_rx_status *hdr_rx_status)
+{
+ u8 vif_id = u32_get_bits(le32_to_cpu(hdr_rx_status->flags),
+ MM81X_RX_STATUS_FLAGS_VIF_ID);
+
+ lockdep_assert_in_rcu_read_lock();
+
+ /*
+ * The firmware passes up broadcast mgmt frames such as beacons with a
+ * NULL VIF. Assign the correct VIF. If no matching VIF was found, the
+ * VIF is not yet up.
+ */
+ if (vif_id == INVALID_VIF_INDEX)
+ return mm81x_rx_h_find_bcast_vif(mm, skb);
+
+ return mm81x_rcu_dereference_vif_id(mm, vif_id, true);
+}
+
+void mm81x_mac_rx_skb(struct mm81x *mm, struct sk_buff *skb,
+ struct mm81x_skb_rx_status *hdr_rx_status)
+{
+ struct ieee80211_vif *vif;
+ struct ieee80211_hw *hw = mm->hw;
+ struct ieee80211_rx_status rx_status;
+ struct ieee80211_hdr *hdr = (void *)skb->data;
+
+ memset(&rx_status, 0, sizeof(rx_status));
+
+ if (!mm->started || !skb->data || !skb->len) {
+ dev_kfree_skb_any(skb);
+ return;
+ }
+
+ mm81x_rx_h_fill_status(mm, hdr_rx_status, &rx_status, skb);
+
+ scoped_guard(rcu) {
+ vif = mm81x_rx_h_skb_get_vif(mm, skb, hdr_rx_status);
+ if (!vif) {
+ dev_kfree_skb_any(skb);
+ return;
+ }
+
+ mm81x_rx_h_update_sta(vif, hdr, &rx_status);
+ }
+
+ memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
+
+ ieee80211_rx_irqsafe(hw, skb);
+}
+
+static void mm81x_mac_ops_flush(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif, u32 queues,
+ bool drop)
+{
+ struct mm81x *mm = hw->priv;
+
+ /* We don't support IEEE80211_HW_QUEUE_CONTROL so flush all queues */
+ if (drop) {
+ /*
+ * No need to call mm81x_skbq_stop_tx_queues as mac80211
+ * has already cancelled each queue prior to calling .flush()
+ */
+ mm81x_skbq_data_traffic_pause(mm);
+
+ flush_work(&mm->hif_work);
+ flush_work(&mm->tx_stale_work);
+
+ mm81x_hif_clear_events(mm);
+ mm81x_hif_flush_tx_data(mm);
+ mm81x_hif_flush_cmds(mm);
+
+ /* Reenable data, not that there will be any */
+ mm81x_skbq_data_traffic_resume(mm);
+ }
+}
+
+static int mm81x_mac_ops_set_rts_threshold(struct ieee80211_hw *hw,
+ int radio_idx, u32 value)
+{
+ struct mm81x *mm = hw->priv;
+
+ mm->rts_threshold = value;
+ return 0;
+}
+
+static void mm81x_mac_ops_sta_rc_update(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_link_sta *link_sta,
+ u32 changed)
+{
+ struct mm81x *mm = hw->priv;
+ struct ieee80211_sta *sta = link_sta->sta;
+ enum ieee80211_sta_state old_state;
+ enum ieee80211_sta_state new_state;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "Rate control config updated (changed %u, peer address %pM)",
+ changed, sta->addr);
+
+ if (!(changed & IEEE80211_RC_BW_CHANGED))
+ return;
+
+ /*
+ * Simulate the disconnection and connection to reinitialize the sta
+ * in mmrc with new BW
+ */
+ old_state = IEEE80211_STA_ASSOC;
+ new_state = IEEE80211_STA_NOTEXIST;
+
+ mm81x_dbg(
+ mm, MM81X_DBG_ANY,
+ "Remove sta, old_state=%d, new_state=%d, changed=0x%x, bw_changed=%d",
+ old_state, new_state, changed,
+ (changed & IEEE80211_RC_BW_CHANGED));
+ mutex_lock(&mm->lock);
+
+ mm81x_rc_sta_state_check(mm, vif, sta, old_state, new_state);
+
+ old_state = IEEE80211_STA_NOTEXIST;
+ new_state = IEEE80211_STA_ASSOC;
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "Add sta, old_state=%d, new_state=%d",
+ old_state, new_state);
+
+ mm81x_rc_sta_state_check(mm, vif, sta, old_state, new_state);
+
+ mutex_unlock(&mm->lock);
+}
+
+static void mm81x_mac_ops_sta_statistics(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct station_info *sinfo)
+{
+ struct mm81x_sta *msta = (struct mm81x_sta *)sta->drv_priv;
+ struct mm81x *mm = hw->priv;
+ const struct mmrc_table *tb = msta->rc.tb;
+ struct mmrc_rate rate;
+
+ if (!tb || tb->best_tp.rate == MMRC_MCS_UNUSED) {
+ sinfo->filled &= ~BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
+ return;
+ }
+
+ rate = tb->best_tp;
+ sinfo->txrate.mcs = rate.rate;
+ sinfo->txrate.nss = NSS_IDX_TO_NSS(rate.ss);
+ sinfo->txrate.flags = RATE_INFO_FLAGS_S1G_MCS;
+ switch (rate.bw) {
+ case MMRC_BW_1MHZ:
+ sinfo->txrate.bw = RATE_INFO_BW_1;
+ break;
+ case MMRC_BW_2MHZ:
+ sinfo->txrate.bw = RATE_INFO_BW_2;
+ break;
+ case MMRC_BW_4MHZ:
+ sinfo->txrate.bw = RATE_INFO_BW_4;
+ break;
+ case MMRC_BW_8MHZ:
+ sinfo->txrate.bw = RATE_INFO_BW_8;
+ break;
+ default:
+ break;
+ }
+
+ if (rate.guard == MMRC_GUARD_SHORT)
+ sinfo->txrate.flags |= (RATE_INFO_FLAGS_SHORT_GI);
+
+ mm81x_dbg(mm, MM81X_DBG_ANY, "mcs: %d, bw: %d, flag: 0x%x", rate.rate,
+ rate.bw, sinfo->txrate.flags);
+ sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
+}
+
+static u32 mm81x_get_expected_throughput(struct ieee80211_hw *hw,
+ struct ieee80211_sta *sta)
+{
+ struct mm81x_sta *msta = (struct mm81x_sta *)sta->drv_priv;
+ struct mm81x *mm = hw->priv;
+ const struct mmrc_table *tb = msta->rc.tb;
+ struct mmrc_rate rate;
+ u32 tput;
+
+ if (!tb || tb->best_tp.rate == MMRC_MCS_UNUSED)
+ return 0;
+
+ rate = tb->best_tp;
+ tput = BPS_TO_KBPS(mmrc_calculate_theoretical_throughput(rate));
+ mm81x_dbg(mm, MM81X_DBG_ANY,
+ "Throughput: MCS: %d, BW: %d, GI: %d -> %u", rate.rate,
+ 1 << rate.bw, rate.guard, tput);
+
+ return tput;
+}
+
+static void mm81x_mac_restart_cleanup_iter(void *data, u8 *mac,
+ struct ieee80211_vif *vif)
+{
+ if (vif->type == NL80211_IFTYPE_AP)
+ mm81x_mac_beacon_finish((struct mm81x_vif *)vif->drv_priv);
+}
+
+static void mm81x_mac_restart_cleanup(struct mm81x *mm)
+{
+ ieee80211_iterate_active_interfaces(mm->hw, IEEE80211_IFACE_ITER_NORMAL,
+ mm81x_mac_restart_cleanup_iter,
+ NULL);
+ mm81x_mac_hw_scan_finish(mm);
+}
+
+static int mm81x_mac_restart(struct mm81x *mm)
+{
+ int ret;
+ u32 chip_id;
+
+ lockdep_assert_held(&mm->lock);
+
+ mm->started = false;
+ mm81x_ps_disable(mm);
+ mm81x_bus_set_irq(mm, false);
+ mm81x_hw_irq_clear(mm);
+ ieee80211_stop_queues(mm->hw);
+
+ set_bit(MM81X_STATE_DATA_TX_STOPPED, &mm->state_flags);
+ set_bit(MM81X_STATE_DATA_QS_STOPPED, &mm->state_flags);
+
+ /* Allow time for in-transit tx/rx packets to settle */
+ mdelay(MM81X_HW_RESTART_DELAY_MS);
+ flush_work(&mm->hif_work);
+ flush_work(&mm->tx_stale_work);
+ mm81x_hif_clear_events(mm);
+ mm81x_hif_flush_tx_data(mm);
+ mm81x_hif_flush_cmds(mm);
+
+ mm81x_claim_bus(mm);
+ ret = mm81x_reg32_read(mm, MM81X_REG_CHIP_ID(mm), &chip_id);
+ mm81x_release_bus(mm);
+
+ if (ret < 0) {
+ mm81x_err(mm, "Failed to access HW: %d", ret);
+ goto exit;
+ }
+
+ mm81x_mac_restart_cleanup(mm);
+
+ ret = mm81x_fw_init(mm, true);
+ if (ret < 0) {
+ mm81x_err(mm, "Failed to init firmware: %d", ret);
+ goto exit;
+ }
+
+ mm81x_hw_irq_enable(mm, MM81X_INT_HW_STOP_NOTIFICATION_NUM, true);
+
+ ret = mm81x_fw_parse_ext_host_tbl(mm);
+ if (ret) {
+ mm81x_err(mm, "failed to parse extended host table: %d", ret);
+ goto exit;
+ }
+
+ mm81x_mac_caps_init(mm);
+
+ mm81x_bus_set_irq(mm, true);
+ clear_bit(MM81X_STATE_DATA_TX_STOPPED, &mm->state_flags);
+ clear_bit(MM81X_STATE_DATA_QS_STOPPED, &mm->state_flags);
+ clear_bit(MM81X_STATE_CHIP_UNRESPONSIVE, &mm->state_flags);
+ clear_bit(MM81X_STATE_RELOAD_FW_AFTER_START, &mm->state_flags);
+ mm81x_mac_check_fw_disabled_chans(mm->hw);
+ ieee80211_restart_hw(mm->hw);
+
+exit:
+ mm81x_ps_enable(mm);
+ return ret;
+}
+
+static int mm81x_mac_ops_add_interface(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+ int ret = 0;
+ struct mm81x *mm = hw->priv;
+ struct mm81x_vif *mm_vif = (struct mm81x_vif *)vif->drv_priv;
+
+ if (test_bit(MM81X_STATE_RELOAD_FW_AFTER_START, &mm->state_flags)) {
+ mm81x_info(mm, "Restarting chip with regdom: %s", mm->country);
+ mutex_lock(&mm->lock);
+
+ ret = mm81x_mac_restart(mm);
+ if (ret) {
+ mm81x_err(mm, "Failed to restart chip");
+ goto exit;
+ }
+
+ mutex_unlock(&mm->lock);
+
+ /*
+ * mac_restart will trigger ieee80211_hw_restart and
+ * add_interface will re-enter. just exit here instead.
+ */
+ return 0;
+ }
+
+ mutex_lock(&mm->lock);
+ vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
+ mm_vif->u.ap.beaconing_enabled = false;
+ mm_vif->mm = mm;
+
+ ret = mm81x_cmd_add_if(mm, &mm_vif->id, vif->addr, vif->type);
+ if (ret) {
+ mm81x_err(mm, "mm81x_cmd_add_if failed %d", ret);
+ goto exit;
+ }
+
+ if (mm_vif->id >= ARRAY_SIZE(mm->vifs)) {
+ mm81x_err(mm, "vif_id is too large %u", mm_vif->id);
+ ret = -EOPNOTSUPP;
+ goto exit;
+ }
+
+ if (mm_vif->id != (mm_vif->id & MM81X_TX_CONF_FLAGS_VIF_ID_MASK)) {
+ mm81x_err(mm, "invalid vif_id %u", mm_vif->id);
+ ret = -EOPNOTSUPP;
+ goto exit;
+ }
+
+ rcu_assign_pointer(mm->vifs[mm_vif->id], vif);
+
+ if (vif->type == NL80211_IFTYPE_AP)
+ mm81x_mac_beacon_init(mm_vif);
+
+ ret = mm81x_cmd_get_capabilities(mm, mm_vif->id, &mm->fw_caps);
+ if (ret) {
+ mm81x_err(mm, "mm81x_cmd_get_capabilities failed for vif %d",
+ mm_vif->id);
+ goto exit;
+ }
+
+ ieee80211_wake_queues(mm->hw);
+exit:
+ mutex_unlock(&mm->lock);
+ return ret;
+}
+
+static const struct ieee80211_ops mm81x_ops = {
+ .start = mm81x_mac_ops_start,
+ .stop = mm81x_mac_ops_stop,
+ .config = mm81x_mac_ops_config,
+ .wake_tx_queue = ieee80211_handle_wake_tx_queue,
+ .tx = mm81x_mac_ops_tx,
+ .add_interface = mm81x_mac_ops_add_interface,
+ .remove_interface = mm81x_mac_ops_remove_interface,
+ .configure_filter = mm81x_mac_ops_configure_filter,
+ .sta_state = mm81x_mac_ops_sta_state,
+ .flush = mm81x_mac_ops_flush,
+ .set_frag_threshold = mm81x_mac_set_frag_threshold,
+ .set_rts_threshold = mm81x_mac_ops_set_rts_threshold,
+ .link_sta_rc_update = mm81x_mac_ops_sta_rc_update,
+ .sta_statistics = mm81x_mac_ops_sta_statistics,
+ .get_expected_throughput = mm81x_get_expected_throughput,
+ .hw_scan = mm81x_mac_ops_hw_scan,
+ .cancel_hw_scan = mm81x_mac_ops_cancel_hw_scan,
+ .get_txpower = mm81x_mac_ops_get_txpower,
+ .bss_info_changed = mm81x_mac_ops_bss_info_changed,
+ .prepare_multicast = mm81x_mac_ops_prepare_multicast,
+ .conf_tx = mm81x_mac_ops_conf_tx,
+ .ampdu_action = mm81x_mac_ops_ampdu_action,
+ .set_key = mm81x_mac_ops_set_key,
+ .add_chanctx = mm81x_mac_ops_add_chanctx,
+ .remove_chanctx = mm81x_mac_ops_remove_chanctx,
+ .change_chanctx = mm81x_mac_ops_change_chanctx,
+ .assign_vif_chanctx = mm81x_mac_ops_assign_vif_chanctx,
+ .unassign_vif_chanctx = mm81x_mac_ops_unassign_vif_chanctx,
+};
+
+struct mm81x *mm81x_mac_create(size_t priv_size, struct device *dev)
+{
+ struct ieee80211_hw *hw;
+ struct mm81x *mm;
+
+ hw = ieee80211_alloc_hw(sizeof(*mm) + priv_size, &mm81x_ops);
+ if (!hw) {
+ dev_err(dev, "ieee80211_alloc_hw failed\r\n");
+ return NULL;
+ }
+
+ SET_IEEE80211_DEV(hw, dev);
+ memset(hw->priv, 0, sizeof(*mm));
+
+ mm = hw->priv;
+ mm->hw = hw;
+ mm->dev = dev;
+ mutex_init(&mm->lock);
+ mutex_init(&mm->cmd_lock);
+ mutex_init(&mm->cmd_wait);
+
+ return mm;
+}
+
+static void mm81x_reg_notifier(struct wiphy *wiphy,
+ struct regulatory_request *request)
+{
+ int ret;
+ struct mm81x *mm = wiphy_to_ieee80211_hw(wiphy)->priv;
+
+ if (mm81x_reg_h_cc_equal(request->alpha2, mm->country))
+ return;
+
+ memcpy(mm->country, request->alpha2, sizeof(mm->country));
+
+ mutex_lock(&mm->lock);
+
+ ret = mm81x_mac_restart(mm);
+ if (ret) {
+ mm81x_err(mm, "Failed to restart chip: %d", ret);
+ dump_stack();
+ }
+
+ mutex_unlock(&mm->lock);
+}
+
+static void mm81x_mac_config_hw(struct mm81x *mm)
+{
+ int i;
+ struct ieee80211_hw *hw = mm->hw;
+ struct wiphy *wiphy;
+
+ for (i = 0; i < NUM_NL80211_BANDS; i++)
+ hw->wiphy->bands[i] = NULL;
+
+ hw->wiphy->bands[NL80211_BAND_S1GHZ] = &mm_band_s1ghz;
+ hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP) |
+ BIT(NL80211_IFTYPE_STATION);
+ hw->wiphy->reg_notifier = mm81x_reg_notifier;
+ hw->queues = MM81X_HW_QUEUE_COUNT;
+ hw->max_rates = MM81X_HW_MAX_RATES;
+ hw->max_report_rates = MM81X_HW_MAX_REPORT_RATES;
+ hw->max_rate_tries = MM81X_HW_MAX_RATE_TRIES;
+ hw->tx_sk_pacing_shift = MM81X_HW_TX_SK_PACING_SHIFT;
+ hw->vif_data_size = sizeof(struct mm81x_vif);
+ hw->sta_data_size = sizeof(struct mm81x_sta);
+ hw->extra_tx_headroom =
+ sizeof(struct mm81x_skb_hdr) + mm81x_bus_get_alignment(mm);
+
+ mm->wiphy = hw->wiphy;
+
+ ieee80211_hw_set(hw, SIGNAL_DBM);
+ ieee80211_hw_set(hw, MFP_CAPABLE);
+ ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
+ ieee80211_hw_set(hw, AMPDU_AGGREGATION);
+ ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
+ ieee80211_hw_set(hw, HAS_RATE_CONTROL);
+ ieee80211_hw_set(hw, SUPPORTS_PS);
+ ieee80211_hw_set(hw, NEED_DTIM_BEFORE_ASSOC);
+ ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
+ ieee80211_hw_set(hw, SUPPORTS_TX_FRAG);
+
+ SET_IEEE80211_PERM_ADDR(hw, mm->macaddr);
+
+ wiphy = mm->wiphy;
+
+ wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
+ wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
+
+ if (!mm->ps.enable)
+ wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+
+ wiphy->features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
+ NL80211_FEATURE_TX_POWER_INSERTION;
+
+ wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);
+ wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
+
+ wiphy->iface_combinations = mm_if_combs;
+ wiphy->n_iface_combinations = ARRAY_SIZE(mm_if_combs);
+ wiphy->max_scan_ie_len = MM81X_MAX_SCAN_IE_LEN;
+ wiphy->max_scan_ssids = MM81X_MAX_SCAN_SSIDS;
+ wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
+ wiphy->max_remain_on_channel_duration =
+ MM81X_MAX_REMAIN_ON_CHAN_DURATION;
+}
+
+static void mm81x_stale_tx_status_timer(struct timer_list *t)
+{
+ struct mm81x *mm = timer_container_of(mm, t, stale_status.timer);
+
+ spin_lock_bh(&mm->stale_status.lock);
+ if (mm81x_hif_get_tx_status_pending_count(mm))
+ queue_work(mm->net_wq, &mm->tx_stale_work);
+ spin_unlock_bh(&mm->stale_status.lock);
+}
+
+static void mm81x_stale_tx_status_timer_finish(struct mm81x *mm)
+{
+ timer_delete_sync_try(&mm->stale_status.timer);
+}
+
+static void mm81x_mac_stale_tx_status_timer_init(struct mm81x *mm)
+{
+ spin_lock_init(&mm->stale_status.lock);
+ timer_setup(&mm->stale_status.timer, mm81x_stale_tx_status_timer, 0);
+}
+
+static int mm81x_mac_init(struct mm81x *mm)
+{
+ int ret;
+
+ mm->tx_power_mbm = INT_MAX;
+ mm->tx_max_power_mbm = INT_MAX;
+ mm->rts_threshold = IEEE80211_MAX_RTS_THRESHOLD;
+
+ ret = mm81x_ps_init(mm);
+ if (ret < 0)
+ return ret;
+
+ mm81x_mac_config_hw(mm);
+ mm81x_mac_hw_scan_init(mm);
+ mm81x_mac_stale_tx_status_timer_init(mm);
+
+ return 0;
+}
+
+int mm81x_mac_register(struct mm81x *mm)
+{
+ int ret;
+ struct ieee80211_hw *hw = mm->hw;
+
+ ret = mm81x_mac_init(mm);
+ if (ret) {
+ mm81x_err(mm, "mm81x_mac_init failed %d", ret);
+ return ret;
+ }
+
+ ret = ieee80211_register_hw(hw);
+ if (ret) {
+ mm81x_err(mm, "ieee80211_register_hw failed %d", ret);
+ mm81x_mac_unregister(mm);
+ return ret;
+ }
+
+ mm81x_rc_init(mm);
+
+ /*
+ * At this stage, we know bus and pager system interrupts are enabled.
+ * Trigger the receive workqueue to drain any incoming chip-to-host
+ * pending packets been pushed in the period between the firmware
+ * initialization and interrupts being enabled.
+ */
+ set_bit(MM81X_HIF_EVT_RX_PEND, &mm->hif.event_flags);
+ queue_work(mm->chip_wq, &mm->hif_work);
+
+ return ret;
+}
+
+static void mm81x_ieee80211_deinit(struct mm81x *mm)
+{
+ ieee80211_stop_queues(mm->hw);
+ ieee80211_unregister_hw(mm->hw);
+}
+
+static void mm81x_mac_deinit(struct mm81x *mm)
+{
+ mm81x_ieee80211_deinit(mm);
+ mm81x_hif_flush_tx_data(mm);
+ mm81x_hif_flush_cmds(mm);
+}
+
+void mm81x_mac_unregister(struct mm81x *mm)
+{
+ mm81x_ps_disable(mm);
+ mm81x_rc_deinit(mm);
+ mm81x_mac_hw_scan_destroy(mm);
+ mm81x_mac_deinit(mm);
+ mm81x_stale_tx_status_timer_finish(mm);
+ mm81x_ps_finish(mm);
+}
+
+void mm81x_mac_destroy(struct mm81x *mm)
+{
+ ieee80211_free_hw(mm->hw);
+}
--
2.43.0
^ permalink raw reply related
* [PATCH wireless-next 15/35] wifi: mm81x: add mac.h
From: Lachlan Hodges @ 2026-02-27 4:10 UTC (permalink / raw)
To: johannes, Lachlan Hodges, Dan Callaghan, Arien Judge
Cc: ayman.grais, linux-wireless, linux-kernel
In-Reply-To: <20260227041108.66508-1-lachlan.hodges@morsemicro.com>
(Patches split per file for review, see cover letter for more
information)
Signed-off-by: Lachlan Hodges <lachlan.hodges@morsemicro.com>
---
drivers/net/wireless/morsemicro/mm81x/mac.h | 69 +++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 drivers/net/wireless/morsemicro/mm81x/mac.h
diff --git a/drivers/net/wireless/morsemicro/mm81x/mac.h b/drivers/net/wireless/morsemicro/mm81x/mac.h
new file mode 100644
index 000000000000..6e27ddf900b3
--- /dev/null
+++ b/drivers/net/wireless/morsemicro/mm81x/mac.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2026 Morse Micro
+ */
+
+#ifndef _MM81X_MAC_H_
+#define _MM81X_MAC_H_
+
+#include "core.h"
+#include "command.h"
+
+struct mm81x_queue_params {
+ u8 uapsd;
+ u8 aci;
+ u8 aifs;
+ u16 cw_min;
+ u16 cw_max;
+ u32 txop;
+};
+
+static inline bool mm81x_mac_is_sta_vif_associated(struct ieee80211_vif *vif)
+{
+ return vif->cfg.assoc;
+}
+
+static inline u32 mm81x_vif_generate_cssid(struct ieee80211_vif *vif)
+{
+ return mm81x_generate_cssid(vif->cfg.ssid, vif->cfg.ssid_len);
+}
+
+static inline u16 mm81x_mac_sta_aid(struct ieee80211_vif *vif)
+{
+ return vif->cfg.aid;
+}
+
+static inline __le32 mac2leuint32(const unsigned char *addr)
+{
+ return cpu_to_le32(((u32)(addr[2]) << 24) | ((u32)(addr[3]) << 16) |
+ ((u32)(addr[4]) << 8) | ((u32)(addr[5])));
+}
+
+static inline struct ieee80211_vif *
+mm81x_rcu_dereference_vif_id(struct mm81x *mm, u8 vif_id, bool rcu)
+{
+ if (WARN_ON(vif_id >= ARRAY_SIZE(mm->vifs)))
+ return NULL;
+
+ if (rcu)
+ return rcu_dereference(mm->vifs[vif_id]);
+
+ return rcu_dereference_protected(mm->vifs[vif_id],
+ lockdep_is_held(&mm->lock));
+}
+
+int mm81x_tx_h_get_attempts(struct mm81x *mm,
+ struct mm81x_skb_tx_status *tx_sts);
+struct mm81x *mm81x_mac_create(size_t priv_size, struct device *dev);
+int mm81x_mac_register(struct mm81x *mm);
+void mm81x_mac_destroy(struct mm81x *mm);
+void mm81x_mac_unregister(struct mm81x *mm);
+int mm81x_mac_event_recv(struct mm81x *mm, struct sk_buff *skb);
+void mm81x_mac_rx_skb(struct mm81x *mm, struct sk_buff *skb,
+ struct mm81x_skb_rx_status *hdr_rx_status);
+void mm81x_mac_beacon_irq_handle(struct mm81x *mm, u32 status);
+
+u8 *mm81x_hw_scan_h_insert_tlvs(struct mm81x_hw_scan_params *params, u8 *buf);
+size_t mm81x_hw_scan_h_get_cmd_size(struct mm81x_hw_scan_params *params);
+void mm81x_tx_h_check_aggr(struct ieee80211_sta *pubsta, struct sk_buff *skb);
+#endif /* !_MM81X_MAC_H_ */
--
2.43.0
^ permalink raw reply related
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