* Re: SDRAM failures on MPC5200B (Xia Yu)
[not found] <mailman.1484.1184968961.8639.linuxppc-embedded@ozlabs.org>
@ 2007-07-21 1:48 ` 夏雨
0 siblings, 0 replies; only message in thread
From: 夏雨 @ 2007-07-21 1:48 UTC (permalink / raw)
To: lokowich; +Cc: linuxppc-embedded
Hi! According to the MPC5200B user's manual, you should define the S-delay
register(MBAR + 0x0190) to 0x04 ,and the initialization sequence of the DDR
should be modified according to the data sheet from MICRON. I have rewrite
the function as below:
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = (SDRAM_CONTROL & 0xefffffff)|
0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = (SDRAM_CONTROL & 0xefffffff)|
0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = (SDRAM_CONTROL & 0xefffffff) |
0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = (SDRAM_CONTROL & 0xefffffff) |
0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = (SDRAM_CONTROL & 0xefffffff) |
0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
udelay(3); //delay 400clks;
}
Hope to be helpful!
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2007-07-21 1:48 ` SDRAM failures on MPC5200B (Xia Yu) 夏雨
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