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From: "LC Geldenhuys" <lourens@mecalc.co.za>
To: <linuxppc-embedded@lists.linuxppc.org>
Subject: RE: Kernel Mode Software Emulation NIP: 00001FFC - cache coherency problem on m8xx processors
Date: Fri, 26 Mar 2004 09:23:52 +0200	[thread overview]
Message-ID: <002401c41303$4dae8890$8702a8c0@lcgnotebook> (raw)
In-Reply-To: <20040325231357.GA22460@logos.cnet>


> -----Original Message-----
> From: owner-linuxppc-embedded@lists.linuxppc.org
> [mailto:owner-linuxppc-embedded@lists.linuxppc.org] On Behalf
> Of Marcelo Tosatti
> Sent: 26 March 2004 01:14 AM
> To: linuxppc-embedded@lists.linuxppc.org
> Subject: Kernel Mode Software Emulation NIP: 00001FFC - cache
> coherency problem on m8xx processors

<snip>

> I'm not exactly sure why we were jumping to "1FFC" instead of "2000",
> but adding "isync" before "bl transfer_to_handler" in both
> DecrementTimer
> and HardwareInterrupt fixed the problem for us.

This sounds distinctly familiar to the CPU13 Errata. Do you have
Instruction fetch show cycles enabled in ICTRL[IST_SER]? See:
http://e-www.motorola.com/files/32bit/doc/errata/MPC860CE.pdf

Cheers,
  Lourens


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

  parent reply	other threads:[~2004-03-26  7:23 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-03-25 23:13 Kernel Mode Software Emulation NIP: 00001FFC - cache coherency problem on m8xx processors Marcelo Tosatti
2004-03-26  6:51 ` Dan Malek
2004-03-26  9:04   ` Wolfgang Denk
2004-03-26 13:44     ` Dan Malek
2004-03-26  7:23 ` LC Geldenhuys [this message]
2004-03-26  8:07   ` Dan Malek

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