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* Re: Re: 82xx IRQ handling
@ 2005-12-12  8:31 debora liu
  0 siblings, 0 replies; only message in thread
From: debora liu @ 2005-12-12  8:31 UTC (permalink / raw)
  To: Dmytro Bablinyuk; +Cc: Linuxppc-embedded

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Hello, Dmytro Bablinyuk

In message <2005-12-12 14:00:46 dmytro.bablinyuk@rftechnology.com.au> you wrote:

>
>By the way question - shall I program somewhere an edge of the IRQ or it 
>always triggers on the rising edge?
>
IRQ_POLARITY_POSITIVE		/* high level or low->high edge */
IRQ_POLARITY_NEGATIVE   	/* low level or high->low edge */



you should modify OpenPIC_InitSenses, example my board:
static u_char sc82xx_openpic_initsenses[] __initdata = {
#if defined(CONFIG_SVM_GEMINI)
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* EPIC IRQ 0,PCI0 */
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* EPIC IRQ 1 ,PCI1*/
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),       /* EPIC IRQ 2 ,PCI2 */
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* DUART CH1  */
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),    /* DUART CH2  */
  (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),    /* EPIC IRQ3, PCI3 or DPRAM */
  (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),    /*  EPIC IRQ4, DPRAM */

#elif defined (CONFIG_SVM_IT6160A)
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* EPIC IRQ 0 */
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* EPIC IRQ 1 */
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* EPIC IRQ 2,  xr16L788 chip1*/
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* DUART CH1  */
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),    /* DUART CH2  */
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),    /* EPIC IRQ3, xr16L788 chip2*/
  (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),    /* EPIC IRQ4,spare */

#else
#error No board defined.!!!
#endif
};

static void __init
sc82xx_init_IRQ(void)
{
  OpenPIC_InitSenses = sc82xx_openpic_initsenses;
  OpenPIC_NumInitSenses = sizeof(sc82xx_openpic_initsenses);

  /*
   * We need to tell openpic_set_sources where things actually are.
   * mpc10x_common will setup OpenPIC_Addr at ioremap(EUMB phys base +
   * EPIC offset (0x40000));  The EPIC IRQ Register Address Map -
   * Interrupt Source Configuration Registers gives these numbers
   * as offsets starting at 0x50200, we need to adjust occordinly.
   */

  openpic_set_sources(0, 3, OpenPIC_Addr + 0x10200);  /* 0=IRQ0,  1=IRQ1, 2=IRQ2  *
  openpic_set_sources(3, 2, OpenPIC_Addr + 0x11120);  /* 3=UART0, 4=UART1         *
  openpic_set_sources(5, 2, OpenPIC_Addr + 0x10260);  /* 5=IRQ3,  6=IRQ4          *

        openpic_init (0);
}



= = = = = = = = = = = = = = = = = = = =
				 
        debora liu
        deboraliu@tom.com
          2005-12-12

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