[PATCH] ppc32 8xx: Fix r3 thrashing due to 8MB TLB page instantiation (!CONFIG_8xx

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* [PATCH] ppc32 8xx: Fix r3 thrashing due to 8MB TLB page instantiation (!CONFIG_8xx_CPU6) @ 2006-05-05 20:09 Marcelo Tosatti 0 siblings, 0 replies; 2+ messages in thread From: Marcelo Tosatti @ 2006-05-05 20:09 UTC (permalink / raw) To: Paul Mackerras; +Cc: David Jander, linux-ppc-embedded Instantiation of 8MB pages on the TLB cache for the kernel static mapping thrashes r3 register on !CONFIG_8xx_CPU6 configurations. Signed-off-by: Marcelo Tosatti <marcelo@kvack.org> diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ec53c7d..7a2f205 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -355,9 +355,7 @@ #endif . = 0x1200 DataStoreTLBMiss: -#ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) -#endif DO_8xx_CPU6(0x3f80, r3) mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mfcr r10 @@ -417,9 +415,7 @@ #endif lwz r11, 0(r0) mtcr r11 lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is an instruction TLB error on the MPC8xx. This could be due ^ permalink raw reply related [flat|nested] 2+ messages in thread

* [PATCH] ppc32 8xx: Fix r3 thrashing due to 8MB TLB page instantiation (!CONFIG_8xx_CPU6) @ 2006-05-05 20:22 Marcelo Tosatti 0 siblings, 0 replies; 2+ messages in thread From: Marcelo Tosatti @ 2006-05-05 20:22 UTC (permalink / raw) To: Paul Mackerras; +Cc: David Jander, linux-ppc-embedded (please ignore last patch, its incomplete) Instantiation of 8MB pages on the TLB cache for the kernel static mapping thrashes r3 register on !CONFIG_8xx_CPU6 configurations. Signed-off-by: Marcelo Tosatti <marcelo@kvack.org> diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ec53c7d..09b3adc 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -355,9 +355,7 @@ #endif . = 0x1200 DataStoreTLBMiss: -#ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) -#endif DO_8xx_CPU6(0x3f80, r3) mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mfcr r10 @@ -417,9 +415,7 @@ #endif lwz r11, 0(r0) mtcr r11 lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is an instruction TLB error on the MPC8xx. This could be due @@ -500,9 +496,7 @@ LoadLargeDTLB: lwz r11, 4(r0) lwz r12, 16(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is the data TLB error on the MPC8xx. This could be due to ^ permalink raw reply related [flat|nested] 2+ messages in thread

end of thread, other threads:[~2006-05-07 9:11 UTC | newest] Thread overview: 2+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2006-05-05 20:22 [PATCH] ppc32 8xx: Fix r3 thrashing due to 8MB TLB page instantiation (!CONFIG_8xx_CPU6) Marcelo Tosatti -- strict thread matches above, loose matches on Subject: below -- 2006-05-05 20:09 Marcelo Tosatti