MPC5200B XLB BSDIS question

MPC5200B XLB BSDIS question

[Roman Fietze]

Hello list,

In our old, modified 2.4.25 I had a statement that sets the bit BSDIS
(real world bit 16, Freescale bit 15) in the XLB config register for
the MPC5200B.

Checking the XLB config of "my" 2.6.32-rc7 doesn't show this bit set
(XLB config reads 0x0000a006).

But this gives me trouble when running under high (BestComm) load. I
have a stress test programm that writes data via PATA to an ext3
filesystem as fast as possible. At the same time I'm using the SCLPC
together with BestComm to read data from FLASH as fast as possible in
64KiB blocks.

Without this bit set I have wrong data in the DMA receive buffer,
almost always only in the first data word (32 bits wide).

And I also have wrong data if I do not invalidate_dcache_range my DMA
buffer before starting the BC task. Looking at dma_map_single or the
old pci_map_single shows me, that they do the cache invalidation on
architecture with non coherent cache, the MPC5200 should be one of
them.

See this old thread that seems to second my theory about a problem in
the MPC5200B, which wouldn't be the first one:

http://www.mail-archive.com/linuxppc-embedded@ozlabs.org/msg02842.html


Is there a reason not to set that bit? Is it true, as I believe it,
that the "polairity" of this bit is documented the wrong way e.g. in
=46reescale's AN3045?


Roman

=2D-=20
Roman Fietze                Telemotive AG B=FCro M=FChlhausen
Breitwiesen                              73347 M=FChlhausen
Tel.: +49(0)7335/18493-45        http://www.telemotive.de