* [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support @ 2010-03-19 15:47 Sergey Temerkhanov 2010-03-19 15:49 ` Sergey Temerkhanov 0 siblings, 1 reply; 4+ messages in thread From: Sergey Temerkhanov @ 2010-03-19 15:47 UTC (permalink / raw) To: linuxppc-dev This patch enables support for Xilinx Virtex 4 FX singe-float FPU. Caveats: - Hard-float binaries which rely on in-kernel math emulation will give wrong results since they expect 64-bit double-precision instead of 32-bit single- precision numbers. Regards, Sergey Temerkhanov ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support 2010-03-19 15:47 [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support Sergey Temerkhanov @ 2010-03-19 15:49 ` Sergey Temerkhanov 2010-05-19 16:52 ` Grant Likely 0 siblings, 1 reply; 4+ messages in thread From: Sergey Temerkhanov @ 2010-03-19 15:49 UTC (permalink / raw) To: linuxppc-dev [-- Attachment #1: Type: Text/Plain, Size: 40 bytes --] The patch. Regards, Resgey Temerkhanov [-- Attachment #2: fp.patch --] [-- Type: text/x-patch, Size: 5213 bytes --] diff -r 9d9ac97e095d .config --- a/.config Thu Feb 25 21:23:42 2010 +0300 +++ b/.config Thu Feb 25 21:49:02 2010 +0300 @@ -14,10 +14,12 @@ CONFIG_40x=y # CONFIG_44x is not set # CONFIG_E200 is not set +CONFIG_PPC_FPU=y CONFIG_4xx=y CONFIG_PPC_MMU_NOHASH=y # CONFIG_PPC_MM_SLICES is not set CONFIG_NOT_COHERENT_CACHE=y +CONFIG_XILINX_FPU=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set @@ -227,7 +229,7 @@ CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y # CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set -CONFIG_MATH_EMULATION=y +# CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set # CONFIG_SWIOTLB is not set CONFIG_PPC_NEED_DMA_SYNC_OPS=y diff -r 9d9ac97e095d arch/powerpc/include/asm/ppc_asm.h --- a/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:49:02 2010 +0300 @@ -85,13 +85,23 @@ #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + +#ifdef CONFIG_XILINX_FPU +#define stfr stfs +#define lfr lfs +#else +#define stfr stfd +#define lfr lfd +#endif + + +#define SAVE_FPR(n, base) stfr n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfr n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) diff -r 9d9ac97e095d arch/powerpc/kernel/fpu.S --- a/arch/powerpc/kernel/fpu.S Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/kernel/fpu.S Thu Feb 25 21:49:02 2010 +0300 @@ -57,6 +57,9 @@ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_FPU + oris r5,r5,MSR_VEC@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r5,r5,MSR_VSX@h @@ -85,6 +88,9 @@ toreal(r5) PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_FPU + oris r10,r10,MSR_VEC@h +#endif andc r4,r4,r10 /* disable FP for previous task */ PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1: @@ -94,6 +100,9 @@ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ lwz r4,THREAD_FPEXC_MODE(r5) ori r9,r9,MSR_FP /* enable FP for current */ +#ifdef CONFIG_XILINX_FPU + oris r9,r9,MSR_VEC@h +#endif or r9,r9,r4 #else ld r4,PACACURRENT(r13) @@ -124,6 +133,9 @@ _GLOBAL(giveup_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_FPU + oris r5,r5,MSR_VEC@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r5,r5,MSR_VSX@h @@ -145,6 +157,9 @@ beq 1f PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r3,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_FPU + oris r3,r3,MSR_VEC@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r3,r3,MSR_VSX@h diff -r 9d9ac97e095d arch/powerpc/kernel/head_40x.S --- a/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:49:02 2010 +0300 @@ -420,7 +420,19 @@ addi r3,r1,STACK_FRAME_OVERHEAD EXC_XFER_STD(0x700, program_check_exception) +/* 0x0800 - FPU unavailable Exception */ +#ifdef CONFIG_PPC_FPU + START_EXCEPTION(0x0800, FloatingPointUnavailable) + NORMAL_EXCEPTION_PROLOG + beq 1f; \ + bl load_up_fpu; /* if from user, just load it up */ \ + b fast_exception_return; \ +1: addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) +#else EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) +#endif + EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) @@ -432,7 +444,7 @@ EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0F20, Trap_0F, unknown_exception, EXC_XFER_EE) /* 0x1000 - Programmable Interval Timer (PIT) Exception */ START_EXCEPTION(0x1000, Decrementer) @@ -821,8 +833,10 @@ * The PowerPC 4xx family of processors do not have an FPU, so this just * returns. */ +#ifndef CONFIG_PPC_FPU _ENTRY(giveup_fpu) blr +#endif /* This is where the main kernel code starts. */ diff -r 9d9ac97e095d arch/powerpc/platforms/Kconfig.cputype --- a/arch/powerpc/platforms/Kconfig.cputype Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/platforms/Kconfig.cputype Thu Feb 25 21:49:02 2010 +0300 @@ -290,4 +290,9 @@ config CHECK_CACHE_COHERENCY bool +config XILINX_FPU + bool "Xilinx softFPU" + select PPC_FPU + depends on 40x + endmenu ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support 2010-03-19 15:49 ` Sergey Temerkhanov @ 2010-05-19 16:52 ` Grant Likely 2010-05-20 9:44 ` Sergey Temerkhanov 0 siblings, 1 reply; 4+ messages in thread From: Grant Likely @ 2010-05-19 16:52 UTC (permalink / raw) To: Sergey Temerkhanov; +Cc: linuxppc-dev On Fri, Mar 19, 2010 at 9:49 AM, Sergey Temerkhanov <temerkhanov@cifronik.ru> wrote: > The patch. > > Regards, Resgey Temerkhanov Hi Sergey. Comments below. > diff -r 9d9ac97e095d .config > --- a/.config Thu Feb 25 21:23:42 2010 +0300 > +++ b/.config Thu Feb 25 21:49:02 2010 +0300 .config changes should not appear in your patch file. > diff -r 9d9ac97e095d arch/powerpc/include/asm/ppc_asm.h > --- a/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:23:42 2010 +0300 > +++ b/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:49:02 2010 +0300 > @@ -85,13 +85,23 @@ > #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) > #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) > > -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > + > +#ifdef CONFIG_XILINX_FPU > +#define stfr stfs > +#define lfr lfs > +#else > +#define stfr stfd > +#define lfr lfd > +#endif the stfr/lfr redirect is a little weird. Why not simply: > + > +#ifdef CONFIG_XILINX_FPU > +#define SAVE_FPR(n, base) stfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > +#else > +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > +#endif A comment here describing that only single precision works with the XILINX 405 FPU wouldn't go amiss either. > diff -r 9d9ac97e095d arch/powerpc/kernel/fpu.S > --- a/arch/powerpc/kernel/fpu.S Thu Feb 25 21:23:42 2010 +0300 > +++ b/arch/powerpc/kernel/fpu.S Thu Feb 25 21:49:02 2010 +0300 > @@ -57,6 +57,9 @@ > _GLOBAL(load_up_fpu) > mfmsr r5 > ori r5,r5,MSR_FP > +#ifdef CONFIG_XILINX_FPU > + oris r5,r5,MSR_VEC@h > +#endif So AltiVec is being enabled here, but double precision is not supported? What instructions are supported? Also, please stick with the same whitespace convention used in the lines above (tab indent instead of a space). Again, a comment would not go amiss. > #ifdef CONFIG_VSX > BEGIN_FTR_SECTION > oris r5,r5,MSR_VSX@h > @@ -85,6 +88,9 @@ > toreal(r5) > PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) > li r10,MSR_FP|MSR_FE0|MSR_FE1 > +#ifdef CONFIG_XILINX_FPU > + oris r10,r10,MSR_VEC@h > +#endif > andc r4,r4,r10 /* disable FP for previous task */ > PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) > 1: > @@ -94,6 +100,9 @@ > mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ > lwz r4,THREAD_FPEXC_MODE(r5) > ori r9,r9,MSR_FP /* enable FP for current */ > +#ifdef CONFIG_XILINX_FPU > + oris r9,r9,MSR_VEC@h > +#endif > or r9,r9,r4 > #else > ld r4,PACACURRENT(r13) > @@ -124,6 +133,9 @@ > _GLOBAL(giveup_fpu) > mfmsr r5 > ori r5,r5,MSR_FP > +#ifdef CONFIG_XILINX_FPU > + oris r5,r5,MSR_VEC@h > +#endif > #ifdef CONFIG_VSX > BEGIN_FTR_SECTION > oris r5,r5,MSR_VSX@h > @@ -145,6 +157,9 @@ > beq 1f > PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) > li r3,MSR_FP|MSR_FE0|MSR_FE1 > +#ifdef CONFIG_XILINX_FPU > + oris r3,r3,MSR_VEC@h > +#endif > #ifdef CONFIG_VSX > BEGIN_FTR_SECTION > oris r3,r3,MSR_VSX@h > diff -r 9d9ac97e095d arch/powerpc/kernel/head_40x.S > --- a/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:23:42 2010 +0300 > +++ b/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:49:02 2010 +0300 > @@ -420,7 +420,19 @@ > addi r3,r1,STACK_FRAME_OVERHEAD > EXC_XFER_STD(0x700, program_check_exception) > > +/* 0x0800 - FPU unavailable Exception */ > +#ifdef CONFIG_PPC_FPU > + START_EXCEPTION(0x0800, FloatingPointUnavailable) > + NORMAL_EXCEPTION_PROLOG > + beq 1f; \ > + bl load_up_fpu; /* if from user, just load it up */ \ > + b fast_exception_return; \ > +1: addi r3,r1,STACK_FRAME_OVERHEAD; \ > + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) > +#else > EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) > +#endif > + > EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) > EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) > EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) > @@ -432,7 +444,7 @@ > > EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) > EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) > - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) > + EXCEPTION(0x0F20, Trap_0F, unknown_exception, EXC_XFER_EE) Why? > > /* 0x1000 - Programmable Interval Timer (PIT) Exception */ > START_EXCEPTION(0x1000, Decrementer) > @@ -821,8 +833,10 @@ > * The PowerPC 4xx family of processors do not have an FPU, so this just > * returns. > */ > +#ifndef CONFIG_PPC_FPU > _ENTRY(giveup_fpu) > blr > +#endif > > /* This is where the main kernel code starts. > */ > diff -r 9d9ac97e095d arch/powerpc/platforms/Kconfig.cputype > --- a/arch/powerpc/platforms/Kconfig.cputype Thu Feb 25 21:23:42 2010 +0300 > +++ b/arch/powerpc/platforms/Kconfig.cputype Thu Feb 25 21:49:02 2010 +0300 > @@ -290,4 +290,9 @@ > config CHECK_CACHE_COHERENCY > bool > > +config XILINX_FPU > + bool "Xilinx softFPU" > + select PPC_FPU > + depends on 40x > + Should be more specific. Use something like XILINX_VIRTEX4_405_FPU (as opposed to Virtex II pro, or the 440 on the Virtex 5. Also, this looks to be very multiplatform unfriendly, so you'll need to make sure other 405 board support is not selectable when the Xilinx FPU is enabled. Cheers, g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support 2010-05-19 16:52 ` Grant Likely @ 2010-05-20 9:44 ` Sergey Temerkhanov 0 siblings, 0 replies; 4+ messages in thread From: Sergey Temerkhanov @ 2010-05-20 9:44 UTC (permalink / raw) To: Grant Likely; +Cc: linuxppc-dev On Wednesday 19 May 2010 20:52:01 Grant Likely wrote: > Hi Sergey. Comments below. > > > diff -r 9d9ac97e095d .config > > --- a/.config Thu Feb 25 21:23:42 2010 +0300 > > +++ b/.config Thu Feb 25 21:49:02 2010 +0300 > > .config changes should not appear in your patch file. > > > diff -r 9d9ac97e095d arch/powerpc/include/asm/ppc_asm.h > > --- a/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:23:42 2010 +0300 > > +++ b/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:49:02 2010 +0300 > > @@ -85,13 +85,23 @@ > > #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) > > #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) > > > > -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n) (base) > > + > > +#ifdef CONFIG_XILINX_FPU > > +#define stfr stfs > > +#define lfr lfs > > +#else > > +#define stfr stfd > > +#define lfr lfd > > +#endif > > the stfr/lfr redirect is a little weird. Why not simply: > > + > > +#ifdef CONFIG_XILINX_FPU > > +#define SAVE_FPR(n, base) stfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > > +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > > +#else > > +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > > +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) > > +#endif > > A comment here describing that only single precision works with the > XILINX 405 FPU wouldn't go amiss either. > Agreed. > > diff -r 9d9ac97e095d arch/powerpc/kernel/fpu.S > > --- a/arch/powerpc/kernel/fpu.S Thu Feb 25 21:23:42 2010 +0300 > > +++ b/arch/powerpc/kernel/fpu.S Thu Feb 25 21:49:02 2010 +0300 > > @@ -57,6 +57,9 @@ > > _GLOBAL(load_up_fpu) > > mfmsr r5 > > ori r5,r5,MSR_FP > > +#ifdef CONFIG_XILINX_FPU > > + oris r5,r5,MSR_VEC@h > > +#endif > > So AltiVec is being enabled here, but double precision is not > supported? That bit means 'APU enabled' for PowerPC 405 core. I've simply used existing #define. As Xilinx uses APU facilities for their FPU this bit must be set too. > What instructions are supported? Only single precision is supported for Virtex-4 FPU. Double presicion opcodes work as single precision there. > > Also, please stick with the same whitespace convention used in the > lines above (tab indent instead of a space). Again, a comment would > not go amiss. > > > #ifdef CONFIG_VSX > > BEGIN_FTR_SECTION > > oris r5,r5,MSR_VSX@h > > @@ -85,6 +88,9 @@ > > toreal(r5) > > PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) > > li r10,MSR_FP|MSR_FE0|MSR_FE1 > > +#ifdef CONFIG_XILINX_FPU > > + oris r10,r10,MSR_VEC@h > > +#endif > > andc r4,r4,r10 /* disable FP for previous task */ > > PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) > > 1: > > @@ -94,6 +100,9 @@ > > mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ > > lwz r4,THREAD_FPEXC_MODE(r5) > > ori r9,r9,MSR_FP /* enable FP for current */ > > +#ifdef CONFIG_XILINX_FPU > > + oris r9,r9,MSR_VEC@h > > +#endif > > or r9,r9,r4 > > #else > > ld r4,PACACURRENT(r13) > > @@ -124,6 +133,9 @@ > > _GLOBAL(giveup_fpu) > > mfmsr r5 > > ori r5,r5,MSR_FP > > +#ifdef CONFIG_XILINX_FPU > > + oris r5,r5,MSR_VEC@h > > +#endif > > #ifdef CONFIG_VSX > > BEGIN_FTR_SECTION > > oris r5,r5,MSR_VSX@h > > @@ -145,6 +157,9 @@ > > beq 1f > > PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) > > li r3,MSR_FP|MSR_FE0|MSR_FE1 > > +#ifdef CONFIG_XILINX_FPU > > + oris r3,r3,MSR_VEC@h > > +#endif > > #ifdef CONFIG_VSX > > BEGIN_FTR_SECTION > > oris r3,r3,MSR_VSX@h > > diff -r 9d9ac97e095d arch/powerpc/kernel/head_40x.S > > --- a/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:23:42 2010 +0300 > > +++ b/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:49:02 2010 +0300 > > @@ -420,7 +420,19 @@ > > addi r3,r1,STACK_FRAME_OVERHEAD > > EXC_XFER_STD(0x700, program_check_exception) > > > > +/* 0x0800 - FPU unavailable Exception */ > > +#ifdef CONFIG_PPC_FPU > > + START_EXCEPTION(0x0800, FloatingPointUnavailable) > > + NORMAL_EXCEPTION_PROLOG > > + beq 1f; \ > > + bl load_up_fpu; /* if from user, just load it up */ \ > > + b fast_exception_return; \ > > +1: addi r3,r1,STACK_FRAME_OVERHEAD; \ > > + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) > > +#else > > EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) > > +#endif > > + > > EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) > > EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) > > EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) > > @@ -432,7 +444,7 @@ > > > > EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) > > EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) > > - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) > > + EXCEPTION(0x0F20, Trap_0F, unknown_exception, EXC_XFER_EE) > > Why? Xilinx UG011 and IBM PowerPC 405 User guides define no 0xF00 exception but 0xF20 (APU unavailable). For 403 core there seems to be no APU support. > > > /* 0x1000 - Programmable Interval Timer (PIT) Exception */ > > START_EXCEPTION(0x1000, Decrementer) > > @@ -821,8 +833,10 @@ > > * The PowerPC 4xx family of processors do not have an FPU, so this just > > * returns. > > */ > > +#ifndef CONFIG_PPC_FPU > > _ENTRY(giveup_fpu) > > blr > > +#endif > > > > /* This is where the main kernel code starts. > > */ > > diff -r 9d9ac97e095d arch/powerpc/platforms/Kconfig.cputype > > --- a/arch/powerpc/platforms/Kconfig.cputype Thu Feb 25 21:23:42 2010 > > +0300 +++ b/arch/powerpc/platforms/Kconfig.cputype Thu Feb 25 21:49:02 > > 2010 +0300 @@ -290,4 +290,9 @@ > > config CHECK_CACHE_COHERENCY > > bool > > > > +config XILINX_FPU > > + bool "Xilinx softFPU" > > + select PPC_FPU > > + depends on 40x > > + > > Should be more specific. Use something like XILINX_VIRTEX4_405_FPU > (as opposed to Virtex II pro, or the 440 on the Virtex 5. > > Also, this looks to be very multiplatform unfriendly, so you'll need > to make sure other 405 board support is not selectable when the Xilinx > FPU is enabled. Agreed, it must depend on Virtex-4FX only. > > Cheers, > g. > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2010-05-20 9:44 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-03-19 15:47 [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support Sergey Temerkhanov 2010-03-19 15:49 ` Sergey Temerkhanov 2010-05-19 16:52 ` Grant Likely 2010-05-20 9:44 ` Sergey Temerkhanov
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