* How can I make the DDR momory storage bigger than 256M?
@ 2007-11-19 14:42 郭劲
2007-11-20 4:38 ` Liu Dave
0 siblings, 1 reply; 2+ messages in thread
From: 郭劲 @ 2007-11-19 14:42 UTC (permalink / raw)
To: linuxppc-embedded
Hi,friends,
I used the U-Boot 1.2.0 on MPC8360E board. My board work nomally with 256M DDR-1
Memory. If I change the DDR-1 up to 1GB, the U-Boot can visit the DDR address
range from 0x00000000 to 0x10000000, but it can not visit the address bigger than
0x10000000,I wat wondering why? Thanks.
Using the 1GB DDR-1, I can write the u-boot to my flash by CodeWarrior.
Follow is the information that when I test the DDR on u-boot, the start address is
0x1ff00000, the end address is 0x20000000;it was dead when visit the DDR.
U-Boot 1.2.0 (Nov 19 2007 - 20:55:34) MPC83XX
CPU: e300c1, MPC8360E, Rev: 20 at 528 MHz, CSB: 264 MHz
Board: Freescale MPC8360EMDS
I2C: ready
DRAM:
DIMM type:
SPD size: 128
EEPROM size: 256
Memory type: 7
Row addr: 13
Column addr: 11
# of rows: 2
Row density: 128
# of banks: 4
Data width: 64
Chip width: 8
Refresh rate: 82
CAS latencies: 18
Write latencies: 02
tRP: 60
tRCD: 60
cs0_bnds = 0x0000001f
cs0_config = 0x80000103
cs1_bnds = 0x0020003f
cs1_config = 0x80000103
DDR:bar=0x00000000
DDR:ar=0x8000001d
DDR: caslat SPD bit is 4
DDR:Module maximum data rate is: 400Mhz
DDR:Effective data rate is: 266Mhz
DDR:The MSB 1 of CAS Latency is: 4
DDR: effective data rate is 266 MHz
DDR: caslat SPD bit is 4, controller field is 0x5
DDR:timing_cfg_1=0x26252727
DDR:timing_cfg_2=0x00004841
DDR DIMM: data bus width is 64 bit without ECC
DDR:sdram_mode=0x00000032
DDR: sdram_mode2 = 0x00000000
DDR:sdram_interval=0x04060100
DDR:sdram_clk_cntl=0x02000000
DDRC ECC mode: OFF
DDR:sdram_cfg=0xc2008000
SDRAM on Local Bus: 64 MB
DDR RAM: 1024 MB
DDR test phase 1:
(dead)
^ permalink raw reply [flat|nested] 2+ messages in thread* RE: How can I make the DDR momory storage bigger than 256M?
2007-11-19 14:42 How can I make the DDR momory storage bigger than 256M? 郭劲
@ 2007-11-20 4:38 ` Liu Dave
0 siblings, 0 replies; 2+ messages in thread
From: Liu Dave @ 2007-11-20 4:38 UTC (permalink / raw)
To: 郭劲, linuxppc-embedded
Hello Guo,
Please post your question to u-boot maillist:
u-boot-users@lists.sourceforge.net=20
Please check if you have the correct BATs for 1GB memory.
1GB memory should need 4 BATs.
Regards,
Dave
> -----Original Message-----
> From:=20
> linuxppc-embedded-bounces+daveliu=3Dfreescale.com@ozlabs.org=20
> [mailto:linuxppc-embedded-bounces+daveliu=3Dfreescale.com@ozlabs
> .org] On Behalf Of =B9=F9=BE=A2
> Sent: 2007=C4=EA11=D4=C219=C8=D5 10:42 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: How can I make the DDR momory storage bigger than 256M?
>=20
> Hi,friends,
>=20
> I used the U-Boot 1.2.0 on MPC8360E board. My board work=20
> nomally with 256M DDR-1
> Memory. If I change the DDR-1 up to 1GB, the U-Boot can=20
> visit the DDR address
> range from 0x00000000 to 0x10000000, but it can not visit the=20
> address bigger than
> 0x10000000,I wat wondering why? Thanks.
>=20
> Using the 1GB DDR-1, I can write the u-boot to my flash by=20
> CodeWarrior.
>=20
> Follow is the information that when I test the DDR on u-boot,=20
> the start address is
> 0x1ff00000, the end address is 0x20000000;it was dead when=20
> visit the DDR.
>=20
>=20
>=20
>=20
>=20
>=20
> U-Boot 1.2.0 (Nov 19 2007 - 20:55:34) MPC83XX =20
> =20
> =20
> =20
> CPU: e300c1, MPC8360E, Rev: 20 at 528 MHz, CSB: 264 MHz =20
> =20
> Board: Freescale MPC8360EMDS =20
> =20
> I2C: ready =20
> =20
> DRAM: =20
> =20
> DIMM type: =20
> =20
> SPD size: 128 =20
> =20
> EEPROM size: 256 =20
> =20
> Memory type: 7 =20
> =20
> Row addr: 13 =20
> =20
> Column addr: 11 =20
> =20
> # of rows: 2 =20
> =20
> Row density: 128 =20
> =20
> # of banks: 4 =20
> =20
> Data width: 64 =20
> =20
> Chip width: 8 =20
> =20
> Refresh rate: 82 =20
> =20
> CAS latencies: 18 =20
> =20
> Write latencies: 02 =20
> =20
> tRP: 60 =20
> =20
> tRCD: 60 =20
> =20
> =20
> =20
> =20
> =20
> cs0_bnds =3D 0x0000001f =20
> =20
> cs0_config =3D 0x80000103 =20
> =20
> cs1_bnds =3D 0x0020003f =20
> =20
> cs1_config =3D 0x80000103 =20
> =20
> DDR:bar=3D0x00000000 =20
> =20
> DDR:ar=3D0x8000001d =20
> =20
> DDR: caslat SPD bit is 4 =20
> =20
> DDR:Module maximum data rate is: 400Mhz =20
> =20
> DDR:Effective data rate is: 266Mhz =20
> =20
> DDR:The MSB 1 of CAS Latency is: 4 =20
> =20
> DDR: effective data rate is 266 MHz =20
> =20
> DDR: caslat SPD bit is 4, controller field is 0x5 =20
> =20
> DDR:timing_cfg_1=3D0x26252727 =20
> =20
> DDR:timing_cfg_2=3D0x00004841 =20
> =20
> =20
> =20
> DDR DIMM: data bus width is 64 bit without ECC =20
> =20
> DDR:sdram_mode=3D0x00000032 =20
> =20
> DDR: sdram_mode2 =3D 0x00000000 =20
> =20
> DDR:sdram_interval=3D0x04060100 =20
> =20
> DDR:sdram_clk_cntl=3D0x02000000 =20
> =20
> DDRC ECC mode: OFF =20
> =20
> DDR:sdram_cfg=3D0xc2008000 =20
> =20
> =20
> =20
> SDRAM on Local Bus: 64 MB =20
> =20
> DDR RAM: 1024 MB =20
> =20
> DDR test phase 1: =20
>=20
>=20
> (dead)
>=20
>=20
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>=20
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2007-11-19 14:42 How can I make the DDR momory storage bigger than 256M? 郭劲
2007-11-20 4:38 ` Liu Dave
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