[PATCH v2] cxl: Remove function write_timebase_ctrl_psl9() for PSL9

[PATCH v2] cxl: Remove function write_timebase_ctrl_psl9() for PSL9

[Vaibhav Jain]

For PSL9 the contents of PSL_TB_CTLSTAT register have changed in PSL9
and all of the register is now readonly. Hence we don't need an sl_ops
implementation for 'write_timebase_ctrl' for to populate this register
for PSL9.

Hence this patch removes function write_timebase_ctrl_psl9() and its
references from the code.

Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
---
Change-log:
v2 -> Updated the patch description to accurately reflect changes
      between PSL9 and PSL8. (Fred)
---
 drivers/misc/cxl/pci.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index c983f23cc2ed..9bc30c20b66b 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -572,12 +572,6 @@ static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_
 /* For the PSL this is a multiple for 0 < n <= 7: */
 #define PSL_2048_250MHZ_CYCLES 1
 
-static void write_timebase_ctrl_psl9(struct cxl *adapter)
-{
-	cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
-		     TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
-}
-
 static void write_timebase_ctrl_psl8(struct cxl *adapter)
 {
 	cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
@@ -639,7 +633,8 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
 	 * Setup PSL Timebase Control and Status register
 	 * with the recommended Timebase Sync Count value
 	 */
-	adapter->native->sl_ops->write_timebase_ctrl(adapter);
+	if (adapter->native->sl_ops->write_timebase_ctrl)
+		adapter->native->sl_ops->write_timebase_ctrl(adapter);
 
 	/* Enable PSL Timebase */
 	cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
@@ -1805,7 +1800,6 @@ static const struct cxl_service_layer_ops psl9_ops = {
 	.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
 	.err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
 	.debugfs_stop_trace = cxl_stop_trace_psl9,
-	.write_timebase_ctrl = write_timebase_ctrl_psl9,
 	.timebase_read = timebase_read_psl9,
 	.capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
 	.needs_reset_before_disable = true,
-- 
2.14.3

Re: [PATCH v2] cxl: Remove function write_timebase_ctrl_psl9() for PSL9

[Andrew Donnellan]

Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>

On 15/02/18 17:19, Vaibhav Jain wrote:
> For PSL9 the contents of PSL_TB_CTLSTAT register have changed in PSL9
> and all of the register is now readonly. Hence we don't need an sl_ops
> implementation for 'write_timebase_ctrl' for to populate this register
> for PSL9.
> 
> Hence this patch removes function write_timebase_ctrl_psl9() and its
> references from the code.
> 
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---
> Change-log:
> v2 -> Updated the patch description to accurately reflect changes
>        between PSL9 and PSL8. (Fred)
> ---
>   drivers/misc/cxl/pci.c | 10 ++--------
>   1 file changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index c983f23cc2ed..9bc30c20b66b 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -572,12 +572,6 @@ static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_
>   /* For the PSL this is a multiple for 0 < n <= 7: */
>   #define PSL_2048_250MHZ_CYCLES 1
> 
> -static void write_timebase_ctrl_psl9(struct cxl *adapter)
> -{
> -	cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
> -		     TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
> -}
> -
>   static void write_timebase_ctrl_psl8(struct cxl *adapter)
>   {
>   	cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
> @@ -639,7 +633,8 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
>   	 * Setup PSL Timebase Control and Status register
>   	 * with the recommended Timebase Sync Count value
>   	 */
> -	adapter->native->sl_ops->write_timebase_ctrl(adapter);
> +	if (adapter->native->sl_ops->write_timebase_ctrl)
> +		adapter->native->sl_ops->write_timebase_ctrl(adapter);
> 
>   	/* Enable PSL Timebase */
>   	cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
> @@ -1805,7 +1800,6 @@ static const struct cxl_service_layer_ops psl9_ops = {
>   	.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
>   	.err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
>   	.debugfs_stop_trace = cxl_stop_trace_psl9,
> -	.write_timebase_ctrl = write_timebase_ctrl_psl9,
>   	.timebase_read = timebase_read_psl9,
>   	.capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
>   	.needs_reset_before_disable = true,
> 

-- 
Andrew Donnellan              OzLabs, ADL Canberra
andrew.donnellan@au1.ibm.com  IBM Australia Limited

Re: [PATCH v2] cxl: Remove function write_timebase_ctrl_psl9() for PSL9

[Frederic Barrat]

Le 15/02/2018 à 07:19, Vaibhav Jain a écrit :
> For PSL9 the contents of PSL_TB_CTLSTAT register have changed in PSL9
> and all of the register is now readonly. Hence we don't need an sl_ops
> implementation for 'write_timebase_ctrl' for to populate this register
> for PSL9.
> 
> Hence this patch removes function write_timebase_ctrl_psl9() and its
> references from the code.
> 
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---

Thanks!

Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>


> Change-log:
> v2 -> Updated the patch description to accurately reflect changes
>        between PSL9 and PSL8. (Fred)
> ---
>   drivers/misc/cxl/pci.c | 10 ++--------
>   1 file changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index c983f23cc2ed..9bc30c20b66b 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -572,12 +572,6 @@ static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_
>   /* For the PSL this is a multiple for 0 < n <= 7: */
>   #define PSL_2048_250MHZ_CYCLES 1
> 
> -static void write_timebase_ctrl_psl9(struct cxl *adapter)
> -{
> -	cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
> -		     TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
> -}
> -
>   static void write_timebase_ctrl_psl8(struct cxl *adapter)
>   {
>   	cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
> @@ -639,7 +633,8 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
>   	 * Setup PSL Timebase Control and Status register
>   	 * with the recommended Timebase Sync Count value
>   	 */
> -	adapter->native->sl_ops->write_timebase_ctrl(adapter);
> +	if (adapter->native->sl_ops->write_timebase_ctrl)
> +		adapter->native->sl_ops->write_timebase_ctrl(adapter);
> 
>   	/* Enable PSL Timebase */
>   	cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
> @@ -1805,7 +1800,6 @@ static const struct cxl_service_layer_ops psl9_ops = {
>   	.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
>   	.err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
>   	.debugfs_stop_trace = cxl_stop_trace_psl9,
> -	.write_timebase_ctrl = write_timebase_ctrl_psl9,
>   	.timebase_read = timebase_read_psl9,
>   	.capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
>   	.needs_reset_before_disable = true,
> 

Re: [v2] cxl: Remove function write_timebase_ctrl_psl9() for PSL9

[Michael Ellerman]

On Thu, 2018-02-15 at 06:19:36 UTC, Vaibhav Jain wrote:
> For PSL9 the contents of PSL_TB_CTLSTAT register have changed in PSL9
> and all of the register is now readonly. Hence we don't need an sl_ops
> implementation for 'write_timebase_ctrl' for to populate this register
> for PSL9.
> 
> Hence this patch removes function write_timebase_ctrl_psl9() and its
> references from the code.
> 
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/02b63b420223db3e33e19cc0aaf346

cheers