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From: Cao Qingtao <harrytaurus2002@yahoo.com.cn>
To: michael@ellerman.id.au
Cc: qingtao.cao@windriver.com, linuxppc-dev@ozlabs.org
Subject: How CPC925 HyperTransport Host Interface mapps NMI request?
Date: Tue, 7 Apr 2009 18:48:47 +0800 (CST)	[thread overview]
Message-ID: <729154.37897.qm@web15608.mail.cnb.yahoo.com> (raw)

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Hi Michael,
 
Thanks for commenting on my CPC925 EDAC driver. I am on vacation this week and will integrate your suggestions next week.
 
I am also thinking of adding EDAC NMI support for the AMD8131 chip, which is a HyperTransport Tunnel device that hosts two PCI-X bridges. If enabled, each PCI-X bridge could generate NMI interrupt request package upstream, with vector identifier = 0. 
 
The CPC925 user mannual, p111, says that "This interrupt vector is used to set a corresponding interrupt latch", does this mean MPIC interrupt pin#0 would be latched on receiving NMI request package?
 
However, the pin#0 has been specified for Internal I2C master interrupt, so it would have to share hwirq #0 with NMI interrupt?
 
Thanks a lot!
 
Best regards,
 
Harry


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                 reply	other threads:[~2009-04-07 10:55 UTC|newest]

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