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From: Michael Ellerman <mpe@ellerman.id.au>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Matt Brown <matthew.brown.dev@gmail.com>,
	"linuxppc-dev\@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	"linux-ide\@vger.kernel.org" <linux-ide@vger.kernel.org>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	"adi-buildroot-devel\@lists.sourceforge.net"
	<adi-buildroot-devel@lists.sourceforge.net>,
	Linux MMC List <linux-mmc@vger.kernel.org>,
	MTD Maling List <linux-mtd@lists.infradead.org>,
	"linux-arm-kernel\@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	linux-spi <linux-spi@vger.kernel.org>,
	"linux-serial\@vger.kernel.org" <linux-serial@vger.kernel.org>,
	USB list <linux-usb@vger.kernel.org>
Subject: Re: [PATCH] powerpc/asm/cacheflush: Cleanup cacheflush function params
Date: Thu, 20 Jul 2017 23:01:56 +1000	[thread overview]
Message-ID: <87h8y7gt2z.fsf@concordia.ellerman.id.au> (raw)
In-Reply-To: <CAMuHMdXU-R8kBs_xp7XDK0pnC5fakpghchuEPD8jtEcHLmgyHg@mail.gmail.com>

Geert Uytterhoeven <geert@linux-m68k.org> writes:

> On Thu, Jul 20, 2017 at 1:43 PM, Michael Ellerman <mpe@ellerman.id.au> wrote:
>> Matt Brown <matthew.brown.dev@gmail.com> writes:
>>> The cacheflush prototypes currently use start and stop values and each
>>> call requires typecasting the address to an unsigned long.
>>> This patch changes the cacheflush prototypes to follow the x86 style of
>>> using a base and size values, with base being a void pointer.
>>>
>>> All callers of the cacheflush functions, including drivers, have been
>>> modified to conform to the new prototypes.
>>>
>>> The 64 bit cacheflush functions which were implemented in assembly code
>>> (flush_dcache_range, flush_inval_dcache_range) have been translated into
>>> C for readability and coherence.
>
>>> --- a/arch/powerpc/include/asm/cacheflush.h
>>> +++ b/arch/powerpc/include/asm/cacheflush.h
>>> @@ -51,13 +51,13 @@ static inline void __flush_dcache_icache_phys(unsigned long physaddr)
>>>   * Write any modified data cache blocks out to memory and invalidate them.
>>>   * Does not invalidate the corresponding instruction cache blocks.
>>>   */
>>> -static inline void flush_dcache_range(unsigned long start, unsigned long stop)
>>> +static inline void flush_dcache_range(void *start, unsigned long size)
>>>  {
>>> -     void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
>>> -     unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
>>> +     void *addr = (void *)((u32)start & ~(L1_CACHE_BYTES - 1));
>>
>> unsigned long would be nicer than u32.
>
> Indeed. That would make this work on ppc64, too.
> After which ppc64 has an identical copy (u64 = unsigned long on ppc64) below?

That was Matt's homework to notice that ;)

cheers

  reply	other threads:[~2017-07-20 13:01 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-20  6:28 [PATCH] powerpc/asm/cacheflush: Cleanup cacheflush function params Matt Brown
2017-07-20  7:00 ` Geert Uytterhoeven
2017-07-20 11:43 ` Michael Ellerman
2017-07-20 12:07   ` Geert Uytterhoeven
2017-07-20 13:01     ` Michael Ellerman [this message]
2017-07-24  4:31       ` Matt Brown
2017-07-31  8:41 ` Christophe LEROY

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