* Re: help requesting for mounting eldk tools on AMCC PPC 405EP Taihu kit
From: Wolfgang Denk @ 2006-06-18 20:49 UTC (permalink / raw)
To: jagadeesh kalisetty; +Cc: linuxppc-dev
In-Reply-To: <20060618152344.13300.qmail@webmail18.rediffmail.com>
In message <20060618152344.13300.qmail@webmail18.rediffmail.com> you wrote:
>
> but the kernel is failed to mount on /dev/nfs as below please can you
> provide necessary steps to fix the problem.
...
> => setenv setboot setenv bootargs root=/dev/pts nfsroot=192.168.2.18:/opt/eldk/ppc_4xx ip=192.168.1.62:::::eth0:off
What's /dev/pts? You mentioned you intended to use NFS as root file
system. Then I'd expect to see /dev/nfs here. [Note: 'n' != 'p']
> bootcmd=run setboot;bootm 0xfc000000 0xfc300000
You mentioned you intended to use NFS as root file system. Then why
do you use a ramdisk?
> ## Loading RAMDisk Image at fc300000 ...
> Image Name: Taihu Ramdisk
> Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
> Data Size: 15447973 Bytes = 14.7 MB
Your ramdisk image is much bigger than the default maximum kernel
ramdisk size (4 MB). But you don't pass any ramdisk size information
with your boot arguments:
> Kernel command line: root=/dev/pts nfsroot=192.168.2.18:/opt/eldk/ppc_4xx ip=192.168.1.62:::::eth0:off
If you really want to use this ramdisk, you should set the root
device and the ramdisk size appropriately.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
NOTE: The Most Fundamental Particles in This Product Are Held
Together by a "Gluing" Force About Which Little is Currently Known
and Whose Adhesive Power Can Therefore Not Be Permanently Guaranteed.
^ permalink raw reply
* help requesting for mounting eldk tools on AMCC PPC 405EP Taihu kit
From: jagadeesh kalisetty @ 2006-06-18 15:23 UTC (permalink / raw)
To: linuxppc-dev
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hi
I am using Taihu Amcc PPC 405EP kit it already contains the U-boot, Linux kernel image, and ramdisk image. I connected the kit using c-kermit on fedora core 4 and installed eldk tools and added it (/opt/eldk/ppc_4xx) to NFS sharing.
While booting on kit I passed kernel arguments as
setenv bootargs root=/dev/nfs nfsroot=192.168.2.18:/opt/eldk/ppc_4xx ip=192.168.1.62:::::eth0:off
but the kernel is failed to mount on /dev/nfs as below please can you provide necessary steps to fix the problem.
I am waiting for your response.
……….after U-booting on kit…..
Hit any key to stop autoboot: 0
=> setenv setboot setenv bootargs root=/dev/pts nfsroot=192.168.2.18:/opt/eldk/ppc_4xx ip=192.168.1.62:::::eth0:off
=> printenv
bootdelay=5
baudrate=9600
filesize=ebb7e5
ethaddr=50:00:00:00:25:00
eth1addr=50:00:00:00:25:01
loads_echo=1
ethact=ppc_4xx_eth0
bootcmd=run setboot;bootm 0xfc000000 0xfc300000
kozio=bootm 0xffe00000
RT_eth0_ip=192.168.1.62
RT_eth0_ip2=:::::eth0:off
stdin=serial
stdout=serial
stderr=serial
ver=U-Boot 1.1.4 (Jan 19 2006 - 14:16:53)
setboot=setenv bootargs root=/dev/pts nfsroot=192.168.2.18:/opt/eldk/ppc_4xx ip=192.168.1.62:::::eth0:off
Environment size: 450/16379 bytes
=> boot
## Booting image at fc000000 ...
Image Name: Linux-2.6.13
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1121647 Bytes = 1.1 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
## Loading RAMDisk Image at fc300000 ...
Image Name: Taihu Ramdisk
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 15447973 Bytes = 14.7 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Loading Ramdisk to 070e3000, end 07f9e7a5 ... OK
Linux version 2.6.13 (root@linux_box) (gcc version 4.0.0 (DENX ELDK 4.0 4.0.0)) #50 Tue Feb 7 09:07:24 CST 2006
AMCC PowerPC 405EP Taihu Platform
Built 1 zonelists
Kernel command line: root=/dev/pts nfsroot=192.168.2.18:/opt/eldk/ppc_4xx ip=192.168.1.62:::::eth0:off
PID hash table entries: 1024 (order: 10, 16384 bytes)
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 112128k available (1916k kernel code, 452k data, 96k init, 0k highmem)
Mount-cache hash table entries: 512
checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 15085k freed
NET: Registered protocol family 16
PCI: Probing PCI hardware
JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc.
Initializing Cryptographic API
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
ttyS0 at MMIO 0x0 (irq = 1) is a 16550A
ttyS1 at MMIO 0x0 (irq = 0) is a 16550A
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
mal0: Initialized, 4 tx channels, 2 rx channels
emac: IBM EMAC Ethernet driver, version 2.0
Maintained by Benjamin Herrenschmidt <benh@kernel.crashing.org>
eth0: IBM emac, MAC 50:00:00:00:25:00
eth0: Found Generic MII PHY (0x14)
eth1: IBM emac, MAC 50:00:00:00:25:01
eth1: Found Generic MII PHY (0x10)
e100: Intel(R) PRO/100 Network Driver, 3.4.8-k2-NAPI
e100: Copyright(c) 1999-2005 Intel Corporation
taihu: bootflash mapping: 200000 at ffe00000
AMCC Taihu Boot Flash: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
Creating 3 MTD partitions on "AMCC Taihu Boot Flash":
0x00000000-0x001a0000 : "kozio diags"
0x001a0000-0x001c0000 : "u-boot env"
0x001c0000-0x00200000 : "u-boot"
taihu: appflash mapping: 2000000 at fc000000
AMCC Taihu Application Flash: Found 2 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
AMCC Taihu Application Flash: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
Creating 3 MTD partitions on "AMCC Taihu Application Flash":
0x00000000-0x00300000 : "kernel"
0x00300000-0x01d00000 : "initrd"
0x01d00000-0x02000000 : "jffs2"
Yenta: CardBus bridge found at 0000:00:07.0 [0000:0000]
Yenta: Enabling burst memory read transactions
Yenta: Using CSCINT to route CSC interrupts to PCI
Yenta: Routing CardBus interrupts to PCI
Yenta TI: socket 0000:00:07.0, mfunc 0x00001000, devctl 0x66
Yenta TI: socket 0000:00:07.0 probing PCI interrupt failed, trying to fix
Yenta TI: socket 0000:00:07.0 falling back to parallel PCI interrupts
Yenta TI: socket 0000:00:07.0 parallel PCI interrupts ok
eth0: Link is Up
eth0: Speed: 100, Full duplex.
Yenta: ISA IRQ mask 0x0000, PCI irq 26
Socket status: 30000087
pcmcia: parent PCI bridge I/O window: 0x0 - 0xffff
pcmcia: parent PCI bridge Memory window: 0x80000000 - 0xbfffffff
zero gadget: Gadget Zero, version: St Patrick's Day 2004
zero gadget: using pd12_udc, OUT ep1out-bulk IN ep2in-bulk
pd12_udc: registered gadget driver 'zero'
i2c /dev entries driver
IBM IIC driver v2.1
ibm-iic0: using standard (100 kHz) mode
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP reno registered
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
NET: Registered protocol family 15
eth0: Link is Up
eth0: Speed: 100, Full duplex.
IP-Config: Guessing netmask 255.255.255.0
IP-Config: Complete:
device=eth0, addr=192.168.1.62, mask=255.255.255.0, gw=255.255.255.255,
host=192.168.1.62, domain=, nis-domain=(none),
bootserver=255.255.255.255, rootserver=255.255.255.255, rootpath=
RAMDISK: Compressed image found at block 0
RAMDISK: incomplete write (-28 != 32768) 4194304
VFS: Cannot open root device "pts" or unknown-block(0,0)
Please append a correct "root=" boot option
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
<0>Rebooting in 180 seconds..<NULL>
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^ permalink raw reply
* Re: [PATCH 7/9 v3] Add 8641 Register space and IRQ definitions.
From: Kumar Gala @ 2006-06-18 14:31 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjet-0004PA-J1@jdl.com>
On Jun 17, 2006, at 5:52 PM, Jon Loeliger wrote:
[snip]
> diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/
> mpc86xx.h
> new file mode 100644
> index 0000000..d0a6718
> --- /dev/null
> +++ b/include/asm-powerpc/mpc86xx.h
> @@ -0,0 +1,47 @@
> +/*
> + * MPC86xx definitions
> + *
> + * Author: Jeff Brown
> + *
> + * Copyright 2004 Freescale Semiconductor, Inc
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#ifdef __KERNEL__
> +#ifndef __ASM_POWERPC_MPC86xx_H__
> +#define __ASM_POWERPC_MPC86xx_H__
> +
> +#include <linux/config.h>
> +#include <asm/mmu.h>
> +
> +#ifdef CONFIG_PPC_86xx
> +
> +#ifdef CONFIG_MPC8641_HPCN
> +#include <platforms/86xx/mpc8641_hpcn.h>
> +#endif
>
Is this really needed, its a hold over from arch/ppc. I dont think
you need anything defined in mpc8641_hpcn.h. This always created
funny dependancies and would be nice to get ride of.
> +
> +#define _IO_BASE isa_io_base
> +#define _ISA_MEM_BASE isa_mem_base
> +#ifdef CONFIG_PCI
> +#define PCI_DRAM_OFFSET pci_dram_offset
> +#else
> +#define PCI_DRAM_OFFSET 0
> +#endif
> +
> +#define CPU0_BOOT_RELEASE 0x01000000
> +#define CPU1_BOOT_RELEASE 0x02000000
> +#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
> +#define MCM_PORT_CONFIG_OFFSET 0x1010
> +
> +/* Offset from CCSRBAR */
> +#define MPC86xx_OPENPIC_OFFSET (0x40000)
> +#define MPC86xx_MCM_OFFSET (0x00000)
> +#define MPC86xx_MCM_SIZE (0x02000)
> +
> +#endif /* CONFIG_PPC_86xx */
> +#endif /* __ASM_POWERPC_MPC86xx_H__ */
> +#endif /* __KERNEL__ */
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 5/9 v3] Add the MPC8641 HPCN platform files.
From: Kumar Gala @ 2006-06-18 14:28 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjen-0004Oz-Hz@jdl.com>
On Jun 17, 2006, at 5:52 PM, Jon Loeliger wrote:
> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
> Signed-off-by: Jon Loeliger <jdl@freescale.com>
>
> ---
>
> arch/powerpc/platforms/86xx/mpc8641_hpcn.h | 54 +++++
> arch/powerpc/platforms/86xx/mpc86xx.h | 28 ++
> arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 326 +++++++++++++++++
> +++++++++++
> arch/powerpc/platforms/86xx/mpc86xx_smp.c | 117 ++++++++++
> 4 files changed, 525 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/
> powerpc/platforms/86xx/mpc8641_hpcn.h
> new file mode 100644
> index 0000000..5042253
> --- /dev/null
> +++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
> @@ -0,0 +1,54 @@
> +/*
> + * MPC8641 HPCN board definitions
> + *
> + * Copyright 2006 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + *
> + * Author: Xianghua Xiao <x.xiao@freescale.com>
> + */
> +
> +#ifndef __MPC8641_HPCN_H__
> +#define __MPC8641_HPCN_H__
> +
> +#include <linux/config.h>
> +#include <linux/init.h>
> +
> +/* PCI interrupt controller */
> +#define PIRQA 3
> +#define PIRQB 4
> +#define PIRQC 5
> +#define PIRQD 6
> +#define PIRQ7 7
> +#define PIRQE 9
> +#define PIRQF 10
> +#define PIRQG 11
> +#define PIRQH 12
> +
> +/* PCI-Express memory map */
> +#define MPC86XX_PCIE_LOWER_IO 0x00000000
> +#define MPC86XX_PCIE_UPPER_IO 0x00ffffff
> +
> +#define MPC86XX_PCIE_LOWER_MEM 0x80000000
> +#define MPC86XX_PCIE_UPPER_MEM 0x9fffffff
> +
> +#define MPC86XX_PCIE_IO_BASE 0xe2000000
> +#define MPC86XX_PCIE_MEM_OFFSET 0x00000000
> +
> +#define MPC86XX_PCIE_IO_SIZE 0x01000000
> +
> +#define PCIE1_CFG_ADDR_OFFSET (0x8000)
> +#define PCIE1_CFG_DATA_OFFSET (0x8004)
> +
> +#define PCIE2_CFG_ADDR_OFFSET (0x9000)
> +#define PCIE2_CFG_DATA_OFFSET (0x9004)
> +
> +#define MPC86xx_PCIE_OFFSET PCIE1_CFG_ADDR_OFFSET
> +#define MPC86xx_PCIE_SIZE (0x1000)
> +
> +#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */
> +
> +#endif /* __MPC8641_HPCN_H__ */
> diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/
> platforms/86xx/mpc86xx.h
> new file mode 100644
> index 0000000..e3c9e4f
> --- /dev/null
> +++ b/arch/powerpc/platforms/86xx/mpc86xx.h
> @@ -0,0 +1,28 @@
> +/*
> + * Copyright 2006 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#ifndef __MPC86XX_H__
> +#define __MPC86XX_H__
> +
> +/*
> + * Declaration for the various functions exported by the
> + * mpc86xx_* files. Mostly for use by mpc86xx_setup().
> + */
> +
> +extern int __init add_bridge(struct device_node *dev);
> +
> +extern void __init setup_indirect_pcie(struct pci_controller *hose,
> + u32 cfg_addr, u32 cfg_data);
> +extern void __init setup_indirect_pcie_nomap(struct pci_controller
> *hose,
> + void __iomem *cfg_addr,
> + void __iomem *cfg_data);
> +
> +extern void __init mpc86xx_smp_init(void);
> +
> +#endif /* __MPC86XX_H__ */
> diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/
> powerpc/platforms/86xx/mpc86xx_hpcn.c
> new file mode 100644
> index 0000000..483c21d
> --- /dev/null
> +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
> @@ -0,0 +1,326 @@
> +/*
> + * MPC86xx HPCN board specific routines
> + *
> + * Recode: ZHANG WEI <wei.zhang@freescale.com>
> + * Initial author: Xianghua Xiao <x.xiao@freescale.com>
> + *
> + * Copyright 2006 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/delay.h>
> +#include <linux/seq_file.h>
> +#include <linux/root_dev.h>
> +
> +#include <asm/system.h>
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <asm/mpc86xx.h>
> +#include <asm/prom.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/udbg.h>
> +#include <asm/i8259.h>
> +
> +#include <asm/mpic.h>
> +
> +#include <sysdev/fsl_soc.h>
> +
> +#include "mpc86xx.h"
> +
> +#ifndef CONFIG_PCI
> +unsigned long isa_io_base = 0;
> +unsigned long isa_mem_base = 0;
> +unsigned long pci_dram_offset = 0;
> +#endif
> +
> +
> +/*
> + * Internal interrupts are all Level Sensitive, and Positive Polarity
> + */
> +
> +static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0:
> Reserved */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR
> DRAM */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCIE1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PCIE2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10:
> Reserved */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11:
> Reserved */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1
> Transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1
> Receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3
> transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3
> receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3
> error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1
> Receive/Transmit Error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2
> Transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2
> Receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4
> transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4
> receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4
> error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2
> Receive/Transmit Error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28:
> Performance Monitor */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO
> error/write-port unit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO
> outbound doorbell */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO
> inbound doorbell */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO
> outbound message unit 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO
> inbound message unit 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO
> outbound message unit 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO
> inbound message unit 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
> + 0x0, /* External 0: */
> + 0x0, /* External 1: */
> + 0x0, /* External 2: */
> + 0x0, /* External 3: */
> + 0x0, /* External 4: */
> + 0x0, /* External 5: */
> + 0x0, /* External 6: */
> + 0x0, /* External 7: */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis
> FPGA */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI
> 8259 INTR Cascade */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad
> ETH PHY */
> + 0x0, /* External 11: */
> + 0x0,
> + 0x0,
> + 0x0,
> + 0x0,
> +};
> +
> +
> +void __init
> +mpc86xx_hpcn_init_irq(void)
> +{
> + struct mpic *mpic1;
> + phys_addr_t openpic_paddr;
> +
> + /* Determine the Physical Address of the OpenPIC regs */
> + openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
> +
> + /* Alloc mpic structure and per isu has 16 INT entries. */
> + mpic1 = mpic_alloc(openpic_paddr,
> + MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
> + 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
> + mpc86xx_hpcn_openpic_initsenses,
> + sizeof(mpc86xx_hpcn_openpic_initsenses),
> + " MPIC ");
> + BUG_ON(mpic1 == NULL);
> +
> + /* 48 Internal Interrupts */
> + mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
> + mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
> + mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
> +
> + /* 16 External interrupts */
> + mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
> +
> + mpic_init(mpic1);
> +
> +#ifdef CONFIG_PCI
> + mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
> + i8259_init(0, I8259_OFFSET);
> +#endif
> +}
> +
> +
> +
> +#ifdef CONFIG_PCI
> +/*
> + * interrupt routing
> + */
> +
> +int
> +mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned
> char pin)
> +{
> + static char pci_irq_table[][4] = {
> + /*
> + * PCI IDSEL/INTPIN->INTLINE
> + * A B C D
> + */
> + {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */
> + {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */
> + {0, 0, 0, 0}, /* IDSEL 19 */
> + {0, 0, 0, 0}, /* IDSEL 20 */
> + {0, 0, 0, 0}, /* IDSEL 21 */
> + {0, 0, 0, 0}, /* IDSEL 22 */
> + {0, 0, 0, 0}, /* IDSEL 23 */
> + {0, 0, 0, 0}, /* IDSEL 24 */
> + {0, 0, 0, 0}, /* IDSEL 25 */
> + {PIRQD, PIRQA, PIRQB, PIRQC}, /* IDSEL 26 -- PCI Bridge*/
> + {PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */
> + {PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */
> + {PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */
> + {PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/
> + {PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */
> + };
> +
> + const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
> + return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
> +}
> +
> +
> +int
> +mpc86xx_exclude_device(u_char bus, u_char devfn)
> +{
> +#if !defined(CONFIG_PCI)
> + if (bus == 0 && PCI_SLOT(devfn) == 0)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +#endif
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
any reason not to put this in pci.c its generic enough. Also, loose
the #if, its pointless ;)
> +#endif /* CONFIG_PCI */
> +
> +
> +static void __init
> +mpc86xx_hpcn_setup_arch(void)
> +{
> + struct device_node *np;
> +
> + if (ppc_md.progress)
> + ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
> +
> + np = of_find_node_by_type(NULL, "cpu");
> + if (np != 0) {
> + unsigned int *fp;
> +
> + fp = (int *)get_property(np, "clock-frequency", NULL);
> + if (fp != 0)
> + loops_per_jiffy = *fp / HZ;
> + else
> + loops_per_jiffy = 50000000 / HZ;
> + of_node_put(np);
> + }
> +
> +#ifdef CONFIG_PCI
> + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
> + add_bridge(np);
> +
> + ppc_md.pci_swizzle = common_swizzle;
> + ppc_md.pci_map_irq = mpc86xx_map_irq;
> + ppc_md.pci_exclude_device = mpc86xx_exclude_device;
> +#endif
> +
> + printk("MPC86xx HPCN board from Freescale Semiconductor\n");
> +
> +#ifdef CONFIG_ROOT_NFS
> + ROOT_DEV = Root_NFS;
> +#else
> + ROOT_DEV = Root_HDA1;
> +#endif
> +
> +#ifdef CONFIG_SMP
> + mpc86xx_smp_init();
> +#endif
> +}
> +
> +
> +void
> +mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
> +{
> + struct device_node *root;
> + uint memsize = total_memory;
> + const char *model = "";
> + uint svid = mfspr(SPRN_SVR);
> +
> + seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
> +
> + root = of_find_node_by_path("/");
> + if (root)
> + model = get_property(root, "model", NULL);
> + seq_printf(m, "Machine\t\t: %s\n", model);
> + of_node_put(root);
> +
> + seq_printf(m, "SVR\t\t: 0x%x\n", svid);
> + seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
> +}
> +
> +
> +/*
> + * Called very early, device-tree isn't unflattened
> + */
> +static int __init mpc86xx_hpcn_probe(void)
> +{
> + unsigned long root = of_get_flat_dt_root();
> +
> + if (of_flat_dt_is_compatible(root, "mpc86xx"))
> + return 1; /* Looks good */
> +
> + return 0;
> +}
You should make this probe actually check model or something more
specific than mpc86xx. I didn't do this on 85xx or 83xx since we had
pre-existing .dts that didn't setup model in a consistent way.
> +
> +
> +void
> +mpc86xx_restart(char *cmd)
> +{
> + void __iomem *rstcr;
> +
> + rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
> +
> + local_irq_disable();
> +
> + /* Assert reset request to Reset Control Register */
> + out_be32(rstcr, 0x2);
> +
> + /* not reached */
> +}
> +
> +
> +long __init
> +mpc86xx_time_init(void)
> +{
> + unsigned int temp;
> +
> + /* Set the time base to zero */
> + mtspr(SPRN_TBWL, 0);
> + mtspr(SPRN_TBWU, 0);
> +
> + temp = mfspr(SPRN_HID0);
> + temp |= HID0_TBEN;
> + mtspr(SPRN_HID0, temp);
> + asm volatile("isync");
> +
> + return 0;
> +}
> +
> +
> +define_machine(mpc86xx_hpcn) {
> + .name = "MPC86xx HPCN",
> + .probe = mpc86xx_hpcn_probe,
> + .setup_arch = mpc86xx_hpcn_setup_arch,
> + .init_IRQ = mpc86xx_hpcn_init_irq,
> + .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
> + .get_irq = mpic_get_irq,
> + .restart = mpc86xx_restart,
> + .time_init = mpc86xx_time_init,
> + .calibrate_decr = generic_calibrate_decr,
> + .progress = udbg_progress,
> +};
> diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/
> powerpc/platforms/86xx/mpc86xx_smp.c
> new file mode 100644
> index 0000000..944ec4b
> --- /dev/null
> +++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
a nit, but any reason to not call this just smp.c?
> @@ -0,0 +1,117 @@
> +/*
> + * Author: Xianghua Xiao <x.xiao@freescale.com>
> + * Zhang Wei <wei.zhang@freescale.com>
> + *
> + * Copyright 2006 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/delay.h>
> +
> +#include <asm/pgtable.h>
> +#include <asm/page.h>
> +#include <asm/pci-bridge.h>
> +#include <asm-powerpc/mpic.h>
> +#include <asm/mpc86xx.h>
> +#include <asm/cacheflush.h>
> +
> +#include <sysdev/fsl_soc.h>
> +
> +#include "mpc86xx.h"
> +
> +extern void __secondary_start_mpc86xx(void);
> +extern unsigned long __secondary_hold_acknowledge;
> +
> +
> +static void __init
> +smp_86xx_release_core(int nr)
> +{
> + void *mcm_vaddr;
> + unsigned long vaddr, pcr;
> +
> + if (nr < 0 || nr >= NR_CPUS)
> + return;
> +
> + /*
> + * Startup Core #nr.
> + */
> + mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
> + MPC86xx_MCM_SIZE);
> + vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;
> + pcr = in_be32((volatile unsigned *)vaddr);
> + pcr |= 1 << (nr + 24);
> + out_be32((volatile unsigned *)vaddr, pcr);
> +}
> +
> +
> +static void __init
> +smp_86xx_kick_cpu(int nr)
> +{
> + unsigned int save_vector;
> + unsigned long target, flags;
> + int n = 0;
> + volatile unsigned int *vector
> + = (volatile unsigned int *)(KERNELBASE + 0x100);
> +
> + if (nr < 0 || nr >= NR_CPUS)
> + return;
> +
> + pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr);
> +
> + local_irq_save(flags);
> + local_irq_disable();
> +
> + /* Save reset vector */
> + save_vector = *vector;
> +
> + /* Setup fake reset vector to call __secondary_start_mpc86xx. */
> + target = (unsigned long) __secondary_start_mpc86xx;
> + create_branch((unsigned long)vector, target, BRANCH_SET_LINK);
> +
> + /* Kick that CPU */
> + smp_86xx_release_core(nr);
> +
> + /* Wait a bit for the CPU to take the exception. */
> + while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000))
> + mdelay(1);
> +
> + /* Restore the exception vector */
> + *vector = save_vector;
> + flush_icache_range((unsigned long) vector, (unsigned long) vector
> + 4);
> +
> + local_irq_restore(flags);
> +
> + pr_debug("wait CPU #%d for %d msecs.\n", nr, n);
> +}
> +
> +
> +static void __init
> +smp_86xx_setup_cpu(int cpu_nr)
> +{
> + mpic_setup_this_cpu();
> +}
> +
> +
> +struct smp_ops_t smp_86xx_ops = {
> + .message_pass = smp_mpic_message_pass,
> + .probe = smp_mpic_probe,
> + .kick_cpu = smp_86xx_kick_cpu,
> + .setup_cpu = smp_86xx_setup_cpu,
> + .take_timebase = smp_generic_take_timebase,
> + .give_timebase = smp_generic_give_timebase,
> +};
> +
> +
> +void __init
> +mpc86xx_smp_init(void)
> +{
> + smp_ops = &smp_86xx_ops;
> +}
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 0/9 v3] Introduce the MPC8641 HPCN platform
From: Kumar Gala @ 2006-06-18 14:23 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjec-0004Oc-Ou@jdl.com>
On Jun 17, 2006, at 5:52 PM, Jon Loeliger wrote:
>
> This is the third posting of a series of patches
> that introduces the MPC8641 HPCN platform. This
> version corrects all of the suggestions from Kumar,
> and shows an ACK from Jeff Garzik for the netdev
> related parts. It also addresses all of the problems
> that Ben brought up related to multi-platform issues.
> It does not use IRQ settings from the device tree yet;
> that will come as a follow on patch when Ben's IRQ
> rewrite is more solid.
>
> Please consider this for addition into the 2.6.18 queue.
General question, have you run these patches through sparse?
>
> Collectively:
>
> Signed-off-by: Jon Loeliger <jdl@freescale.com>
> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
> Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com>
> Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
> Acked-by: Jeff Garzik <jeff@garzik.org>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 3/9 v3] Add 8641 CPU table entry.
From: Kumar Gala @ 2006-06-18 14:16 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjei-0004Oq-Ot@jdl.com>
On Jun 17, 2006, at 5:52 PM, Jon Loeliger wrote:
> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
> Signed-off-by: Jon Loeliger <jdl@freescale.com>
>
> ---
>
> arch/powerpc/kernel/cputable.c | 12 ++++++++++++
> 1 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/
> cputable.c
> index abf7d42..1c11488 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -722,6 +722,18 @@ #if CLASSIC_PPC
> .oprofile_type = PPC_OPROFILE_G4,
> .platform = "ppc7450",
> },
> + { /* 8641 */
> + .pvr_mask = 0xffffffff,
> + .pvr_value = 0x80040010,
> + .cpu_name = "8641",
> + .cpu_features = CPU_FTRS_7447A,
> + .cpu_user_features = COMMON_USER |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> + .icache_bsize = 32,
> + .dcache_bsize = 32,
> + .num_pmcs = 6,
> + .cpu_setup = __setup_cpu_745x
> + },
> +
is this really needed? Based on the PVR you'd match the 7448 entry
which seems identical (beyond the name, which is irrelevant)? [also
your missing oprofile & platform info]
> { /* 82xx (8240, 8245, 8260 are all 603e cores) */
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00810000,
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 1/9 v3] Add the mpc8641 hpcn Kconfig and Makefiles.
From: Kumar Gala @ 2006-06-18 14:13 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjed-0004Of-T3@jdl.com>
On Jun 17, 2006, at 5:52 PM, Jon Loeliger wrote:
> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
> Signed-off-by: Jon Loeliger <jdl@freescale.com>
>
> ---
>
> arch/powerpc/Kconfig | 15 ++++++++++++--
> arch/powerpc/platforms/Makefile | 1 +
> arch/powerpc/platforms/86xx/Kconfig | 36 +++++++++++++++++++++++
> +++++++++++
> arch/powerpc/platforms/86xx/Makefile | 10 +++++++++
> 4 files changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 4ef2478..65f4cd1 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -141,6 +141,15 @@ config PPC_85xx
> select FSL_SOC
> select 85xx
>
> +config PPC_86xx
> + bool "Freescale 86xx"
> + select 6xx
> + select FSL_SOC
> + select PPC_FPU
> + select ALTIVEC
> + help
> + The Freescale E600 SoCs have 74xx cores.
> +
> config 40x
> bool "AMCC 40x"
>
> @@ -549,6 +558,7 @@ source arch/powerpc/platforms/embedded6x
> source arch/powerpc/platforms/4xx/Kconfig
> source arch/powerpc/platforms/83xx/Kconfig
> source arch/powerpc/platforms/85xx/Kconfig
> +source arch/powerpc/platforms/86xx/Kconfig
> source arch/powerpc/platforms/8xx/Kconfig
> source arch/powerpc/platforms/cell/Kconfig
>
> @@ -780,6 +790,7 @@ config GENERIC_ISA_DMA
>
> config PPC_I8259
> bool
> + default y if MPC8641_HPCN
> default n
Can you change this into a select under the config MPC8641_HPCN menu?
>
> config PPC_INDIRECT_PCI
> @@ -802,8 +813,8 @@ config MCA
> bool
>
> config PCI
> - bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx ||
> PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
> - default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !
> PPC_85xx
> + bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx ||
> PPC_86xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
> + default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !
> PPC_85xx && !PPC_86xx
> default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
> default PCI_QSPAN if !4xx && !CPM2 && 8xx
> help
> diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/
> platforms/Makefile
> index c4f6b0d..2928636 100644
> --- a/arch/powerpc/platforms/Makefile
> +++ b/arch/powerpc/platforms/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_PPC_CHRP) += chrp/
> obj-$(CONFIG_4xx) += 4xx/
> obj-$(CONFIG_PPC_83xx) += 83xx/
> obj-$(CONFIG_PPC_85xx) += 85xx/
> +obj-$(CONFIG_PPC_86xx) += 86xx/
> obj-$(CONFIG_PPC_PSERIES) += pseries/
> obj-$(CONFIG_PPC_ISERIES) += iseries/
> obj-$(CONFIG_PPC_MAPLE) += maple/
> diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/
> platforms/86xx/Kconfig
> new file mode 100644
> index 0000000..3a87863
> --- /dev/null
> +++ b/arch/powerpc/platforms/86xx/Kconfig
> @@ -0,0 +1,36 @@
> +menu "Platform Support"
> + depends on PPC_86xx
> +
> +choice
> + prompt "Machine Type"
> + default MPC8641_HPCN
> +
> +config MPC8641_HPCN
> + bool "Freescale MPC8641 HPCN"
> + help
> + This option enables support for the MPC8641 HPCN board.
> +
> +endchoice
> +
> +
> +config MPC8641
> + bool
> + select PPC_INDIRECT_PCI
> + select PPC_UDBG_16550
> + default y if MPC8641_HPCN
> +
> +config MPIC
> + bool
> + default y
> +
> +config PPC_INDIRECT_PCI_BE
> + bool
> + depends on PPC_86xx
> + default y
> +
> +config PPC_STD_MMU
> + bool
> + depends on PPC_86xx
> + default y
this seems redundant, having 6xx should get this for you already.
> +
> +endmenu
> diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/
> platforms/86xx/Makefile
> new file mode 100644
> index 0000000..7be796c
> --- /dev/null
> +++ b/arch/powerpc/platforms/86xx/Makefile
> @@ -0,0 +1,10 @@
> +#
> +# Makefile for the PowerPC 86xx linux kernel.
> +#
> +
> +
> +ifeq ($(CONFIG_PPC_86xx),y)
> +obj-$(CONFIG_SMP) += mpc86xx_smp.o
> +endif
isn't the ifeq redundant, we would only parse this Makefile if we
were CONFIG_PPC_86xx
> +obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
> +obj-$(CONFIG_PCI) += pci.o mpc86xx_pcie.o
> _______________________________________________
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> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* CPU_FREQ any platforms?
From: Guennadi Liakhovetski @ 2006-06-18 12:36 UTC (permalink / raw)
To: linuxppc-dev
Hi
Was surprised to see that CPU_FREQ is only supported for (some) Apple's
ppc systems. Why that? Are there principal problems or just nobody has
done so far?
Thanks
Guennadi
---
Guennadi Liakhovetski
^ permalink raw reply
* Re: [PATCH 5/9 v3] Add the MPC8641 HPCN platform files.
From: Benjamin Herrenschmidt @ 2006-06-18 3:14 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjen-0004Oz-Hz@jdl.com>
> +/*
> + * Internal interrupts are all Level Sensitive, and Positive Polarity
> + */
> +
> +static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCIE1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PCIE2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
> + 0x0, /* External 0: */
> + 0x0, /* External 1: */
> + 0x0, /* External 2: */
> + 0x0, /* External 3: */
> + 0x0, /* External 4: */
> + 0x0, /* External 5: */
> + 0x0, /* External 6: */
> + 0x0, /* External 7: */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */
> + 0x0, /* External 11: */
> + 0x0,
> + 0x0,
> + 0x0,
> + 0x0,
> +};
So what I suggest you do with the above, rather than having this big
array in the kernel, is to have a property in the interrupt controller
node, let's call it "default-senses", which contains a cell for every
interrupt source with the default sense value.
The interrupt mapping code that I'm working on will allow individual
interrupts to carry their sense value through the device-tree, but it's
useful to have some sane defaults, either because you don't have a
device-tree entry for a given interrupt (oops, happens ...) or
because... you don't have my new code yet :)
I'm not too fan of the big table in the kernel however. I'd rather have
it in the device-tree.
I'm not forcing you here, do as you prefer, but if you decide to go
toward the "default-senses" property in the DT, then I think we should
add a couple of sections to my proposed patch to the
booting-without-of.txt file about interrupt that describes a set of
optional properties for interrupt controllers, and describe that there.
I'm toying with creating a "generic" create_interrupt_controller()
function in fact that takes a device-node and would instanciate known
interrupt controller types (i8259, OpenPIC, for now, maybe more later)
entire based on device-tree properties (big-endian, maybe that one for
default sense codes, etc...).
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 5/9 v3] Add the MPC8641 HPCN platform files.
From: Benjamin Herrenschmidt @ 2006-06-18 3:07 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjen-0004Oz-Hz@jdl.com>
> struct smp_ops_t smp_86xx_ops = {
> + .message_pass = smp_mpic_message_pass,
> + .probe = smp_mpic_probe,
> + .kick_cpu = smp_86xx_kick_cpu,
> + .setup_cpu = smp_86xx_setup_cpu,
> + .take_timebase = smp_generic_take_timebase,
> + .give_timebase = smp_generic_give_timebase,
> +};
You don't have any way to freeze the timebase ? (No GPIO controlling
TBEN ?) It's pretty nasty to rely on software sync, especially if it's
supposed to be an example design ...
Ben.
^ permalink raw reply
* Re: [PATCH 4/9 v3] Add starting of secondary 86xx CPUs.
From: Benjamin Herrenschmidt @ 2006-06-18 3:05 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Frjem-0004Ou-2S@jdl.com>
> + .globl __secondary_start_mpc86xx
> +__secondary_start_mpc86xx:
> + mfspr r3, SPRN_PIR
> + stw r3, __secondary_hold_acknowledge@l(0)
> + mr r24, r3 /* cpu # */
> + b __secondary_start
The above looks generic enough... why not call it
__secondary_start_PIR ? :) Might be useful for other platforms I
reckon...
> .globl __secondary_start_pmac_0
> __secondary_start_pmac_0:
> /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
> @@ -1088,7 +1095,12 @@ load_up_mmu:
> LOAD_BAT(1,r3,r4,r5)
> LOAD_BAT(2,r3,r4,r5)
> LOAD_BAT(3,r3,r4,r5)
> -
> +BEGIN_FTR_SECTION
> + LOAD_BAT(4,r3,r4,r5)
> + LOAD_BAT(5,r3,r4,r5)
> + LOAD_BAT(6,r3,r4,r5)
> + LOAD_BAT(7,r3,r4,r5)
> +END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
> blr
Looks good.
^ permalink raw reply
* [RFC] Interrupt mapping documentation
From: Benjamin Herrenschmidt @ 2006-06-18 2:45 UTC (permalink / raw)
To: linuxppc-dev list
Hi !
I'm almost finished with a set of patches overhauling the interrupt
management of the powerpc kernel to allow proper and mostly hack-less
remapping of interrupt numbers, proper walking of the interrupt tree in
all cases, and lift the requirement of having all PCI devices have
matching device nodes in order to resolve their interrupts.
Along with this work for which I'll post patches in a couple of days,
I've started updating the documentation booting-without-of.txt. Here's a
draft diff against 2.6.17, please comment asap:
--- linux-2.6/Documentation/powerpc/booting-without-of.txt 2006-04-19 15:04:29.000000000 +1000
+++ booting-without-of.txt 2006-06-18 12:42:49.000000000 +1000
@@ -50,10 +50,15 @@
structure
- Added chapter VI
+ June 18, 2006: Rev 0.6
+ - Define the interrupt tree properties and
+ requirements
+ - Initial PCI requirements vs. interrupts
+ - Remove linux,platform as the kernel no
+ longer uses them.
+
ToDo:
- - Add some definitions of interrupt tree (simple/complex)
- - Add some definitions for pci host bridges
- Add some common address format examples
- Add definitions for standard properties and "compatible"
names for cells that are not already defined by the existing
@@ -523,6 +528,10 @@
explained in chapter IV which defines precisely the required nodes and
properties and their content.
+Note that in most cases, you will need at least an interrupt
+controller somewhere in that tree, and possibly one or more PCI host
+bridges if you have PCI, PCI-X, PCI Express or HyperTransport
+devices.
3) Device tree "structure" block
@@ -731,9 +740,9 @@
for example, if you have 2 board models with a similar layout,
that typically get driven by the same platform code in the
kernel, you would use a different "model" property but put a
- value in "compatible". The kernel doesn't directly use that
- value (see /chosen/linux,platform for how the kernel choses a
- platform type) but it is generally useful.
+ value in "compatible". Your board support code will use any
+ combination of those properties to uniquely identify your board
+ and decide to "attach" to it.
The root node is also generally where you add additional properties
specific to your board like the serial number if any, that sort of
@@ -844,8 +853,11 @@
Required properties:
- - linux,platform : This is your platform number as assigned by the
- architecture maintainers
+ - (OBSOLETE) linux,platform : This is your platform number as assigned by the
+ architecture maintainers. This properly has been obsoleted. As
+ of 2.6.17, the kernel board support code has a probe() function
+ that can access the flat device-tree to decide wether to attach
+ or not. The platform numbers are gone.
Recommended properties:
@@ -884,13 +896,13 @@
- device_type : Should be "soc"
- ranges : Should be defined as specified in 1) to describe the
translation of SOC addresses for memory mapped SOC registers.
- - bus-frequency: Contains the bus frequency for the SOC node.
- Typically, the value of this field is filled in by the boot
- loader.
Recommended properties:
+ - bus-frequency: Contains the bus frequency for the SOC node.
+ Typically, the value of this field is filled in by the boot
+ loader.
- reg : This property defines the address and size of the
memory-mapped registers that are used for the SOC node itself.
It does not include the child device registers - these will be
@@ -931,6 +943,26 @@
}
+ g) interrupt controller
+
+ At least one interrupt controller shall be present somewhere in the
+ device-tree. It can be anywhere, it doesn't have to be a dedicated
+ node (could be the /soc node) though it's generally separate. See
+ chapter VII for a description of interrupt mapping and associated
+ properties.
+
+ h) PCI (and PCI-X,PCI-E and HyperTransport) host bridge(s)
+
+ The kernel requires host bridges to be present in the device-tree as
+ "anchors" for the PCI subsystem. The kernel doesn't require nodes
+ for the individual PCI devices, however, before 2.6.18, the standard
+ powerpc PCI code is unable to resolve interrupt mapping unless those
+ are present. As of 2.6.18, the requirement for interrupt mapping has
+ been lifted so that only host bridges (and PCI2PCI bridges that don't
+ follow standard interrupt swizzling) need to have nodes in order to
+ provide appropriate interrupt maps. This is discussed in more
+ details in chapter VII along with the rest of the interrupt mapping.
+
IV - "dtc", the device tree compiler
====================================
@@ -1119,6 +1151,11 @@
2) Specifying interrupt information for SOC devices
---------------------------------------------------
+[NOTE: This section if historical and will be removed. Complete
+interrupt mapping is described now in Chapter VII which is a superset
+of what is described here. What is described here is still valid
+though, it's just superceeded.]
+
Each device that is part of an SOC and which generates interrupts
should have the following properties:
@@ -1149,6 +1186,11 @@
2 = high to low edge sensitive type enabled
3 = low to high edge sensitive type enabled
+[NOTE: In addition, the interrupt controller (pointed to by the
+interrupt-parent property) _MUST_ have a #interrupt-cells indicating
+the number of cells used to represent an interrupt. If following the
+above recommendation of 2 cells, then this property shall have a value
+of 2]
3) Representing devices without a current OF specification
@@ -1263,11 +1305,12 @@
Example :
- pic@40000 {
+ interrupt-controller@40000 {
linux,phandle = <40000>;
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
+ #interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
@@ -1445,6 +1488,314 @@
More devices will be defined as this spec matures.
+VII - Interrupt mapping
+=======================
+
+Interrupt mapping shall follow the document "Open Firmware,
+Recommended Practice: Interrupt Mapping". In addition, it is described
+in simpler words below.
+
+The interrupts representation in the device-tree form one or several
+trees rooted at the interrupt-controllers. (The interrupt controllers
+themselves can have an interrupt connected to another controller,
+that's the typical case of cascaded controllers, though I
+intentionally disconnect the 2 trees).
+
+For each interrupt controller in the system, the device-tree shall
+contain an interrupt-controller node. This doesn't have to be a
+dedicated node. A device node can also act as an interrupt
+controller. For example, some processors might want to have the /soc
+node also be the interrupt controller.
+
+Devices that can emit interrupts shall have an "interrupts" property
+containing interrupt specifiers. The format for these is specific to a
+given interrupt controller or interrupt nexus (see below).
+
+Some busses might want to define an "interrupt nexus". This is
+essentially a format conversion between child devices interrupt
+specifiers ("interrupts" properties) and parent interrupt controller
+defined interrupt specifiers. A typical example of this is PCI bridges
+who convert PCI devices interrupt specifiers representing their
+interrupts as a PCI interrupt line (INT#A...D) to interrupt sepcifiers
+in the format of the parent controller (generally a source number and
+a sense value). PCI is described in more details as an example later.
+
+Thus, a given device "interrupts" property is interpreted based on the
+interrupt "parent" of that device which can either be an interrupt
+controller or a nexus. The interrupt "parent" of a given device is, by
+default, the parent node in the tree, unless the device contains an
+explicit "interrupt-parent" property (defined below). In addition, the
+linux kernel will walk up the tree until it finds either a nexus or an
+interrupt controller, jumping up one level when no interrupt-parent is
+to be found or jumping to that node when one is found. Thus, a single
+interrupt-parent property can be used in a /soc node to represent the
+interrupt parent of all child nodes for example.
+
+
+1) Interrupt controllers
+------------------------
+
+An interrupt controller is identified by the presence of an empty
+"interrupt-controller" property in the node. It must also have those
+two required properties:
+
+ - linux,phandle : The normally optional phandle is required for an
+ interrupt controller node as that node will have to be
+ referrenced by phandle by other nodes (childs and nexus).
+ - #interrupt-cells : This property contains one cell indicating
+ the size of the child interrupt specifiers (number of
+ cells). For example, both ISA and OpenPIC standard specifiers
+ are 2 cells long (interrupt source number and trigger type) thus
+ the interrupt-controller node for these shall contain a
+ #interrupt-cells property with the value <2>.
+
+In addition, it needs that optional property if there is ever a nexus
+pointing to that controller:
+
+ - #address-cells : This is generally the value 0 for an interrupt
+ controller, the reason why this property is needed is described
+ in the documentation of an interrupt nexus.
+
+The format of the interrupt specifier is specific to a given interrupt
+controller. Open Firmware (and thus this document) defines the format
+for OpenPIC and ISA controllers. Both of them define a 2 cells
+specifier comprised of the interrupt source number followed by the
+trigger type (also called sense and polarity). The trigger types for
+OpenPIC and ISA are different however:
+
+ - Devices connected to openPIC-compatible controllers should encode
+ sense and polarity as follows:
+
+ 0 = high to low edge sensitive type enabled
+ 1 = active low level sensitive type enabled
+
+ In addition, common practice defines the following (which is
+ often supported only for OpenPIC interrupt 0, aka cascade):
+
+ 2 = low to high edge sensitive type enabled
+
+ For completeness (and to allow for extensions by vendors), we also
+ define the following:
+
+ 3 = active high level sensitive type enabled
+
+ - ISA PIC interrupt controllers should adhere to the ISA PIC
+ encodings listed below:
+
+ 0 = active low level sensitive type enabled
+ 1 = active high level sensitive type enabled
+ 2 = high to low edge sensitive type enabled
+ 3 = low to high edge sensitive type enabled
+
+Note: The interrupt source numbers are local to the interrupt
+controller. They don't necessarily match the linux interrupt numbers
+that will be used as interrupt numbers can be virtually offset or
+remapped by the kernel to accomodate several controller interrupt
+spaces in the single linux linear interrupt space. The device-tree
+shall only contain "hardware" source numbers, a given specifier
+containing a source number local to it's interrupt controller (or nexus).
+
+2) Devices
+----------
+
+A device that can emit interrupts is defined to have an "interrupts"
+property that contain one or several interrupt specifiers in the
+format defined by the interrupt parent (controller or nexus) of that
+device. In addition, it can have an optional:
+
+ - interrupt-parent: This property contains a phandle which points
+ to the interrupt controller or nexus that acts as the parent for
+ this node (and thus defines the format of the interrupt
+ specifiers in the "interrupts" property and contains the
+ #interrupt-cells for it). In absence of this property, the
+ device-tree parent is the default interrupt parent for the
+ device. If this parent still doesn't contain a #interrupt-cells
+ property, the linux kernel will continue walking up the tree
+ until it finds one (or an interrupt-parent).
+
+3) Nexus
+--------
+
+An interrupt "nexus" doesn't necessarily represent a physical device
+in the system. It's a node (can be any type of node but is typically
+the bus parent of a given bus type) that contain properties to remap
+the interrupt specifiers of child devices into the format of interrupt
+specifiers of the parent interrupt controller. An interrupt nexus is
+defined by the presence of an "interrupt-map" property.
+
+A typical example is PCI. PCI host and PCI-PCI bridges shall have
+interrupt nexus that convert between the "interrupts" properties of
+PCI devices, which are defined by the PCI bindings to contain a value
+representing the interrupt line used by that device
+(1=INT#A...4=INT#D), to the actual interrupt source line of the parent
+controller where those lines are connected to. In a sense, the
+interrupt nexus represents the wiring of PCI INT# lines to the parent
+controller sources.
+
+Interrupt nexus aren't mandatory for devices that are explicitely
+represented in the device-tree. If a node is in the tree, it can have
+an interrupt-parent pointing directly to the interrupt controller or
+be on a bus that has a common interrupt-parent (like ISA) and in which
+case device "interrupts" properties directly contain an interrupt
+specifier in the format defined by the parent interrupt controller.
+
+However interrupt nexus are useful for busses like PCI which provide
+slots that can be probed and do not require the presence of matching
+device nodes for every devices. It allows a PCI host bridge for
+example to provide the complete mapping of all interrupt lines of all
+slots without having to actually create nodes for those child devices
+or, if they are created anyway, without having to fill them with fully
+resolved interrupt specifiers and interrupt-parent pointers.
+
+
+There are 3 required properties in an interrupt nexus:
+
+ - #interrupt-cells : This property defines the number of cells of
+ interrupt specifiers for child nodes (exactly like for an
+ interrupt-controller).
+ - #address-cells : This property defines the number of cells of
+ an address in the child device "reg" property. it's not
+ specific to interrupt nexus. In fact, when interrupt nexus are
+ also bus bridges (like in the case of PCI bridges), they shall
+ already have such a property. The way this property is used
+ for interrupt resolution is described below
+ - #interrupt-map : This property defines the mapping between
+ child interrupt specifiers and parent interrupts. It's format
+ is fairly complex and described below.
+
+Along with an optional one:
+
+ - interrupt-map-mask : This property defines which part of an
+ interrupt "unit specifier" (see definition below) is taken into
+ account when comparing child devices with entries in the
+ interrupt-map.
+
+Ok, so now, here's how it works:
+
+We define the notion of an "interrupt unit specifier" as being the
+concatenation of a device unit address and its interrupt
+specififer. The unit address is the first cells (how many is defined
+by the #address-cells property) of the device "reg" property. The
+interrupt specifier is the content of the "interrupts" property for a
+given interrupt.
+
+For example, if a bus has a #address-cells of 1 and a #interrupt-cells
+of 2, a device with those properties:
+
+ reg = <0xabcd1234>;
+ interrupts = <0x00000001 0x00000000 0x00000002 0x00000001>
+
+(That is a device with 2 interrupt specifiers in its "interrupts"
+property) would thus have the following interrupt unit
+specifiers for its two interrupts:
+
+ 0xabcd1234 0x00000001 0x00000000
+and
+ 0xabcd1234 0x00000002 0x00000001
+
+Now the "interrupt-map" property is defined as containing a list of:
+
+ [ child interrupt unit specifier ] [ parent ] [ parent interrupt unit
+ specifier ]
+
+That is, a concatenated list of entries containing:
+
+ - an interrupt unit specifier for a child device
+ - a phandle pointing to the interrupt-parent for that interrupt
+ - an interrupt unit specifier in the parent space for that
+ interrupt
+
+In effect, when resolving an interrupt, the system "matches" the
+interrupt unit specifier of the device interrupt to resolve with an
+entry in that list and when a match is found, this specifier is
+"replaced" by the new specifier in the parent space and the resolving
+continues from the new parent.
+
+Note that since the parent interrupt unit specifier represents the new
+unit address and interrupt specifier to be used when resolving in the
+parent's space, their size follows the parent's #address-cells and
+#interrupt-cells. That's also why interrupt-controllers generally need
+a #address-cells property when there is an interrupt-nexus pointing to
+them. In absence of such a property, the kernel will assume a value of
+0. It's usual that the #address-cells of an interrupt controller is
+0. This indicates that the "unit address" part of the "interrupt unit
+specifier" doesn't exist in the interrupt controller space, thus
+turning the interrupt unit specifier into a simple interrupt
+specifier.
+
+Now, it's generally useful to not take into account an entire
+interrupt unit specifier for matching but only part of it (for
+example a PCI unit address contains the PCI bus,device and function
+along with various informations related to PCI BARs, though only the
+PCI device and the interrupt specifier are interesting to the
+interrupt mapping in most cases). That's what the interrupt-map-mask
+property is for. This property has the same size as an interrupt unit
+specifier in the child device space and contains a bitmask of the bits
+of the interrupt unit specifier that are relevant for comparison in
+the interrupt-map.
+
+Example of interrupt-map in the PCI binding section.
+
+
+4) PCI bindings
+---------------
+
+The PCI bindings to open firmware defines a specific format for the
+"interrupts" property of PCI devies and thus that all PCI host and PCI to
+PCI bridges are interrupt nexus. This is not mandatory as per this
+spec. The kernel will be able to resolve interrupts for PCI devices
+that have device node, wether they contain an interrupt-parent
+property pointing directly to the interrupt controller (and thus their
+interrupts property is in the controller format) or wether they have a
+PCI defined interrupts property and use a nexus in the parent bridge.
+
+The format of a PCI device interrupt specifier as per the PCI-OF
+bindings is a single cell (thus PCI bridges contain a #interrupt-cells
+property with the value <1>) containing the interrupt line used by the
+device:
+
+ <1> = INT#A
+ <2> = INT#B
+ <3> = INT#C
+ <4> = INT#D
+
+It's generally obtained from the device/function config space
+interrupt pin register and define which of the 4 interrupt pins a
+given device function uses.
+
+However, if you decide to not provide device-nodes for some PCI
+devices (typically for slots, thus not having to probe those slots
+from the firmware), you shall provide an interrupt nexus in the parent
+bridge containing mappings for all the possible interrupt lines on
+those slots. If those are behind a PCI-PCI bridge, you have the choice
+of either providing a node (and a nexus) for the bridge, or not. If
+the bridge uses standard sizzling, the kernel will be able (from
+2.6.18 and later) to resolve interrupts provided that the host bridge
+contains a nexus with maps for all possible interrupt lines of the
+PCI-PCI bridge itself. If your PCI-PCI bridge doesn't use standard
+swizzling, then you are required to provide a device-node and a nexus
+for it in order to allow the kernel to resolve interrupt for child
+devices of that bridge.
+
+
+<... INSERT EXAMPLES ...>
+
+
+
+VIII - PCI, PCI-X, PCI-Express and HyperTransport busses
+========================================================
+
+The specification follows exactly the Open Firmware bindings to PCI
+with the exception that nodes for devices are optional provided enough
+interrupt mapping information is provided in the host bridges (see
+chapter VII).
+
+<... TODO ...> add more and define properties for PCI host bridges>
+
+<... TODO ...> add PCI examples
+
+
+
Appendix A - Sample SOC node for MPC8540
========================================
@@ -1539,11 +1890,12 @@
interrupt-parent = <40000>;
};
- pic@40000 {
+ interrupt-controller@40000 {
linux,phandle = <40000>;
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
+ #interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
^ permalink raw reply
* RE: Using bestcomm in an external module (MPC5200B to be exact)
From: SalQ @ 2006-06-18 1:26 UTC (permalink / raw)
To: bennett78; +Cc: linuxppc-embedded
In-Reply-To: <44944F9B.8060007@digis.net>
Thanks Frank, I actually have seen that, but it looks like an internal
module, not an external module... unless I'm missing something. I've tried
configuring a few drivers that used bestcomm as <M>, and once I used insmod
on them they complained about all of the bestcomm API functions as missing.
________________________________
From: linuxppc-embedded-bounces+salquint=gmail.com@ozlabs.org
[mailto:linuxppc-embedded-bounces+salquint=gmail.com@ozlabs.org] On Behalf
Of Frank Bennett
Sent: Saturday, June 17, 2006 11:53 AM
To: Trueskew
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Using bestcomm in an external module (MPC5200B to be exact)
Trueskew wrote:
I'm writing a driver for a TI codec attached to the MPC5200B PSC3
codec lines on a Lite5200b. It's an external module, and I'd like to use
Bestcomm with it. I've already tried a bunch of horrible things to get it
to work. I could say it's close, but by close I mean the FEC still runs, my
stuff doesn't.
1. Can the Bestcomm I/F be used by an external module, or is the
module required to be built in if built-in drivers use Bestcomm?
TasksInitAPI (no so bad) and TasksLoadImage (yeah, bad) aren't really
supposed to be called more than once from what I've read, and the kernel
loads them for ethernet and ATA (no disk in my system if that matters).
2. If it can be used by an external module, how would I do it? I've
tried compiling the source into my module and replicating the initialization
the kernel does in addition to my own stuff. It's not too bad, though I
don't get any interrupts yet.
The LTIB from Freescale includes AIC23 and AC97 drivers that use
Bestcomm. I built my kernel with them set as modules, and they had the same
unresolved problems that my driver has on insmod, so I'm pessimistic. If
someone could put me out of my misery one way or another, I'd appreciate it.
Might check out the driver posted by Bob Petersen:
http://ozlabs.org/pipermail/linuxppc-embedded/2005-September/020210.html
using DENX linuxppc_2_4_devel/arch/ppc/5xxx_io/ i2s.c, psc.c and Bestcomm/
Frank
Thanks.
Sal
________________________________
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Frank Bennett
President
Mathegraphics,LLC
613 Bentley Pl
Fort Collins,CO 80526
970-229-9269 (hm) 970-402-9269 (cell)
www.mathegraphics.com
bennett78@digis.net
^ permalink raw reply
* [PATCH 8/9 v3] Document I2C_MPC option for 86xx too.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev, khali
The same I2C driver found on 85xx, etc., can be used for 86xx too.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
drivers/i2c/busses/Kconfig | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d6d4494..fbeae82 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -252,12 +252,12 @@ config I2C_POWERMAC
will be called i2c-powermac.
config I2C_MPC
- tristate "MPC107/824x/85xx/52xx"
+ tristate "MPC107/824x/85xx/52xx/86xx"
depends on I2C && PPC32
help
If you say yes to this option, support will be included for the
built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and
- MPC85xx family processors. The driver may also work on 52xx
+ MPC85xx/MPC8641 family processors. The driver may also work on 52xx
family processors, though interrupts are known not to work.
This driver can also be built as a module. If so, the module
^ permalink raw reply related
* [PATCH 9/9 v3] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev, netdev, jeff
Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Jeff Garzik <jeff@garzik.org>
---
drivers/net/Kconfig | 6 +-
drivers/net/phy/Kconfig | 5 ++
drivers/net/phy/Makefile | 1
drivers/net/phy/vitesse.c | 112 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 121 insertions(+), 3 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index bdaaad8..c1c2758 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2179,11 +2179,11 @@ config SPIDER_NET
config GIANFAR
tristate "Gianfar Ethernet"
- depends on 85xx || 83xx
+ depends on 85xx || 83xx || PPC_86xx
select PHYLIB
help
- This driver supports the Gigabit TSEC on the MPC85xx
- family of chips, and the FEC on the 8540
+ This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
+ and MPC86xx family of chips, and the FEC on the 8540.
config GFAR_NAPI
bool "NAPI Support"
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index fa39b94..76e51b1 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -44,6 +44,11 @@ config CICADA_PHY
depends on PHYLIB
---help---
Currently supports the cis8204
+config VITESSE_PHY
+ tristate "Drivers for the Vitesse PHYs"
+ depends on PHYLIB
+ ---help---
+ Currently supports the vsc8244
endmenu
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index e4116a5..a8d066e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DAVICOM_PHY) += davicom.o
obj-$(CONFIG_CICADA_PHY) += cicada.o
obj-$(CONFIG_LXT_PHY) += lxt.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+obj-$(CONFIG_VITESSE_PHY) += vitesse.o
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
new file mode 100644
index 0000000..ffd215d
--- /dev/null
+++ b/drivers/net/phy/vitesse.c
@@ -0,0 +1,112 @@
+/*
+ * Driver for Vitesse PHYs
+ *
+ * Author: Kriston Carson
+ *
+ * Copyright (c) 2005 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+
+/* Vitesse Extended Control Register 1 */
+#define MII_VSC8244_EXT_CON1 0x17
+#define MII_VSC8244_EXTCON1_INIT 0x0000
+
+/* Vitesse Interrupt Mask Register */
+#define MII_VSC8244_IMASK 0x19
+#define MII_VSC8244_IMASK_IEN 0x8000
+#define MII_VSC8244_IMASK_SPEED 0x4000
+#define MII_VSC8244_IMASK_LINK 0x2000
+#define MII_VSC8244_IMASK_DUPLEX 0x1000
+#define MII_VSC8244_IMASK_MASK 0xf000
+
+/* Vitesse Interrupt Status Register */
+#define MII_VSC8244_ISTAT 0x1a
+#define MII_VSC8244_ISTAT_STATUS 0x8000
+#define MII_VSC8244_ISTAT_SPEED 0x4000
+#define MII_VSC8244_ISTAT_LINK 0x2000
+#define MII_VSC8244_ISTAT_DUPLEX 0x1000
+
+/* Vitesse Auxiliary Control/Status Register */
+#define MII_VSC8244_AUX_CONSTAT 0x1c
+#define MII_VSC8244_AUXCONSTAT_INIT 0x0004
+#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
+#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
+#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
+#define MII_VSC8244_AUXCONSTAT_100 0x0008
+
+MODULE_DESCRIPTION("Vitesse PHY driver");
+MODULE_AUTHOR("Kriston Carson");
+MODULE_LICENSE("GPL");
+
+static int vsc824x_config_init(struct phy_device *phydev)
+{
+ int err;
+
+ err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
+ MII_VSC8244_AUXCONSTAT_INIT);
+ if (err < 0)
+ return err;
+
+ err = phy_write(phydev, MII_VSC8244_EXT_CON1,
+ MII_VSC8244_EXTCON1_INIT);
+ return err;
+}
+
+static int vsc824x_ack_interrupt(struct phy_device *phydev)
+{
+ int err = phy_read(phydev, MII_VSC8244_ISTAT);
+
+ return (err < 0) ? err : 0;
+}
+
+static int vsc824x_config_intr(struct phy_device *phydev)
+{
+ int err;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+ err = phy_write(phydev, MII_VSC8244_IMASK,
+ MII_VSC8244_IMASK_MASK);
+ else
+ err = phy_write(phydev, MII_VSC8244_IMASK, 0);
+ return err;
+}
+
+/* Vitesse 824x */
+static struct phy_driver vsc8244_driver = {
+ .phy_id = 0x000fc6c2,
+ .name = "Vitesse VSC8244",
+ .phy_id_mask = 0x000fffc0,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init = &vsc824x_config_init,
+ .config_aneg = &genphy_config_aneg,
+ .read_status = &genphy_read_status,
+ .ack_interrupt = &vsc824x_ack_interrupt,
+ .config_intr = &vsc824x_config_intr,
+ .driver = { .owner = THIS_MODULE,},
+};
+
+static int __init vsc8244_init(void)
+{
+ return phy_driver_register(&vsc8244_driver);
+}
+
+static void __exit vsc8244_exit(void)
+{
+ phy_driver_unregister(&vsc8244_driver);
+}
+
+module_init(vsc8244_init);
+module_exit(vsc8244_exit);
^ permalink raw reply related
* [PATCH 7/9 v3] Add 8641 Register space and IRQ definitions.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
include/asm-powerpc/immap_86xx.h | 199 ++++++++++++++++++++++++++++++++++++++
include/asm-powerpc/irq.h | 86 ++++++++++++++++
include/asm-powerpc/mpc86xx.h | 47 +++++++++
3 files changed, 332 insertions(+), 0 deletions(-)
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
new file mode 100644
index 0000000..d905b66
--- /dev/null
+++ b/include/asm-powerpc/immap_86xx.h
@@ -0,0 +1,199 @@
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_IMMAP_86XX_H__
+#define __ASM_POWERPC_IMMAP_86XX_H__
+#ifdef __KERNEL__
+
+/* Eventually this should define all the IO block registers in 86xx */
+
+/* PCI Registers */
+typedef struct ccsr_pci {
+ uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
+ uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
+ uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
+ char res1[3060];
+ uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
+ uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
+ uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
+ char res2[4];
+ uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
+ char res3[12];
+ uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
+ uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
+ uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
+ char res4[4];
+ uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
+ char res5[12];
+ uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
+ uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
+ uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
+ char res6[4];
+ uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
+ char res7[12];
+ uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
+ uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
+ uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
+ char res8[4];
+ uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
+ char res9[12];
+ uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
+ uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
+ uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
+ char res10[4];
+ uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
+ char res11[268];
+ uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
+ char res12[4];
+ uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
+ uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
+ uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
+ char res13[12];
+ uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
+ char res14[4];
+ uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
+ uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
+ uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
+ char res15[12];
+ uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
+ char res16[4];
+ uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
+ char res17[4];
+ uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
+ char res18[12];
+ uint err_dr; /* 0x.e00 - PCI Error Detect Register */
+ uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
+ uint err_en; /* 0x.e08 - PCI Error Enable Register */
+ uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
+ uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
+ uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
+ uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
+ uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
+ uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
+ uint pci_timr; /* 0x.e24 - PCI Timer Register */
+ char res19[472];
+} ccsr_pci_t;
+
+/* PCI Express Registers */
+typedef struct ccsr_pex {
+ uint pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
+ uint pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
+ char res1[4];
+ uint pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
+ uint pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
+ char res2[12];
+ uint pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
+ uint pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
+ uint pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
+ uint pex_pmcr; /* 0x.02c - PCI Express power management command register */
+ char res3[3024];
+ uint pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
+ uint pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
+ char res4[8];
+ uint pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
+ char res5[12];
+ uint pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
+ uint pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
+ uint pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
+ char res6[4];
+ uint pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
+ char res7[12];
+ uint pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
+ uint pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
+ uint pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
+ char res8[4];
+ uint pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
+ char res9[12];
+ uint pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
+ uint pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
+ uint pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
+ char res10[4];
+ uint pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
+ char res11[12];
+ uint pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
+ uint pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
+ uint pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
+ char res12[4];
+ uint pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
+ char res13[12];
+ char res14[256];
+ uint pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
+ char res15[4];
+ uint pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
+ uint pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
+ uint pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
+ char res16[12];
+ uint pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
+ char res17[4];
+ uint pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
+ uint pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
+ uint pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
+ char res18[12];
+ uint pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
+ char res19[4];
+ uint pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
+ uint pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
+ uint pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
+ char res20[12];
+ uint pex_err_dr; /* 0x.e00 - PCI Express error detect register */
+ char res21[4];
+ uint pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
+ char res22[4];
+ uint pex_err_disr; /* 0x.e10 - PCI Express error disable register */
+ char res23[12];
+ uint pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
+ char res24[4];
+ uint pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
+ uint pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
+ uint pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
+ uint pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
+} ccsr_pex_t;
+
+/* Global Utility Registers */
+typedef struct ccsr_guts {
+ uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
+ uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
+ uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
+ uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
+ uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
+ char res1[12];
+ uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
+ char res2[12];
+ uint gpiocr; /* 0x.0030 - GPIO Control Register */
+ char res3[12];
+ uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
+ char res4[12];
+ uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
+ char res5[12];
+ uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
+ char res6[12];
+ uint devdisr; /* 0x.0070 - Device Disable Control */
+ char res7[12];
+ uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
+ char res8[12];
+ uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
+ char res9[12];
+ uint pvr; /* 0x.00a0 - Processor Version Register */
+ uint svr; /* 0x.00a4 - System Version Register */
+ char res10[3416];
+ uint clkocr; /* 0x.0e00 - Clock Out Select Register */
+ char res11[12];
+ uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
+ char res12[12];
+ uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
+ char res13[61916];
+} ccsr_guts_t;
+
+#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 7bc6d73..7a76209 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -348,6 +348,92 @@ #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ
#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
+#elif defined(CONFIG_PPC_86xx)
+#include <asm/mpc86xx.h>
+
+#define NR_EPIC_INTS 48
+#ifndef NR_8259_INTS
+#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
+#endif
+#define NUM_8259_INTERRUPTS NR_8259_INTS
+
+#ifndef I8259_OFFSET
+#define I8259_OFFSET 0
+#endif
+
+#define NR_IRQS 256
+
+/* Internal IRQs on MPC86xx OpenPIC */
+
+#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
+#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
+#endif
+
+/* The 48 internal sources */
+#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* no 10,11 */
+#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 25 */
+#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 29,30,31 */
+#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 35,36 */
+#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* The 12 external interrupt lines */
+#define MPC86xx_IRQ_EXT_BASE 48
+#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+
#else /* CONFIG_40x + CONFIG_8xx */
/*
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
new file mode 100644
index 0000000..d0a6718
--- /dev/null
+++ b/include/asm-powerpc/mpc86xx.h
@@ -0,0 +1,47 @@
+/*
+ * MPC86xx definitions
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_MPC86xx_H__
+#define __ASM_POWERPC_MPC86xx_H__
+
+#include <linux/config.h>
+#include <asm/mmu.h>
+
+#ifdef CONFIG_PPC_86xx
+
+#ifdef CONFIG_MPC8641_HPCN
+#include <platforms/86xx/mpc8641_hpcn.h>
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#define CPU0_BOOT_RELEASE 0x01000000
+#define CPU1_BOOT_RELEASE 0x02000000
+#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
+#define MCM_PORT_CONFIG_OFFSET 0x1010
+
+/* Offset from CCSRBAR */
+#define MPC86xx_OPENPIC_OFFSET (0x40000)
+#define MPC86xx_MCM_OFFSET (0x00000)
+#define MPC86xx_MCM_SIZE (0x02000)
+
+#endif /* CONFIG_PPC_86xx */
+#endif /* __ASM_POWERPC_MPC86xx_H__ */
+#endif /* __KERNEL__ */
^ permalink raw reply related
* [PATCH 6/9 v3] Add mpc8641hpcn PCI/PCI-Express platform files.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/platforms/86xx/mpc86xx_pcie.c | 173 +++++++++++++++
arch/powerpc/platforms/86xx/pci.c | 325 ++++++++++++++++++++++++++++
2 files changed, 498 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_pcie.c b/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
new file mode 100644
index 0000000..a2f4f73
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
@@ -0,0 +1,173 @@
+/*
+ * Support for indirect PCI bridges.
+ *
+ * Copyright (C) 1998 Gabriel Paubert.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * "Temporary" MPC8548 Errata file -
+ * The standard indirect_pci code should work with future silicon versions.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+
+#include "mpc86xx.h"
+
+#define PCI_CFG_OUT out_be32
+
+/* ERRATA PCI-Ex 14 PCIE Controller timeout */
+#define PCIE_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
+
+
+static int
+indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
+ int len, u32 *val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ volatile void __iomem *cfg_data;
+ u32 temp;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Possible artifact of CDCpp50937 needs further investigation */
+ if (devfn != 0x0 && bus->number == 0xff)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ PCIE_FIX;
+ if (bus->number == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000001 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ PCIE_FIX;
+ temp = in_le32(cfg_data);
+ switch (len) {
+ case 1:
+ *val = (temp >> (((offset & 3))*8)) & 0xff;
+ break;
+ case 2:
+ *val = (temp >> (((offset & 3))*8)) & 0xffff;
+ break;
+ default:
+ *val = temp;
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
+ int len, u32 val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ volatile void __iomem *cfg_data;
+ u32 temp;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Possible artifact of CDCpp50937 needs further investigation */
+ if (devfn != 0x0 && bus->number == 0xff)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ PCIE_FIX;
+ if (bus->number == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000001 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ switch (len) {
+ case 1:
+ PCIE_FIX;
+ temp = in_le32(cfg_data);
+ temp = (temp & ~(0xff << ((offset & 3) * 8))) |
+ (val << ((offset & 3) * 8));
+ PCIE_FIX;
+ out_le32(cfg_data, temp);
+ break;
+ case 2:
+ PCIE_FIX;
+ temp = in_le32(cfg_data);
+ temp = (temp & ~(0xffff << ((offset & 3) * 8)));
+ temp |= (val << ((offset & 3) * 8)) ;
+ PCIE_FIX;
+ out_le32(cfg_data, temp);
+ break;
+ default:
+ PCIE_FIX;
+ out_le32(cfg_data, val);
+ break;
+ }
+ PCIE_FIX;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops indirect_pcie_ops = {
+ indirect_read_config_pcie,
+ indirect_write_config_pcie
+};
+
+void __init
+setup_indirect_pcie_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
+ void __iomem * cfg_data)
+{
+ hose->cfg_addr = cfg_addr;
+ hose->cfg_data = cfg_data;
+ hose->ops = &indirect_pcie_ops;
+}
+
+void __init
+setup_indirect_pcie(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+{
+ unsigned long base = cfg_addr & PAGE_MASK;
+ void __iomem *mbase, *addr, *data;
+
+ mbase = ioremap(base, PAGE_SIZE);
+ addr = mbase + (cfg_addr & ~PAGE_MASK);
+ if ((cfg_data & PAGE_MASK) != base)
+ mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
+ data = mbase + (cfg_data & ~PAGE_MASK);
+ setup_indirect_pcie_nomap(hose, addr, data);
+}
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
new file mode 100644
index 0000000..5180df7
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -0,0 +1,325 @@
+/*
+ * MPC86XX pci setup code
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/serial.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/immap_86xx.h>
+#include <asm/pci-bridge.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+struct pcie_outbound_window_regs {
+ uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
+ uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
+ uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
+ char res1[4];
+ uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
+ char res2[12];
+};
+
+struct pcie_inbound_window_regs {
+ uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
+ char res1[4];
+ uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
+ uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
+ uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
+ char res2[12];
+};
+
+static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
+{
+ volatile struct ccsr_pex *pcie;
+ volatile struct pcie_outbound_window_regs *pcieow;
+ volatile struct pcie_inbound_window_regs *pcieiw;
+ int i = 0;
+
+ DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
+ rsrc->end - rsrc->start + 1);
+ pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+
+ /* Disable all windows (except pexowar0 since its ignored) */
+ pcie->pexowar1 = 0;
+ pcie->pexowar2 = 0;
+ pcie->pexowar3 = 0;
+ pcie->pexowar4 = 0;
+ pcie->pexiwar1 = 0;
+ pcie->pexiwar2 = 0;
+ pcie->pexiwar3 = 0;
+
+ pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
+ pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
+
+ /* Setup outbound MEM window */
+ for(i = 0; i < 3; i++)
+ if (hose->mem_resources[i].flags & IORESOURCE_MEM){
+ DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
+ hose->mem_resources[i].start,
+ hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1);
+ pcieow->pexotar = (hose->mem_resources[i].start) >> 12
+ & 0x000fffff;
+ pcieow->pexotear = 0;
+ pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
+ & 0x000fffff;
+ /* Enable, Mem R/W */
+ pcieow->pexowar = 0x80044000 |
+ (__ilog2(hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1)
+ - 1);
+ pcieow++;
+ }
+
+ /* Setup outbound IO window */
+ if (hose->io_resource.flags & IORESOURCE_IO){
+ DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
+ hose->io_resource.start,
+ hose->io_resource.end - hose->io_resource.start + 1,
+ hose->io_base_phys);
+ pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
+ pcieow->pexotear = 0;
+ pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
+ /* Enable, IO R/W */
+ pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
+ - hose->io_resource.start + 1) - 1);
+ }
+
+ /* Setup 2G inbound Memory Window @ 0 */
+ pcieiw->pexitar = 0x00000000;
+ pcieiw->pexiwbar = 0x00000000;
+ /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+ pcieiw->pexiwar = 0xa0f5501e;
+}
+
+static void __init
+mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
+{
+ volatile struct ccsr_pex *pcie;
+ u16 cmd;
+ unsigned int temps;
+
+ DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
+ pcie_offset, pcie_size);
+
+ pcie = ioremap(pcie_offset, pcie_size);
+
+ early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_IO;
+ early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+
+ early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+
+ /* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
+ early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
+ temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+ early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
+}
+
+int __init add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ int *bus_range;
+ int has_address = 0;
+ int primary = 0;
+
+ DBG("Adding PCIE host bridge %s\n", dev->full_name);
+
+ /* Fetch host bridge registers address */
+ has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+
+ /* Get bus range if any */
+ bus_range = (int *) get_property(dev, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int))
+ printk(KERN_WARNING "Can't get bus-range for %s, assume"
+ " bus 0\n", dev->full_name);
+
+ hose = pcibios_alloc_controller();
+ if (!hose)
+ return -ENOMEM;
+ hose->arch_data = dev;
+ hose->set_cfg_type = 1;
+
+ /* last_busno = 0xfe cause by MPC8641 PCIE bug */
+ hose->first_busno = bus_range ? bus_range[0] : 0x0;
+ hose->last_busno = bus_range ? bus_range[1] : 0xfe;
+
+ setup_indirect_pcie(hose, rsrc.start, rsrc.start + 0x4);
+
+ /* Setup the PCIE host controller. */
+ mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
+
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ primary = 1;
+
+ printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
+ "Firmware bus number: %d->%d\n",
+ rsrc.start, hose->first_busno, hose->last_busno);
+
+ DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+ hose, hose->cfg_addr, hose->cfg_data);
+
+ /* Interpret the "ranges" property */
+ /* This also maps the I/O region and sets isa_io/mem_base */
+ pci_process_bridge_OF_ranges(hose, dev, primary);
+
+ /* Setup PEX window registers */
+ setup_pcie_atmu(hose, &rsrc);
+
+ return 0;
+}
+
+static void __devinit quirk_ali1575(struct pci_dev *dev)
+{
+ unsigned short temp;
+
+ /*
+ * ALI1575 interrupts route table setup:
+ *
+ * IRQ pin IRQ#
+ * PIRQA ---- 3
+ * PIRQB ---- 4
+ * PIRQC ---- 5
+ * PIRQD ---- 6
+ * PIRQE ---- 9
+ * PIRQF ---- 10
+ * PIRQG ---- 11
+ * PIRQH ---- 12
+ *
+ * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
+ * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
+ */
+ pci_write_config_dword(dev, 0x48, 0xb9317542);
+
+ /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
+ pci_write_config_byte(dev, 0x86, 0x0c);
+
+ /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
+ pci_write_config_byte(dev, 0x87, 0x0d);
+
+ /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x88, 0x0f);
+
+ /* USB 2.0 controller, interrupt: PIRQ7 */
+ pci_write_config_byte(dev, 0x74, 0x06);
+
+ /* Audio controller, interrupt: PIRQE */
+ pci_write_config_byte(dev, 0x8a, 0x0c);
+
+ /* Modem controller, interrupt: PIRQF */
+ pci_write_config_byte(dev, 0x8b, 0x0d);
+
+ /* HD audio controller, interrupt: PIRQG */
+ pci_write_config_byte(dev, 0x8c, 0x0e);
+
+ /* Serial ATA interrupt: PIRQD */
+ pci_write_config_byte(dev, 0x8d, 0x0b);
+
+ /* SMB interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x8e, 0x0f);
+
+ /* PMU ACPI SCI interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x8f, 0x0f);
+
+ /* Primary PATA IDE IRQ: 14
+ * Secondary PATA IDE IRQ: 15
+ */
+ pci_write_config_byte(dev, 0x44, 0x3d);
+ pci_write_config_byte(dev, 0x75, 0x0f);
+
+ /* Set IRQ14 and IRQ15 to legacy IRQs */
+ pci_read_config_word(dev, 0x46, &temp);
+ temp |= 0xc000;
+ pci_write_config_word(dev, 0x46, temp);
+
+ /* Set i8259 interrupt trigger
+ * IRQ 3: Level
+ * IRQ 4: Level
+ * IRQ 5: Level
+ * IRQ 6: Level
+ * IRQ 7: Level
+ * IRQ 9: Level
+ * IRQ 10: Level
+ * IRQ 11: Level
+ * IRQ 12: Level
+ * IRQ 14: Edge
+ * IRQ 15: Edge
+ */
+ outb(0xfa, 0x4d0);
+ outb(0x1e, 0x4d1);
+}
+
+static void __devinit quirk_uli5288(struct pci_dev *dev)
+{
+ unsigned char c;
+
+ pci_read_config_byte(dev,0x83,&c);
+ c |= 0x80;
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_write_config_byte(dev, 0x09, 0x01);
+ pci_write_config_byte(dev, 0x0a, 0x06);
+
+ pci_read_config_byte(dev,0x83,&c);
+ c &= 0x7f;
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_read_config_byte(dev,0x84,&c);
+ c |= 0x01;
+ pci_write_config_byte(dev, 0x84, c);
+}
+
+static void __devinit quirk_uli5229(struct pci_dev *dev)
+{
+ unsigned short temp;
+ pci_write_config_word(dev, 0x04, 0x0405);
+ pci_read_config_word(dev, 0x4a, &temp);
+ temp |= 0x1000;
+ pci_write_config_word(dev, 0x4a, temp);
+}
+
+static void __devinit early_uli5249(struct pci_dev *dev)
+{
+ unsigned char temp;
+ pci_write_config_word(dev, 0x04, 0x0007);
+ pci_read_config_byte(dev, 0x7c, &temp);
+ pci_write_config_byte(dev, 0x7c, 0x80);
+ pci_write_config_byte(dev, 0x09, 0x01);
+ pci_write_config_byte(dev, 0x7c, temp);
+ dev->class |= 0x1;
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
^ permalink raw reply related
* [PATCH 5/9 v3] Add the MPC8641 HPCN platform files.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/platforms/86xx/mpc8641_hpcn.h | 54 +++++
arch/powerpc/platforms/86xx/mpc86xx.h | 28 ++
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 326 ++++++++++++++++++++++++++++
arch/powerpc/platforms/86xx/mpc86xx_smp.c | 117 ++++++++++
4 files changed, 525 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
new file mode 100644
index 0000000..5042253
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
@@ -0,0 +1,54 @@
+/*
+ * MPC8641 HPCN board definitions
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ */
+
+#ifndef __MPC8641_HPCN_H__
+#define __MPC8641_HPCN_H__
+
+#include <linux/config.h>
+#include <linux/init.h>
+
+/* PCI interrupt controller */
+#define PIRQA 3
+#define PIRQB 4
+#define PIRQC 5
+#define PIRQD 6
+#define PIRQ7 7
+#define PIRQE 9
+#define PIRQF 10
+#define PIRQG 11
+#define PIRQH 12
+
+/* PCI-Express memory map */
+#define MPC86XX_PCIE_LOWER_IO 0x00000000
+#define MPC86XX_PCIE_UPPER_IO 0x00ffffff
+
+#define MPC86XX_PCIE_LOWER_MEM 0x80000000
+#define MPC86XX_PCIE_UPPER_MEM 0x9fffffff
+
+#define MPC86XX_PCIE_IO_BASE 0xe2000000
+#define MPC86XX_PCIE_MEM_OFFSET 0x00000000
+
+#define MPC86XX_PCIE_IO_SIZE 0x01000000
+
+#define PCIE1_CFG_ADDR_OFFSET (0x8000)
+#define PCIE1_CFG_DATA_OFFSET (0x8004)
+
+#define PCIE2_CFG_ADDR_OFFSET (0x9000)
+#define PCIE2_CFG_DATA_OFFSET (0x9004)
+
+#define MPC86xx_PCIE_OFFSET PCIE1_CFG_ADDR_OFFSET
+#define MPC86xx_PCIE_SIZE (0x1000)
+
+#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */
+
+#endif /* __MPC8641_HPCN_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
new file mode 100644
index 0000000..e3c9e4f
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MPC86XX_H__
+#define __MPC86XX_H__
+
+/*
+ * Declaration for the various functions exported by the
+ * mpc86xx_* files. Mostly for use by mpc86xx_setup().
+ */
+
+extern int __init add_bridge(struct device_node *dev);
+
+extern void __init setup_indirect_pcie(struct pci_controller *hose,
+ u32 cfg_addr, u32 cfg_data);
+extern void __init setup_indirect_pcie_nomap(struct pci_controller *hose,
+ void __iomem *cfg_addr,
+ void __iomem *cfg_data);
+
+extern void __init mpc86xx_smp_init(void);
+
+#endif /* __MPC86XX_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
new file mode 100644
index 0000000..483c21d
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -0,0 +1,326 @@
+/*
+ * MPC86xx HPCN board specific routines
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc86xx.h>
+#include <asm/prom.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+#include <asm/i8259.h>
+
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+unsigned long pci_dram_offset = 0;
+#endif
+
+
+/*
+ * Internal interrupts are all Level Sensitive, and Positive Polarity
+ */
+
+static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCIE1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PCIE2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
+ 0x0, /* External 0: */
+ 0x0, /* External 1: */
+ 0x0, /* External 2: */
+ 0x0, /* External 3: */
+ 0x0, /* External 4: */
+ 0x0, /* External 5: */
+ 0x0, /* External 6: */
+ 0x0, /* External 7: */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */
+ 0x0, /* External 11: */
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+};
+
+
+void __init
+mpc86xx_hpcn_init_irq(void)
+{
+ struct mpic *mpic1;
+ phys_addr_t openpic_paddr;
+
+ /* Determine the Physical Address of the OpenPIC regs */
+ openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
+
+ /* Alloc mpic structure and per isu has 16 INT entries. */
+ mpic1 = mpic_alloc(openpic_paddr,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
+ mpc86xx_hpcn_openpic_initsenses,
+ sizeof(mpc86xx_hpcn_openpic_initsenses),
+ " MPIC ");
+ BUG_ON(mpic1 == NULL);
+
+ /* 48 Internal Interrupts */
+ mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
+ mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
+ mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
+
+ /* 16 External interrupts */
+ mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
+
+ mpic_init(mpic1);
+
+#ifdef CONFIG_PCI
+ mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
+ i8259_init(0, I8259_OFFSET);
+#endif
+}
+
+
+
+#ifdef CONFIG_PCI
+/*
+ * interrupt routing
+ */
+
+int
+mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] = {
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */
+ {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */
+ {0, 0, 0, 0}, /* IDSEL 19 */
+ {0, 0, 0, 0}, /* IDSEL 20 */
+ {0, 0, 0, 0}, /* IDSEL 21 */
+ {0, 0, 0, 0}, /* IDSEL 22 */
+ {0, 0, 0, 0}, /* IDSEL 23 */
+ {0, 0, 0, 0}, /* IDSEL 24 */
+ {0, 0, 0, 0}, /* IDSEL 25 */
+ {PIRQD, PIRQA, PIRQB, PIRQC}, /* IDSEL 26 -- PCI Bridge*/
+ {PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */
+ {PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */
+ {PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */
+ {PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/
+ {PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */
+ };
+
+ const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
+}
+
+
+int
+mpc86xx_exclude_device(u_char bus, u_char devfn)
+{
+#if !defined(CONFIG_PCI)
+ if (bus == 0 && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+
+ return PCIBIOS_SUCCESSFUL;
+}
+#endif /* CONFIG_PCI */
+
+
+static void __init
+mpc86xx_hpcn_setup_arch(void)
+{
+ struct device_node *np;
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ if (np != 0) {
+ unsigned int *fp;
+
+ fp = (int *)get_property(np, "clock-frequency", NULL);
+ if (fp != 0)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(np);
+ }
+
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ add_bridge(np);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = mpc86xx_map_irq;
+ ppc_md.pci_exclude_device = mpc86xx_exclude_device;
+#endif
+
+ printk("MPC86xx HPCN board from Freescale Semiconductor\n");
+
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+
+#ifdef CONFIG_SMP
+ mpc86xx_smp_init();
+#endif
+}
+
+
+void
+mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
+{
+ struct device_node *root;
+ uint memsize = total_memory;
+ const char *model = "";
+ uint svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+
+ root = of_find_node_by_path("/");
+ if (root)
+ model = get_property(root, "model", NULL);
+ seq_printf(m, "Machine\t\t: %s\n", model);
+ of_node_put(root);
+
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mpc86xx_hpcn_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "mpc86xx"))
+ return 1; /* Looks good */
+
+ return 0;
+}
+
+
+void
+mpc86xx_restart(char *cmd)
+{
+ void __iomem *rstcr;
+
+ rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
+
+ local_irq_disable();
+
+ /* Assert reset request to Reset Control Register */
+ out_be32(rstcr, 0x2);
+
+ /* not reached */
+}
+
+
+long __init
+mpc86xx_time_init(void)
+{
+ unsigned int temp;
+
+ /* Set the time base to zero */
+ mtspr(SPRN_TBWL, 0);
+ mtspr(SPRN_TBWU, 0);
+
+ temp = mfspr(SPRN_HID0);
+ temp |= HID0_TBEN;
+ mtspr(SPRN_HID0, temp);
+ asm volatile("isync");
+
+ return 0;
+}
+
+
+define_machine(mpc86xx_hpcn) {
+ .name = "MPC86xx HPCN",
+ .probe = mpc86xx_hpcn_probe,
+ .setup_arch = mpc86xx_hpcn_setup_arch,
+ .init_IRQ = mpc86xx_hpcn_init_irq,
+ .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
+ .get_irq = mpic_get_irq,
+ .restart = mpc86xx_restart,
+ .time_init = mpc86xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
new file mode 100644
index 0000000..944ec4b
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
@@ -0,0 +1,117 @@
+/*
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ * Zhang Wei <wei.zhang@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/pci-bridge.h>
+#include <asm-powerpc/mpic.h>
+#include <asm/mpc86xx.h>
+#include <asm/cacheflush.h>
+
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+extern void __secondary_start_mpc86xx(void);
+extern unsigned long __secondary_hold_acknowledge;
+
+
+static void __init
+smp_86xx_release_core(int nr)
+{
+ void *mcm_vaddr;
+ unsigned long vaddr, pcr;
+
+ if (nr < 0 || nr >= NR_CPUS)
+ return;
+
+ /*
+ * Startup Core #nr.
+ */
+ mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
+ MPC86xx_MCM_SIZE);
+ vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;
+ pcr = in_be32((volatile unsigned *)vaddr);
+ pcr |= 1 << (nr + 24);
+ out_be32((volatile unsigned *)vaddr, pcr);
+}
+
+
+static void __init
+smp_86xx_kick_cpu(int nr)
+{
+ unsigned int save_vector;
+ unsigned long target, flags;
+ int n = 0;
+ volatile unsigned int *vector
+ = (volatile unsigned int *)(KERNELBASE + 0x100);
+
+ if (nr < 0 || nr >= NR_CPUS)
+ return;
+
+ pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr);
+
+ local_irq_save(flags);
+ local_irq_disable();
+
+ /* Save reset vector */
+ save_vector = *vector;
+
+ /* Setup fake reset vector to call __secondary_start_mpc86xx. */
+ target = (unsigned long) __secondary_start_mpc86xx;
+ create_branch((unsigned long)vector, target, BRANCH_SET_LINK);
+
+ /* Kick that CPU */
+ smp_86xx_release_core(nr);
+
+ /* Wait a bit for the CPU to take the exception. */
+ while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000))
+ mdelay(1);
+
+ /* Restore the exception vector */
+ *vector = save_vector;
+ flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
+
+ local_irq_restore(flags);
+
+ pr_debug("wait CPU #%d for %d msecs.\n", nr, n);
+}
+
+
+static void __init
+smp_86xx_setup_cpu(int cpu_nr)
+{
+ mpic_setup_this_cpu();
+}
+
+
+struct smp_ops_t smp_86xx_ops = {
+ .message_pass = smp_mpic_message_pass,
+ .probe = smp_mpic_probe,
+ .kick_cpu = smp_86xx_kick_cpu,
+ .setup_cpu = smp_86xx_setup_cpu,
+ .take_timebase = smp_generic_take_timebase,
+ .give_timebase = smp_generic_give_timebase,
+};
+
+
+void __init
+mpc86xx_smp_init(void)
+{
+ smp_ops = &smp_86xx_ops;
+}
^ permalink raw reply related
* [PATCH 4/9 v3] Add starting of secondary 86xx CPUs.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
Clear the high BATS during load_up_mmu if FTR_HAS_HIGH_BATS.
Allow just a bit more time for secondary CPUs to phone home.
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/head_32.S | 14 +++++++++++++-
arch/powerpc/kernel/smp.c | 2 +-
arch/powerpc/mm/ppc_mmu_32.c | 4 ++--
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index a0579e8..b25b259 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -973,6 +973,13 @@ __secondary_start_gemini:
b __secondary_start
#endif /* CONFIG_GEMINI */
+ .globl __secondary_start_mpc86xx
+__secondary_start_mpc86xx:
+ mfspr r3, SPRN_PIR
+ stw r3, __secondary_hold_acknowledge@l(0)
+ mr r24, r3 /* cpu # */
+ b __secondary_start
+
.globl __secondary_start_pmac_0
__secondary_start_pmac_0:
/* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
@@ -1088,7 +1095,12 @@ load_up_mmu:
LOAD_BAT(1,r3,r4,r5)
LOAD_BAT(2,r3,r4,r5)
LOAD_BAT(3,r3,r4,r5)
-
+BEGIN_FTR_SECTION
+ LOAD_BAT(4,r3,r4,r5)
+ LOAD_BAT(5,r3,r4,r5)
+ LOAD_BAT(6,r3,r4,r5)
+ LOAD_BAT(7,r3,r4,r5)
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
blr
/*
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 530f7db..c5d179d 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -492,7 +492,7 @@ int __devinit __cpu_up(unsigned int cpu)
* -- Cort
*/
if (system_state < SYSTEM_RUNNING)
- for (c = 5000; c && !cpu_callin_map[cpu]; c--)
+ for (c = 50000; c && !cpu_callin_map[cpu]; c--)
udelay(100);
#ifdef CONFIG_HOTPLUG_CPU
else
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index ab5cd72..2ed43a4 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -43,13 +43,13 @@ unsigned long _SDR1;
union ubat { /* BAT register values to be loaded */
BAT bat;
u32 word[2];
-} BATS[4][2]; /* 4 pairs of IBAT, DBAT */
+} BATS[8][2]; /* 8 pairs of IBAT, DBAT */
struct batrange { /* stores address ranges mapped by BATs */
unsigned long start;
unsigned long limit;
unsigned long phys;
-} bat_addrs[4];
+} bat_addrs[8];
/*
* Return PA for this VA if it is mapped by a BAT, or 0
^ permalink raw reply related
* [PATCH 3/9 v3] Add 8641 CPU table entry.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/cputable.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index abf7d42..1c11488 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -722,6 +722,18 @@ #if CLASSIC_PPC
.oprofile_type = PPC_OPROFILE_G4,
.platform = "ppc7450",
},
+ { /* 8641 */
+ .pvr_mask = 0xffffffff,
+ .pvr_value = 0x80040010,
+ .cpu_name = "8641",
+ .cpu_features = CPU_FTRS_7447A,
+ .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .num_pmcs = 6,
+ .cpu_setup = __setup_cpu_745x
+ },
+
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00810000,
^ permalink raw reply related
* [PATCH 2/9 v3] Add mpc8641_hpcn_defconfig config file.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/configs/mpc8641_hpcn_defconfig | 921 +++++++++++++++++++++++++++
1 files changed, 921 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc8641_hpcn_defconfig b/arch/powerpc/configs/mpc8641_hpcn_defconfig
new file mode 100644
index 0000000..d7a30f9
--- /dev/null
+++ b/arch/powerpc/configs/mpc8641_hpcn_defconfig
@@ -0,0 +1,921 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.17-rc3
+# Fri Jun 16 10:47:09 2006
+#
+# CONFIG_PPC64 is not set
+CONFIG_PPC32=y
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_GENERIC_TBSYNC=y
+# CONFIG_DEFAULT_UIMAGE is not set
+
+#
+# Processor support
+#
+# CONFIG_CLASSIC32 is not set
+# CONFIG_PPC_52xx is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_85xx is not set
+CONFIG_PPC_86xx=y
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+CONFIG_6xx=y
+CONFIG_PPC_FPU=y
+CONFIG_ALTIVEC=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_CPUSETS is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+# CONFIG_SLAB is not set
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_SLOB=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_MPIC=y
+# CONFIG_WANT_EARLY_SERIAL is not set
+CONFIG_PPC_INDIRECT_PCI_BE=y
+
+#
+# Platform Support
+#
+CONFIG_MPC8641_HPCN=y
+CONFIG_MPC8641=y
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT_BKL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IRQ_ALL_CPUS is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_I8259=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+CONFIG_VITESSE_PHY=y
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_GIANFAR=y
+# CONFIG_GFAR_NAPI is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=y
+# CONFIG_NFSD_V3 is not set
+CONFIG_NFSD_TCP=y
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Instrumentation Support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_UNWIND_INFO is not set
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
+# CONFIG_PPC_EARLY_DEBUG_G5 is not set
+# CONFIG_PPC_EARLY_DEBUG_RTAS is not set
+# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
+# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
^ permalink raw reply related
* [PATCH 1/9 v3] Add the mpc8641 hpcn Kconfig and Makefiles.
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/Kconfig | 15 ++++++++++++--
arch/powerpc/platforms/Makefile | 1 +
arch/powerpc/platforms/86xx/Kconfig | 36 ++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/86xx/Makefile | 10 +++++++++
4 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 4ef2478..65f4cd1 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -141,6 +141,15 @@ config PPC_85xx
select FSL_SOC
select 85xx
+config PPC_86xx
+ bool "Freescale 86xx"
+ select 6xx
+ select FSL_SOC
+ select PPC_FPU
+ select ALTIVEC
+ help
+ The Freescale E600 SoCs have 74xx cores.
+
config 40x
bool "AMCC 40x"
@@ -549,6 +558,7 @@ source arch/powerpc/platforms/embedded6x
source arch/powerpc/platforms/4xx/Kconfig
source arch/powerpc/platforms/83xx/Kconfig
source arch/powerpc/platforms/85xx/Kconfig
+source arch/powerpc/platforms/86xx/Kconfig
source arch/powerpc/platforms/8xx/Kconfig
source arch/powerpc/platforms/cell/Kconfig
@@ -780,6 +790,7 @@ config GENERIC_ISA_DMA
config PPC_I8259
bool
+ default y if MPC8641_HPCN
default n
config PPC_INDIRECT_PCI
@@ -802,8 +813,8 @@ config MCA
bool
config PCI
- bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
- default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx
+ bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_86xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
+ default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx && !PPC_86xx
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
default PCI_QSPAN if !4xx && !CPM2 && 8xx
help
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index c4f6b0d..2928636 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PPC_CHRP) += chrp/
obj-$(CONFIG_4xx) += 4xx/
obj-$(CONFIG_PPC_83xx) += 83xx/
obj-$(CONFIG_PPC_85xx) += 85xx/
+obj-$(CONFIG_PPC_86xx) += 86xx/
obj-$(CONFIG_PPC_PSERIES) += pseries/
obj-$(CONFIG_PPC_ISERIES) += iseries/
obj-$(CONFIG_PPC_MAPLE) += maple/
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
new file mode 100644
index 0000000..3a87863
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -0,0 +1,36 @@
+menu "Platform Support"
+ depends on PPC_86xx
+
+choice
+ prompt "Machine Type"
+ default MPC8641_HPCN
+
+config MPC8641_HPCN
+ bool "Freescale MPC8641 HPCN"
+ help
+ This option enables support for the MPC8641 HPCN board.
+
+endchoice
+
+
+config MPC8641
+ bool
+ select PPC_INDIRECT_PCI
+ select PPC_UDBG_16550
+ default y if MPC8641_HPCN
+
+config MPIC
+ bool
+ default y
+
+config PPC_INDIRECT_PCI_BE
+ bool
+ depends on PPC_86xx
+ default y
+
+config PPC_STD_MMU
+ bool
+ depends on PPC_86xx
+ default y
+
+endmenu
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
new file mode 100644
index 0000000..7be796c
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the PowerPC 86xx linux kernel.
+#
+
+
+ifeq ($(CONFIG_PPC_86xx),y)
+obj-$(CONFIG_SMP) += mpc86xx_smp.o
+endif
+obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
+obj-$(CONFIG_PCI) += pci.o mpc86xx_pcie.o
^ permalink raw reply related
* [PATCH 0/9 v3] Introduce the MPC8641 HPCN platform
From: Jon Loeliger @ 2006-06-17 22:52 UTC (permalink / raw)
To: linuxppc-dev
This is the third posting of a series of patches
that introduces the MPC8641 HPCN platform. This
version corrects all of the suggestions from Kumar,
and shows an ACK from Jeff Garzik for the netdev
related parts. It also addresses all of the problems
that Ben brought up related to multi-platform issues.
It does not use IRQ settings from the device tree yet;
that will come as a follow on patch when Ben's IRQ
rewrite is more solid.
Please consider this for addition into the 2.6.18 queue.
Collectively:
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com>
Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
Acked-by: Jeff Garzik <jeff@garzik.org>
^ permalink raw reply
* [PATCH] Prevent duplicate lmb reservations for Device Tree blob.
From: Jon Loeliger @ 2006-06-17 22:51 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
We talked about preventing the device tree blob from being
reserved multiple times. This patch implements it.
arch/powerpc/kernel/prom.c | 13 +++++++++++--
1 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index d77d24a..6290232 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -1267,13 +1267,16 @@ static void __init early_reserve_mem(voi
{
u64 base, size;
u64 *reserve_map;
+ unsigned long self_base;
+ unsigned long self_size;
reserve_map = (u64 *)(((unsigned long)initial_boot_params) +
initial_boot_params->off_mem_rsvmap);
/* before we do anything, lets reserve the dt blob */
- lmb_reserve(__pa((unsigned long)initial_boot_params),
- initial_boot_params->totalsize);
+ self_base = __pa((unsigned long)initial_boot_params);
+ self_size = initial_boot_params->totalsize;
+ lmb_reserve(self_base, self_size);
#ifdef CONFIG_PPC32
/*
@@ -1289,6 +1292,9 @@ #ifdef CONFIG_PPC32
size_32 = *(reserve_map_32++);
if (size_32 == 0)
break;
+ /* skip if the reservation is for the blob */
+ if (base_32 == self_base && size_32 == self_size)
+ continue;
DBG("reserving: %x -> %x\n", base_32, size_32);
lmb_reserve(base_32, size_32);
}
@@ -1300,6 +1306,9 @@ #endif
size = *(reserve_map++);
if (size == 0)
break;
+ /* skip if the reservation is for the blob */
+ if (base == self_base && size == self_size)
+ continue;
DBG("reserving: %llx -> %llx\n", base, size);
lmb_reserve(base, size);
}
^ permalink raw reply related
* [PATCH] Guard L3CR references with CPU_FTR_L3CR.
From: Jon Loeliger @ 2006-06-17 22:49 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/cpu_setup_6xx.S | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index 55ed771..365381f 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -210,9 +210,11 @@ setup_745x_specifics:
* the firmware. If any, we disable NAP capability as
* it's known to be bogus on rev 2.1 and earlier
*/
+BEGIN_FTR_SECTION
mfspr r11,SPRN_L3CR
andis. r11,r11,L3CR_L3E@h
beq 1f
+END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
lwz r6,CPU_SPEC_FEATURES(r5)
andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
beq 1f
^ permalink raw reply related
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