Virtex-4 PPC405 first instruction after reset - ultracontroller vs regular designs

Virtex-4 PPC405 first instruction after reset - ultracontroller vs regular designs

[Mohammad Sadegh Sadri]

Hi all

may be not really related to linux but I hope some body can help me with th=
is

As you know PPC405 runs the instruction at 0xfffffffc address as it's first=
 instruction

when generating a base system for ML403 using XPS, one should certainly add=
 PLB BRAM controller , this module will reside on PLB and contains some BRA=
M instances. A Code called boot loop is located in these block memories. PP=
C405 runs boot loop until sysace makes linux elf ready.=20

Looking in the generated xparameters.h you see that the base address for PL=
B BRAM IF is 0xffff0000 and since the first instruction should be located a=
t 0xfffffffc , you have to define the size of this PLB BRAM IF equal to 64k=
 when generating your system in XPS.

Now looking at ultracontroller reference design one can see that PPC405 loo=
ks for 0xfffffffc address on its IS OCM bus , but in regular designs as you=
 see PPC405 looks for this address on PLB Instruction bus, I'm wondering ho=
w PPC understands to do so in each of these designs? Does PPC have a specia=
l input port which is assigned a fix value and indicates where should PPC l=
ook for 0xfffffffc address ( ISOCM or IS PLB )?

thanks.

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