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* [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq
@ 2017-09-07 12:13 Vaibhav Jain
  2017-09-07 17:25 ` christophe lombard
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Vaibhav Jain @ 2017-09-07 12:13 UTC (permalink / raw)
  To: linuxppc-dev, Frederic Barrat, Christophe Lombard
  Cc: Vaibhav Jain, Andrew Donnellan, Philippe Bergheaud,
	Alastair D'Silva

For PSL9 currently we aren't dumping the PSL FIR1/2 registers when a
PSL error interrupt is triggered. Contents of these registers are
useful in debugging AFU issues.

This patch fixes issue by updating the cxl_native_err_irq_dump_regs()
to dump these regs on PSL error interrupt thereby bringing the
behavior in line with PSL on POWER-8.

Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
---
 drivers/misc/cxl/native.c | 13 +++++++++++--
 drivers/misc/cxl/pci.c    |  1 +
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 4a82c313cf71..60b91e95821d 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -1261,8 +1261,17 @@ void cxl_native_err_irq_dump_regs(struct cxl *adapter)
 {
 	u64 fir1, fir2;
 
-	fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
-	fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
+	if (cxl_is_power8()) {
+		fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
+		fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
+	} else if (cxl_is_power9()) {
+		fir1 = cxl_p1_read(adapter, CXL_PSL9_FIR1);
+		fir2 = cxl_p1_read(adapter, CXL_PSL9_FIR2);
+	} else {
+		/* Dont report garbage */
+		fir1 = fir2 = 0;
+		WARN_ON(1);
+	}
 
 	dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
 }
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index d18b3d9292fd..597e145f38e3 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1762,6 +1762,7 @@ static const struct cxl_service_layer_ops psl9_ops = {
 	.debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
 	.debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
 	.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
+	.err_irq_dump_registers = cxl_native_err_irq_dump_regs,
 	.debugfs_stop_trace = cxl_stop_trace_psl9,
 	.write_timebase_ctrl = write_timebase_ctrl_psl9,
 	.timebase_read = timebase_read_psl9,
-- 
2.13.5

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq
  2017-09-07 12:13 [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq Vaibhav Jain
@ 2017-09-07 17:25 ` christophe lombard
  2017-09-08  1:15 ` Andrew Donnellan
  2017-10-09 16:46 ` Vaibhav Jain
  2 siblings, 0 replies; 4+ messages in thread
From: christophe lombard @ 2017-09-07 17:25 UTC (permalink / raw)
  To: Vaibhav Jain, linuxppc-dev, Frederic Barrat, Christophe Lombard
  Cc: Philippe Bergheaud, Andrew Donnellan, Alastair D'Silva

[-- Attachment #1: Type: text/plain, Size: 683 bytes --]

Le 07/09/2017 à 14:13, Vaibhav Jain a écrit :
> For PSL9 currently we aren't dumping the PSL FIR1/2 registers when a
> PSL error interrupt is triggered. Contents of these registers are
> useful in debugging AFU issues.
>
> This patch fixes issue by updating the cxl_native_err_irq_dump_regs()
> to dump these regs on PSL error interrupt thereby bringing the
> behavior in line with PSL on POWER-8.
>
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---
>   drivers/misc/cxl/native.c | 13 +++++++++++--
>   drivers/misc/cxl/pci.c    |  1 +
>   2 files changed, 12 insertions(+), 2 deletions(-)

sounds good.

Acked-by:  Christophe Lombard <clombard@linux.vnet.ibm.com>


[-- Attachment #2: Type: text/html, Size: 1225 bytes --]

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq
  2017-09-07 12:13 [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq Vaibhav Jain
  2017-09-07 17:25 ` christophe lombard
@ 2017-09-08  1:15 ` Andrew Donnellan
  2017-10-09 16:46 ` Vaibhav Jain
  2 siblings, 0 replies; 4+ messages in thread
From: Andrew Donnellan @ 2017-09-08  1:15 UTC (permalink / raw)
  To: Vaibhav Jain, linuxppc-dev, Frederic Barrat, Christophe Lombard
  Cc: Philippe Bergheaud, Alastair D'Silva

LGTM

Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>

On 07/09/17 22:13, Vaibhav Jain wrote:
> For PSL9 currently we aren't dumping the PSL FIR1/2 registers when a
> PSL error interrupt is triggered. Contents of these registers are
> useful in debugging AFU issues.
> 
> This patch fixes issue by updating the cxl_native_err_irq_dump_regs()
> to dump these regs on PSL error interrupt thereby bringing the
> behavior in line with PSL on POWER-8.
> 
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---
>   drivers/misc/cxl/native.c | 13 +++++++++++--
>   drivers/misc/cxl/pci.c    |  1 +
>   2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
> index 4a82c313cf71..60b91e95821d 100644
> --- a/drivers/misc/cxl/native.c
> +++ b/drivers/misc/cxl/native.c
> @@ -1261,8 +1261,17 @@ void cxl_native_err_irq_dump_regs(struct cxl *adapter)
>   {
>   	u64 fir1, fir2;
>   
> -	fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
> -	fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
> +	if (cxl_is_power8()) {
> +		fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
> +		fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
> +	} else if (cxl_is_power9()) {
> +		fir1 = cxl_p1_read(adapter, CXL_PSL9_FIR1);
> +		fir2 = cxl_p1_read(adapter, CXL_PSL9_FIR2);
> +	} else {
> +		/* Dont report garbage */
> +		fir1 = fir2 = 0;
> +		WARN_ON(1);
> +	}
>   
>   	dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
>   }
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index d18b3d9292fd..597e145f38e3 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -1762,6 +1762,7 @@ static const struct cxl_service_layer_ops psl9_ops = {
>   	.debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
>   	.debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
>   	.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
> +	.err_irq_dump_registers = cxl_native_err_irq_dump_regs,
>   	.debugfs_stop_trace = cxl_stop_trace_psl9,
>   	.write_timebase_ctrl = write_timebase_ctrl_psl9,
>   	.timebase_read = timebase_read_psl9,
> 

-- 
Andrew Donnellan              OzLabs, ADL Canberra
andrew.donnellan@au1.ibm.com  IBM Australia Limited

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq
  2017-09-07 12:13 [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq Vaibhav Jain
  2017-09-07 17:25 ` christophe lombard
  2017-09-08  1:15 ` Andrew Donnellan
@ 2017-10-09 16:46 ` Vaibhav Jain
  2 siblings, 0 replies; 4+ messages in thread
From: Vaibhav Jain @ 2017-10-09 16:46 UTC (permalink / raw)
  To: linuxppc-dev, Frederic Barrat, Christophe Lombard
  Cc: Andrew Donnellan, Philippe Bergheaud, Alastair D'Silva

Fred just pointed out that there is no register named FIR2 on PSL9
instead we have a FIR_MASK register in its place. So I will re-spin this
patch with the correct register name.

Thanks everyone for the review and to Fred for pointing out the issue.

-- 
Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Linux Technology Center, IBM India Pvt. Ltd.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2017-10-09 16:46 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2017-09-07 12:13 [PATCH] cxl: Dump PSL_FIR1/2 registers on PSL9 error irq Vaibhav Jain
2017-09-07 17:25 ` christophe lombard
2017-09-08  1:15 ` Andrew Donnellan
2017-10-09 16:46 ` Vaibhav Jain

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