* Fw: Problem with NTP on (embedded) PPC, patch and RFC
From: Andrew Morton @ 2005-03-12 1:24 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Giovambattista Pulcini
Begin forwarded message:
Date: Fri, 11 Mar 2005 14:16:32 +0100
From: Giovambattista Pulcini <gpulcini@swintel.it>
To: LKML <linux-kernel@vger.kernel.org>
Subject: Problem with NTP on (embedded) PPC, patch and RFC
Hi,
On an embedded device based on the IBM 405GP, but this may be a general
problem for most PPC platforms except for chrp and gemini, the NTP
utility 'ntptime' always returns error code 5 (TIME_ERROR) even after
that NTP status reaches the PLL and FLL state. Analysis of problem
showed that the time_state variable set to TIME_ERROR by
do_settimeofday() is never set back to TIME_OK.
I found the problem in 2.4.10-1 (Lynuxworks BlueCat) but I also checked
the 2.6.11 and found similar problem. Many architectures under arch/ppc
may be affected with the exception of chrp and gemini.
Steps to reproduce:
On a PowerPC (non-CHRP) platform, set the system date with 'date',
configure and start the NTP daemon as client of a working NTP server.
Wait for it to reach the PLL/FLL state. Issue the 'ntptime' command and
check that the following two errors never disappear no matter how long
you let it running: "ntp_gettime() returns code 5 (ERROR)",
"ntp_adjtime() returns code 5 (ERROR)".
Detailed analysis:
AFAIK NTP relies on the global time_state variable which is statically
initialized to TIME_OK (kernel/timer.c). The ntptime utility calls
adjtimex() which results in a call to do_adjtimex() and prints its
return value which is basically the value of time_state. It is changed
by (kernel/timer.c)second_overflow() and by the
(kernel/time.c)do_adjtimex() state machine.
These two functions never set time_state to TIME_OK once it has been set
to TIME_ERROR.
Also, do_settimeofday() sets the STA_UNSYNC flag in time_status and sets
time_state to TIME_ERROR (in ppc but not in ppc64 nor in x86).
The function (arch/ppc/kernel/time.c)timer_interrupt() calls the
ppc_md.set_rtc_time() when certain conditions are met, as follows
(time.c:171):
if ( ppc_md.set_rtc_time && (time_status & STA_UNSYNC) == 0 &&
xtime.tv_sec - last_rtc_update >= 659 &&
abs(xtime.tv_usec - (1000000-1000000/HZ)) < 500000/HZ &&
jiffies - wall_jiffies == 1) {
if (ppc_md.set_rtc_time(xtime.tv_sec+1 + time_offset) == 0)
In the CHRP architecture (see arch/ppc/platforms/chrp_*) the specific
implementation of the set_rtc_time(), chrp_set_rtc_time(), has a check
like this (chrp_time.c:76):
if ( (time_state == TIME_ERROR) || (time_state == TIME_BAD) )
time_state = TIME_OK;
which is the only chance for the time_state to be set back to TIME_OK
after a do_settimeofday(). In other platforms this is not done.
Proposed patch:
This change should make NTP to work on any ppc platform, while not
breaking chrp and gemini. Although I've tested it only on mine.
--- linux-2.6.11/arch/ppc/kernel/time.c 2005-03-02 08:38:17.000000000 +0100
+++ linux/arch/ppc/kernel/time.c 2005-03-08 14:16:56.000000000 +0100
@@ -272,7 +272,6 @@
time_adjust = 0; /* stop active adjtime() */
time_status |= STA_UNSYNC;
- time_state = TIME_ERROR; /* p. 24, (a) */
time_maxerror = NTP_PHASE_LIMIT;
time_esterror = NTP_PHASE_LIMIT;
write_sequnlock_irqrestore(&xtime_lock, flags);
My question:
I've read some documentation but I am by no means an expert in the NTP
kernel support implementation. So I ask you where the time_state should
be reset to TIME_OK. Should this be done by the <platform>set_rtc_time() ?
Or, as in the x86 case, do_settimeofday should not set time_state to
TIME_ERROR ?
Giovambattista Pulcini
^ permalink raw reply
* [PATCH 2.6.12] mtd: Remove MTD map file for Chestnut platform.
From: Mark A. Greer @ 2005-03-12 0:40 UTC (permalink / raw)
To: dwmw2; +Cc: linux-mtd, Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 295 bytes --]
Remove Chestnut mtd map file.
The chestnut now sets up its MTD map from its platform-specific file so
the map file drivers/mtd/maps/chestnut.c is no longer needed. This
patch removes the file & the Kconfig/Makefile hooks.
Please apply.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: chestnut_mtd.patch --]
[-- Type: text/plain, Size: 3773 bytes --]
diff -Nru a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
--- a/drivers/mtd/maps/Kconfig 2005-03-11 14:51:08 -07:00
+++ b/drivers/mtd/maps/Kconfig 2005-03-11 14:51:08 -07:00
@@ -405,14 +405,6 @@
Redwood board. If you have one of these boards and would like to
use the flash chips on it, say 'Y'.
-config MTD_CHESTNUT
- tristate "CFI Flash devices mapped on IBM 750FX or IBM 750GX Eval Boards"
- depends on MTD_CFI && PPC32 && CHESTNUT && MTD_PARTITIONS
- help
- This enables access routines for the flash chips on the IBM
- 750FX and 750GX Eval Boards. If you have one of these boards and
- would like to use the flash chips on it, say 'Y'
-
config MTD_CSTM_MIPS_IXX
tristate "Flash chip mapping on ITE QED-4N-S01B, Globespan IVR or custom board"
depends on MIPS && MTD_CFI && MTD_JEDECPROBE && MTD_PARTITIONS
diff -Nru a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
--- a/drivers/mtd/maps/Makefile 2005-03-11 14:51:08 -07:00
+++ b/drivers/mtd/maps/Makefile 2005-03-11 14:51:08 -07:00
@@ -54,7 +54,6 @@
obj-$(CONFIG_MTD_IMPA7) += impa7.o
obj-$(CONFIG_MTD_FORTUNET) += fortunet.o
obj-$(CONFIG_MTD_REDWOOD) += redwood.o
-obj-$(CONFIG_MTD_CHESTNUT) += chestnut.o
obj-$(CONFIG_MTD_UCLINUX) += uclinux.o
obj-$(CONFIG_MTD_NETtel) += nettel.o
obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
diff -Nru a/drivers/mtd/maps/chestnut.c b/drivers/mtd/maps/chestnut.c
--- a/drivers/mtd/maps/chestnut.c 2005-03-11 14:51:08 -07:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,91 +0,0 @@
-/*
- * drivers/mtd/maps/chestnut.c
- *
- * $Id: chestnut.c,v 1.1 2005/01/05 16:59:50 dwmw2 Exp $
- *
- * Flash map driver for IBM Chestnut (750FXGX Eval)
- *
- * Chose not to enable 8 bit flash as it contains the firmware and board
- * info. Thus only the 32bit flash is supported.
- *
- * Author: <source@mvista.com>
- *
- * 2004 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <asm/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <platforms/chestnut.h>
-
-static struct map_info chestnut32_map = {
- .name = "User FS",
- .size = CHESTNUT_32BIT_SIZE,
- .bankwidth = 4,
- .phys = CHESTNUT_32BIT_BASE,
-};
-
-static struct mtd_partition chestnut32_partitions[] = {
- {
- .name = "User FS",
- .offset = 0,
- .size = CHESTNUT_32BIT_SIZE,
- }
-};
-
-static struct mtd_info *flash32;
-
-int __init init_chestnut(void)
-{
- /* 32-bit FLASH */
-
- chestnut32_map.virt = ioremap(chestnut32_map.phys, chestnut32_map.size);
-
- if (!chestnut32_map.virt) {
- printk(KERN_NOTICE "Failed to ioremap 32-bit flash\n");
- return -EIO;
- }
-
- simple_map_init(&chestnut32_map);
-
- flash32 = do_map_probe("cfi_probe", &chestnut32_map);
- if (flash32) {
- flash32->owner = THIS_MODULE;
- add_mtd_partitions(flash32, chestnut32_partitions,
- ARRAY_SIZE(chestnut32_partitions));
- } else {
- printk(KERN_NOTICE "map probe failed for 32-bit flash\n");
- return -ENXIO;
- }
-
- return 0;
-}
-
-static void __exit
-cleanup_chestnut(void)
-{
- if (flash32) {
- del_mtd_partitions(flash32);
- map_destroy(flash32);
- }
-
- if (chestnut32_map.virt) {
- iounmap((void *)chestnut32_map.virt);
- chestnut32_map.virt = 0;
- }
-}
-
-module_init(init_chestnut);
-module_exit(cleanup_chestnut);
-
-MODULE_DESCRIPTION("MTD map and partitions for IBM Chestnut (750fxgx Eval)");
-MODULE_AUTHOR("<source@mvista.com>");
-MODULE_LICENSE("GPL");
^ permalink raw reply
* Re: [PATCH 2.6.12] PPC32: Update chestnut platform files
From: Mark A. Greer @ 2005-03-12 0:35 UTC (permalink / raw)
To: Josh Boyer; +Cc: akpm, Embedded PPC Linux list
In-Reply-To: <1110586166.28218.10.camel@jdub.homelinux.org>
[-- Attachment #1: Type: text/plain, Size: 690 bytes --]
Josh Boyer wrote:
>On Fri, 2005-03-11 at 15:05 -0700, Mark A. Greer wrote:
>
>
>>Update Chestnut platform files.
>>
>>- Set up mtd partition from arch-specific platform file and remove
>>obsoleted mtd map.
>>
>>
>
>Could you forward this portion of the patch to the MTD maintainer? That
>way it has less of a chance getting re-added to -mm when Andrew grabs
>the latest MTD bitkeeper tree.
>
Certainly. Thanks.
Mark
----------------------------------------
Update Chestnut platform files.
- Update default config file (now enables embedded ethernet driver).
- Make some minor fixups.
- General code cleanup.
Please apply.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: chestnut.patch --]
[-- Type: text/plain, Size: 19084 bytes --]
diff -Nru a/arch/ppc/configs/chestnut_defconfig b/arch/ppc/configs/chestnut_defconfig
--- a/arch/ppc/configs/chestnut_defconfig 2005-03-11 14:51:08 -07:00
+++ b/arch/ppc/configs/chestnut_defconfig 2005-03-11 14:51:08 -07:00
@@ -1,11 +1,12 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.10-rc2
-# Tue Dec 7 16:02:09 2004
+# Linux kernel version: 2.6.11
+# Fri Mar 11 14:32:49 2005
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
@@ -35,6 +36,7 @@
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -44,6 +46,7 @@
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
#
# Loadable module support
@@ -78,7 +81,9 @@
#
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_APUS is not set
+# CONFIG_KATANA is not set
# CONFIG_WILLOW is not set
+# CONFIG_CPCI690 is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
CONFIG_CHESTNUT=y
@@ -91,6 +96,7 @@
# CONFIG_PRPMC750 is not set
# CONFIG_PRPMC800 is not set
# CONFIG_SANDPOINT is not set
+# CONFIG_RADSTONE_PPC7D is not set
# CONFIG_ADIR is not set
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
@@ -101,7 +107,9 @@
# CONFIG_RPX8260 is not set
# CONFIG_TQM8260 is not set
# CONFIG_ADS8272 is not set
+# CONFIG_PQ2FADS is not set
# CONFIG_LITE5200 is not set
+# CONFIG_MPC834x_SYS is not set
CONFIG_MV64360=y
CONFIG_MV64X60=y
@@ -128,6 +136,15 @@
CONFIG_PCI_NAMES=y
#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
# Advanced setup
#
CONFIG_ADVANCED_OPTIONS=y
@@ -154,6 +171,7 @@
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
#
# Memory Technology Devices (MTD)
@@ -181,6 +199,9 @@
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -198,13 +219,16 @@
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_CHESTNUT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xfc000000
+CONFIG_MTD_PHYSMAP_LEN=0x02000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
#
# Self-contained MTD device drivers
@@ -214,6 +238,7 @@
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
@@ -244,11 +269,13 @@
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
@@ -262,6 +289,7 @@
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
#
# ATA/ATAPI/MFM/RLL support
@@ -404,7 +432,6 @@
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
CONFIG_E100=y
-# CONFIG_E100_NAPI is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
@@ -429,6 +456,10 @@
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+# CONFIG_MV643XX_ETH_2 is not set
#
# Ethernet (10000 Mbit)
@@ -485,14 +516,6 @@
# CONFIG_INPUT_EVBUG is not set
#
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-
-#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
@@ -502,6 +525,13 @@
# CONFIG_INPUT_MISC is not set
#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+
+#
# Character devices
#
CONFIG_VT=y
@@ -520,6 +550,7 @@
#
# Non-8250 serial port support
#
+# CONFIG_SERIAL_MPSC is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
@@ -550,6 +581,11 @@
# CONFIG_RAW_DRIVER is not set
#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
# I2C support
#
# CONFIG_I2C is not set
@@ -606,6 +642,16 @@
# CONFIG_USB_GADGET is not set
#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
# File systems
#
CONFIG_EXT2_FS=y
@@ -614,6 +660,10 @@
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
@@ -664,6 +714,7 @@
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_FS_NOR_ECC is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
@@ -686,7 +737,6 @@
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
-# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -725,6 +775,7 @@
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_PRINTK_TIME is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
#
@@ -737,3 +788,7 @@
# Cryptographic options
#
# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -Nru a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c
--- a/arch/ppc/platforms/chestnut.c 2005-03-11 14:51:08 -07:00
+++ b/arch/ppc/platforms/chestnut.c 2005-03-11 14:51:08 -07:00
@@ -28,6 +28,7 @@
#include <linux/ide.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
+#include <linux/mtd/physmap.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
@@ -42,8 +43,8 @@
#include <asm/mv64x60.h>
#include <platforms/chestnut.h>
-static u32 boot_base; /* Virtual addr of 8bit boot */
-static u32 cpld_base; /* Virtual addr of CPLD Regs */
+static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
+static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
static mv64x60_handle_t bh;
@@ -65,7 +66,8 @@
*
****/
static void __init
-chestnut_calibrate_decr(void){
+chestnut_calibrate_decr(void)
+{
ulong freq;
freq = CHESTNUT_BUS_SPEED / 4;
@@ -75,8 +77,6 @@
tb_ticks_per_jiffy = freq / HZ;
tb_to_us = mulhwu_scale_factor(freq, 1000000);
-
- return;
}
static int
@@ -103,7 +103,7 @@
mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
MV64x60_TYPE_MV64460);
}
- return(mem_size);
+ return mem_size;
}
#if defined(CONFIG_SERIAL_8250)
@@ -155,7 +155,7 @@
};
const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return (PCI_IRQ_TABLE_LOOKUP);
+ return PCI_IRQ_TABLE_LOOKUP;
}
@@ -193,24 +193,30 @@
si.pci_0.pci_cmd_bits = 0;
si.pci_0.latency_timer = 0x80;
- si.window_preserve_mask_32_lo = CHESTNUT_PRESERVE_MASK;
-
for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
+#if defined(CONFIG_NOT_COHERENT_CACHE)
si.cpu_prot_options[i] = 0;
-#ifdef CONFIG_NOT_CACHE_COHERENT
- si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_NONE;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
+
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_NONE |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
- si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_WB; /* risky */
-#endif
- si.pci_0.acc_cntl_options[i] =
-#ifdef CONFIG_NOT_CACHE_COHERENT
- MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-#else
- MV64360_PCI_ACC_CNTL_SNOOP_WB | /* risky */
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
+
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_WB |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
- MV64360_PCI_ACC_CNTL_SWAP_NONE |
- MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
- MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
}
/* Lookup host bridge - on CPU 0 - no SMP support */
@@ -227,55 +233,44 @@
bh.hose_a->first_busno = 0;
bh.hose_a->last_busno = 0xff;
bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
-
}
void __init
chestnut_setup_peripherals(void)
{
-
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
+
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
+ cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
+
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
- /* Set up window for internal sram (256KByte insize) */
- mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
- boot_base = (u32)ioremap(CHESTNUT_BOOT_8BIT_BASE,
- CHESTNUT_BOOT_8BIT_SIZE);
- cpld_base = (u32)ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
+ CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
- /*
- * Configure internal SRAM -
- * Cache coherent write back, incase
- * CONFIG_MV64360_SRAM_CACHE_COHERENT set
- * Parity enabled.
- * Parity error propagation
- * Arbitration not parked for CPU only
- * Other bits are reserved.
- */
-#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
- mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
-#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
+#else
+ mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
+ sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
+ memset(sram_base, 0, MV64360_SRAM_SIZE);
- /*
- * Setting the SRAM to 0. Note that this generates parity errors on
- * internal data path in SRAM since it's first time accessing it
- * while after reset it's not configured
- */
- memset((void *)CHESTNUT_INTERNAL_SRAM_BASE, 0, CHESTNUT_INTERNAL_SRAM_SIZE);
/*
* Configure MPP pins for PCI DMA
*
@@ -312,9 +307,9 @@
(0xf << 20) | /* MPPSel13 GPIO[13] */
(0xf << 24) | /* MPPSel14 GPIO[14] */
(0xf << 28)); /* MPPSel15 GPIO[15] */
- mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL,
+ mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) |
- BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15)); /* Output */
+ BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15));
/*
* Configure the following MPP pins to indicate a level
@@ -364,7 +359,7 @@
/*
* Dismiss and then enable interrupt on CPU #0 high cause register
* BIT27 summarizes GPP interrupts 24-31
- */
+ */
mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
if (ppc_md.progress)
@@ -423,14 +418,32 @@
/* Identify the system */
printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
- printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc. (source@mvista.com)\n");
+ printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
+ " (source@mvista.com)\n");
if (ppc_md.progress)
ppc_md.progress("chestnut_setup_arch: exit", 0);
+}
+
+#ifdef CONFIG_MTD_PHYSMAP
+static struct mtd_partition ptbl;
+
+static int __init
+chestnut_setup_mtd(void)
+{
+ memset(&ptbl, 0, sizeof(ptbl));
- return;
+ ptbl.name = "User FS";
+ ptbl.size = CHESTNUT_32BIT_SIZE;
+
+ physmap_map.size = CHESTNUT_32BIT_SIZE;
+ physmap_set_partitions(&ptbl, 1);
+ return 0;
}
+arch_initcall(chestnut_setup_mtd);
+#endif
+
/**************************************************************************
* FUNCTION: chestnut_restart
*
@@ -450,7 +463,7 @@
*
* MPP24 - board reset
*/
- writeb(0x1, (void __iomem *)(cpld_base+3));
+ writeb(0x1, cpld_base + 3);
/* GPP pin tied to MPP earlier */
mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
@@ -474,37 +487,6 @@
/* NOTREACHED */
}
-#define SET_PCI_COMMAND_INVALIDATE
-#ifdef SET_PCI_COMMAND_INVALIDATE
-/*
- * Dave Wilhardt found that PCI_COMMAND_INVALIDATE must
- * be set for each device if you are using cache coherency.
- */
-static void __init
-set_pci_command_invalidate(void)
-{
- struct pci_dev *dev = NULL;
- u16 val;
-
- while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
- pci_read_config_word(dev, PCI_COMMAND, &val);
- val |= PCI_COMMAND_INVALIDATE;
- pci_write_config_word(dev, PCI_COMMAND, val);
-
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
- L1_CACHE_LINE_SIZE >> 2);
- }
-}
-#endif
-
-static void __init
-chestnut_pci_fixups(void)
-{
-#ifdef SET_PCI_COMMAND_INVALIDATE
- set_pci_command_invalidate();
-#endif
-}
-
/**************************************************************************
* FUNCTION: chestnut_map_io
*
@@ -514,27 +496,9 @@
static void __init
chestnut_map_io(void)
{
-#ifdef CONFIG_MV64360_SRAM_CACHEABLE
- io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE,
- _PAGE_KERNEL | _PAGE_GUARDED);
-#else
-#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
- io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE,
- _PAGE_KERNEL | _PAGE_GUARDED | _PAGE_COHERENT);
-#else
- io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE,
- _PAGE_IO);
-#endif /* !CONFIG_MV64360_SRAM_CACHE_COHERENT */
-#endif /* !CONFIG_MV64360_SRAM_CACHEABLE */
-
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000, _PAGE_IO);
+ io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
+ _PAGE_IO);
#endif
}
@@ -552,8 +516,6 @@
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xf000002a);
mb();
-
- return;
}
/**************************************************************************
@@ -587,7 +549,6 @@
ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
ppc_md.setup_io_mappings = chestnut_map_io;
- ppc_md.pcibios_fixup = chestnut_pci_fixups;
ppc_md.restart = chestnut_restart;
ppc_md.power_off = chestnut_power_off;
@@ -603,8 +564,6 @@
ppc_md.heartbeat = NULL;
- ppc_md.pcibios_fixup = chestnut_pci_fixups;
-
bh.p_base = CONFIG_MV64X60_NEW_BASE;
chestnut_set_bat();
@@ -618,6 +577,4 @@
if (ppc_md.progress)
ppc_md.progress("chestnut_init(): exit", 0);
-
- return;
}
diff -Nru a/arch/ppc/platforms/chestnut.h b/arch/ppc/platforms/chestnut.h
--- a/arch/ppc/platforms/chestnut.h 2005-03-11 14:51:08 -07:00
+++ b/arch/ppc/platforms/chestnut.h 2005-03-11 14:51:08 -07:00
@@ -24,11 +24,12 @@
* implement at 0xf1000000 only at this time
*
* 0xfff00000-0xffffffff - 8 Flash
+ * 0xffe00000-0xffefffff - BOOT SRAM
* 0xffd00000-0xffd00004 - CPLD
* 0xffc00000-0xffc0000f - UART
* 0xffb00000-0xffb07fff - FRAM
* 0xffa00000-0xffafffff - *** HOLE ***
- * 0xff900000-0xff9fffff - MV64460 Integrated SRAM
+ * 0xff800000-0xff9fffff - MV64460 Integrated SRAM
* 0xfe000000-0xff8fffff - *** HOLE ***
* 0xfc000000-0xfdffffff - 32bit Flash
* 0xf1010000-0xfbffffff - *** HOLE ***
@@ -49,9 +50,7 @@
#define CHESTNUT_UART_SIZE_ACTUAL 16
#define CHESTNUT_FRAM_BASE 0xffb00000
#define CHESTNUT_FRAM_SIZE_ACTUAL (32*1024)
-#define CHESTNUT_BRIDGE_REG_BASE 0xf1000000
-#define CHESTNUT_INTERNAL_SRAM_BASE 0xff900000
-#define CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL (256*1024)
+#define CHESTNUT_INTERNAL_SRAM_BASE 0xff800000
#define CHESTNUT_32BIT_BASE 0xfc000000
#define CHESTNUT_32BIT_SIZE (32*1024*1024)
@@ -65,14 +64,16 @@
CHESTNUT_UART_SIZE_ACTUAL)
#define CHESTNUT_FRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
CHESTNUT_FRAM_SIZE_ACTUAL)
-#define CHESTNUT_INTERNAL_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
- CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL)
#define CHESTNUT_BUS_SPEED 200000000
#define CHESTNUT_PIBS_DATABASE 0xf0000 /* from PIBS src code */
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT0 0x243c
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT1 0x283c
+#define KATANA_ETH0_PHY_ADDR 12
+#define KATANA_ETH1_PHY_ADDR 11
+#define KATANA_ETH2_PHY_ADDR 4
+
+#define CHESTNUT_ETH_TX_QUEUE_SIZE 800
+#define CHESTNUT_ETH_RX_QUEUE_SIZE 400
/*
* PCI windows
@@ -89,17 +90,17 @@
/*
* Board-specific IRQ info
*/
-#define CHESTNUT_PCI_SLOT0_IRQ 64+31
-#define CHESTNUT_PCI_SLOT1_IRQ 64+30
-#define CHESTNUT_PCI_SLOT2_IRQ 64+29
-#define CHESTNUT_PCI_SLOT3_IRQ 64+28
+#define CHESTNUT_PCI_SLOT0_IRQ (64 + 31)
+#define CHESTNUT_PCI_SLOT1_IRQ (64 + 30)
+#define CHESTNUT_PCI_SLOT2_IRQ (64 + 29)
+#define CHESTNUT_PCI_SLOT3_IRQ (64 + 28)
/* serial port definitions */
-#define CHESTNUT_UART0_IO_BASE CHESTNUT_UART_BASE+8
+#define CHESTNUT_UART0_IO_BASE (CHESTNUT_UART_BASE + 8)
#define CHESTNUT_UART1_IO_BASE CHESTNUT_UART_BASE
-#define UART0_INT 64+25
-#define UART1_INT 64+26
+#define UART0_INT (64 + 25)
+#define UART1_INT (64 + 26)
#ifdef CONFIG_SERIAL_MANY_PORTS
#define RS_TABLE_SIZE 64
@@ -108,7 +109,7 @@
#endif
/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
-#define BASE_BAUD ( 3686400 / 16 )
+#define BASE_BAUD (3686400 / 16)
#ifdef CONFIG_SERIAL_DETECT_IRQ
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
^ permalink raw reply
* Re: [PATCH 2.6.12] PPC32: Update chestnut platform files
From: Josh Boyer @ 2005-03-12 0:09 UTC (permalink / raw)
To: Mark A. Greer; +Cc: akpm, Embedded PPC Linux list
In-Reply-To: <4232162D.5000100@mvista.com>
On Fri, 2005-03-11 at 15:05 -0700, Mark A. Greer wrote:
> Update Chestnut platform files.
>
> - Set up mtd partition from arch-specific platform file and remove
> obsoleted mtd map.
Could you forward this portion of the patch to the MTD maintainer? That
way it has less of a chance getting re-added to -mm when Andrew grabs
the latest MTD bitkeeper tree.
thx,
josh
^ permalink raw reply
* [PATCH] MPC52xx updates (2nd take) : cleanups + PCI
From: Sylvain Munaut @ 2005-03-11 23:17 UTC (permalink / raw)
To: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 480 bytes --]
Ok, second try.
I've included the remarks alread done (the C99 init and the missing
space for " MPC52xx ")
They can be found included (correctly this time I hope), and on-line as well
Bitkeeper tree :
bk://tnt.bkbits.net/linux-2.5-mpc52xx-pending
Patch download :
http://www.246tnt.com/mpc52xx/linux-2.5-mpc52xx-pending-20050311-sparsecleanup.diff
http://www.246tnt.com/mpc52xx/linux-2.5-mpc52xx-pending-20050311-pci.diff
That'll be hopefully enough ...
Sylvain
[-- Attachment #2: linux-2.5-mpc52xx-pending-20050311-pci.diff --]
[-- Type: text/x-patch, Size: 16352 bytes --]
# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
# 2005/03/11 23:49:52+01:00 tnt@246tNt.com
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# Note that this support has "known" problem but theses
# are believed to be due to hardware issues.
#
#
# Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
#
# arch/ppc/syslib/mpc52xx_pci.h
# 2005/03/11 23:49:35+01:00 tnt@246tNt.com +139 -0
#
# arch/ppc/syslib/mpc52xx_pci.h
# 2005/03/11 23:49:35+01:00 tnt@246tNt.com +0 -0
# BitKeeper file /home/tnt/musicbox/kernel/linux-2.5-mpc52xx-pending/arch/ppc/syslib/mpc52xx_pci.h
#
# arch/ppc/syslib/mpc52xx_pci.c
# 2005/03/11 23:49:34+01:00 tnt@246tNt.com +235 -0
#
# include/linux/pci_ids.h
# 2005/03/11 23:49:34+01:00 tnt@246tNt.com +1 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# include/asm-ppc/mpc52xx.h
# 2005/03/11 23:49:34+01:00 tnt@246tNt.com +2 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/syslib/mpc52xx_pci.c
# 2005/03/11 23:49:34+01:00 tnt@246tNt.com +0 -0
# BitKeeper file /home/tnt/musicbox/kernel/linux-2.5-mpc52xx-pending/arch/ppc/syslib/mpc52xx_pci.c
#
# arch/ppc/syslib/Makefile
# 2005/03/11 23:49:34+01:00 tnt@246tNt.com +3 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/platforms/lite5200.c
# 2005/03/11 23:49:34+01:00 tnt@246tNt.com +33 -3
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/Kconfig
# 2005/03/11 23:49:34+01:00 tnt@246tNt.com +1 -1
# ppc32: Add PCI bus support for Freescale MPC52xx
#
diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig 2005-03-12 00:02:18 +01:00
+++ b/arch/ppc/Kconfig 2005-03-12 00:02:18 +01:00
@@ -1097,7 +1097,7 @@
bool
config PCI
- bool "PCI support" if 40x || CPM2 || 83xx || 85xx
+ bool "PCI support" if 40x || CPM2 || 83xx || 85xx || PPC_MPC52xx
default y if !40x && !CPM2 && !8xx && !APUS && !83xx && !85xx
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
default PCI_QSPAN if !4xx && !CPM2 && 8xx
diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
--- a/arch/ppc/platforms/lite5200.c 2005-03-12 00:02:18 +01:00
+++ b/arch/ppc/platforms/lite5200.c 2005-03-12 00:02:18 +01:00
@@ -35,6 +35,8 @@
#include <asm/ocp.h>
#include <asm/mpc52xx.h>
+#include <syslib/mpc52xx_pci.h>
+
extern int powersave_nap;
@@ -79,21 +81,39 @@
return 0;
}
+#ifdef CONFIG_PCI
+static int
+lite5200_map_irq(struct pci_dev *dev, unsigned char idsel,
+ unsigned char pin) {
+ return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1;
+}
+#endif
+
static void __init
lite5200_setup_cpu(void)
{
+ struct mpc52xx_xlb __iomem *xlb;
struct mpc52xx_intr __iomem *intr;
u32 intr_ctrl;
/* Map zones */
+ xlb = ioremap(MPC52xx_XLB,sizeof(struct mpc52xx_xlb));
intr = ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
- if (!intr) {
- printk("lite5200.c: Error while mapping INTR during lite5200_setup_cpu\n");
+ if (!xlb || !intr) {
+ printk("lite5200.c: Error while mapping XLB/INTR during lite5200_setup_cpu\n");
goto unmap_regs;
}
+ /* Configure the XLB Arbiter */
+ out_be32(&xlb->master_pri_enable, 0xff);
+ out_be32(&xlb->master_priority, 0x11111111);
+
+ /* Enable ram snooping for 1GB window */
+ out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_SNOOP);
+ out_be32(&xlb->snoop_window, MPC52xx_PCI_TARGET_MEM | 0x1d);
+
/* IRQ[0-3] setup : IRQ0 - Level Active Low */
/* IRQ[1-3] - Level Active High */
intr_ctrl = in_be32(&intr->ctrl);
@@ -103,6 +123,7 @@
/* Unmap reg zone */
unmap_regs:
+ if (xlb) iounmap(xlb);
if (intr) iounmap(intr);
}
@@ -114,6 +135,11 @@
/* CPU & Port mux setup */
lite5200_setup_cpu();
+
+#ifdef CONFIG_PCI
+ /* PCI Bridge setup */
+ mpc52xx_find_bridges();
+#endif
}
void __init
@@ -152,7 +178,7 @@
/* BAT setup */
mpc52xx_set_bat();
- /* No ISA bus AFAIK */
+ /* No ISA bus by default */
isa_io_base = 0;
isa_mem_base = 0;
@@ -165,6 +191,10 @@
ppc_md.show_percpuinfo = NULL;
ppc_md.init_IRQ = mpc52xx_init_irq;
ppc_md.get_irq = mpc52xx_get_irq;
+
+#ifdef CONFIG_PCI
+ ppc_md.pci_map_irq = lite5200_map_irq;
+#endif
ppc_md.find_end_of_memory = mpc52xx_find_end_of_memory;
ppc_md.setup_io_mappings = mpc52xx_map_io;
diff -Nru a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile 2005-03-12 00:02:18 +01:00
+++ b/arch/ppc/syslib/Makefile 2005-03-12 00:02:18 +01:00
@@ -106,3 +106,6 @@
endif
obj-$(CONFIG_MPC8555_CDS) += todc_time.o
obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o
+ifeq ($(CONFIG_PPC_MPC52xx),y)
+obj-$(CONFIG_PCI) += mpc52xx_pci.o
+endif
diff -Nru a/arch/ppc/syslib/mpc52xx_pci.c b/arch/ppc/syslib/mpc52xx_pci.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/mpc52xx_pci.c 2005-03-12 00:02:18 +01:00
@@ -0,0 +1,235 @@
+/*
+ * arch/ppc/syslib/mpc52xx_pci.c
+ *
+ * PCI code for the Freescale MPC52xx embedded CPU.
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+
+#include <asm/pci.h>
+
+#include <asm/mpc52xx.h>
+#include "mpc52xx_pci.h"
+
+#include <asm/delay.h>
+
+
+static int
+mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ u32 value;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ out_be32(hose->cfg_addr,
+ (1 << 31) |
+ ((bus->number - hose->bus_offset) << 16) |
+ (devfn << 8) |
+ (offset & 0xfc));
+
+ value = in_le32(hose->cfg_data);
+
+ if (len != 4) {
+ value >>= ((offset & 0x3) << 3);
+ value &= 0xffffffff >> (32 - (len << 3));
+ }
+
+ *val = value;
+
+ out_be32(hose->cfg_addr, 0);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ u32 value, mask;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ out_be32(hose->cfg_addr,
+ (1 << 31) |
+ ((bus->number - hose->bus_offset) << 16) |
+ (devfn << 8) |
+ (offset & 0xfc));
+
+ if (len != 4) {
+ value = in_le32(hose->cfg_data);
+
+ offset = (offset & 0x3) << 3;
+ mask = (0xffffffff >> (32 - (len << 3)));
+ mask <<= offset;
+
+ value &= ~mask;
+ val = value | ((val << offset) & mask);
+ }
+
+ out_le32(hose->cfg_data, val);
+
+ out_be32(hose->cfg_addr, 0);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops mpc52xx_pci_ops = {
+ .read = mpc52xx_pci_read_config,
+ .write = mpc52xx_pci_write_config
+};
+
+
+static void __init
+mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
+{
+
+ /* Setup control regs */
+ /* Nothing to do afaik */
+
+ /* Setup windows */
+ out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
+ MPC52xx_PCI_MEM_START + MPC52xx_PCI_MEM_OFFSET,
+ MPC52xx_PCI_MEM_START,
+ MPC52xx_PCI_MEM_SIZE ));
+
+ out_be32(&pci_regs->iw1btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
+ MPC52xx_PCI_MMIO_START + MPC52xx_PCI_MEM_OFFSET,
+ MPC52xx_PCI_MMIO_START,
+ MPC52xx_PCI_MMIO_SIZE ));
+
+ out_be32(&pci_regs->iw2btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
+ MPC52xx_PCI_IO_BASE,
+ MPC52xx_PCI_IO_START,
+ MPC52xx_PCI_IO_SIZE ));
+
+ out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(
+ ( MPC52xx_PCI_IWCR_ENABLE | /* iw0btar */
+ MPC52xx_PCI_IWCR_READ_MULTI |
+ MPC52xx_PCI_IWCR_MEM ),
+ ( MPC52xx_PCI_IWCR_ENABLE | /* iw1btar */
+ MPC52xx_PCI_IWCR_READ |
+ MPC52xx_PCI_IWCR_MEM ),
+ ( MPC52xx_PCI_IWCR_ENABLE | /* iw2btar */
+ MPC52xx_PCI_IWCR_IO )
+ ));
+
+
+ out_be32(&pci_regs->tbatr0,
+ MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO );
+ out_be32(&pci_regs->tbatr1,
+ MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
+
+ out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
+
+ /* Reset the exteral bus ( internal PCI controller is NOT resetted ) */
+ /* Not necessary and can be a bad thing if for example the bootloader
+ is displaying a splash screen or ... Just left here for
+ documentation purpose if anyone need it */
+#if 0
+ u32 tmp;
+ tmp = in_be32(&pci_regs->gscr);
+ out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
+ udelay(50);
+ out_be32(&pci_regs->gscr, tmp);
+#endif
+}
+
+static void __init
+mpc52xx_pci_fixup_resources(struct pci_dev *dev)
+{
+ int i;
+
+ /* We don't rely on boot loader for PCI and resets all
+ devices */
+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+ struct resource *res = &dev->resource[i];
+ if (res->end > res->start) { /* Only valid resources */
+ res->end -= res->start;
+ res->start = 0;
+ res->flags |= IORESOURCE_UNSET;
+ }
+ }
+
+ /* The PCI Host bridge of MPC52xx has a prefetch memory resource
+ fixed to 1Gb. Doesn't fit in the resource system so we remove it */
+ if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
+ (dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200) ) {
+ struct resource *res = &dev->resource[1];
+ res->start = res->end = res->flags = 0;
+ }
+}
+
+void __init
+mpc52xx_find_bridges(void)
+{
+ struct mpc52xx_pci __iomem *pci_regs;
+ struct pci_controller *hose;
+
+ pci_assign_all_busses = 1;
+
+ pci_regs = ioremap(MPC52xx_PCI, sizeof(struct mpc52xx_pci));
+ if (!pci_regs)
+ return;
+
+ hose = pcibios_alloc_controller();
+ if (!hose) {
+ iounmap(pci_regs);
+ return;
+ }
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+ hose->bus_offset = 0;
+ hose->ops = &mpc52xx_pci_ops;
+
+ mpc52xx_pci_setup(pci_regs);
+
+ hose->pci_mem_offset = MPC52xx_PCI_MEM_OFFSET;
+
+ isa_io_base =
+ (unsigned long) ioremap(MPC52xx_PCI_IO_BASE,
+ MPC52xx_PCI_IO_SIZE);
+ hose->io_base_virt = (void *) isa_io_base;
+
+ hose->cfg_addr = &pci_regs->car;
+ hose->cfg_data = (void __iomem *) isa_io_base;
+
+ /* Setup resources */
+ pci_init_resource(&hose->mem_resources[0],
+ MPC52xx_PCI_MEM_START,
+ MPC52xx_PCI_MEM_STOP,
+ IORESOURCE_MEM|IORESOURCE_PREFETCH,
+ "PCI prefetchable memory");
+
+ pci_init_resource(&hose->mem_resources[1],
+ MPC52xx_PCI_MMIO_START,
+ MPC52xx_PCI_MMIO_STOP,
+ IORESOURCE_MEM,
+ "PCI memory");
+
+ pci_init_resource(&hose->io_resource,
+ MPC52xx_PCI_IO_START,
+ MPC52xx_PCI_IO_STOP,
+ IORESOURCE_IO,
+ "PCI I/O");
+
+}
diff -Nru a/arch/ppc/syslib/mpc52xx_pci.h b/arch/ppc/syslib/mpc52xx_pci.h
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/mpc52xx_pci.h 2005-03-12 00:02:18 +01:00
@@ -0,0 +1,139 @@
+/*
+ * arch/ppc/syslib/mpc52xx_pci.h
+ *
+ * PCI Include file the Freescale MPC52xx embedded cpu chips
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Inspired from code written by Dale Farnsworth <dfarnsworth@mvista.com>
+ * for the 2.4 kernel.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __SYSLIB_MPC52xx_PCI_H__
+#define __SYSLIB_MPC52xx_PCI_H__
+
+/* ======================================================================== */
+/* PCI windows config */
+/* ======================================================================== */
+
+/*
+ * Master windows : MPC52xx -> PCI
+ *
+ * 0x80000000 -> 0x9FFFFFFF PCI Mem prefetchable IW0BTAR
+ * 0xA0000000 -> 0xAFFFFFFF PCI Mem IW1BTAR
+ * 0xB0000000 -> 0xB0FFFFFF PCI IO IW2BTAR
+ *
+ * Slave windows : PCI -> MPC52xx
+ *
+ * 0xF0000000 -> 0xF003FFFF MPC52xx MBAR TBATR0
+ * 0x00000000 -> 0x3FFFFFFF MPC52xx local memory TBATR1
+ */
+
+#define MPC52xx_PCI_MEM_OFFSET 0x00000000 /* Offset for MEM MMIO */
+
+#define MPC52xx_PCI_MEM_START 0x80000000
+#define MPC52xx_PCI_MEM_SIZE 0x20000000
+#define MPC52xx_PCI_MEM_STOP (MPC52xx_PCI_MEM_START+MPC52xx_PCI_MEM_SIZE-1)
+
+#define MPC52xx_PCI_MMIO_START 0xa0000000
+#define MPC52xx_PCI_MMIO_SIZE 0x10000000
+#define MPC52xx_PCI_MMIO_STOP (MPC52xx_PCI_MMIO_START+MPC52xx_PCI_MMIO_SIZE-1)
+
+#define MPC52xx_PCI_IO_BASE 0xb0000000
+
+#define MPC52xx_PCI_IO_START 0x00000000
+#define MPC52xx_PCI_IO_SIZE 0x01000000
+#define MPC52xx_PCI_IO_STOP (MPC52xx_PCI_IO_START+MPC52xx_PCI_IO_SIZE-1)
+
+
+#define MPC52xx_PCI_TARGET_IO MPC52xx_MBAR
+#define MPC52xx_PCI_TARGET_MEM 0x00000000
+
+
+/* ======================================================================== */
+/* Structures mapping & Defines for PCI Unit */
+/* ======================================================================== */
+
+#define MPC52xx_PCI_GSCR_BM 0x40000000
+#define MPC52xx_PCI_GSCR_PE 0x20000000
+#define MPC52xx_PCI_GSCR_SE 0x10000000
+#define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000
+#define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24
+#define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000
+#define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16
+#define MPC52xx_PCI_GSCR_BME 0x00004000
+#define MPC52xx_PCI_GSCR_PEE 0x00002000
+#define MPC52xx_PCI_GSCR_SEE 0x00001000
+#define MPC52xx_PCI_GSCR_PR 0x00000001
+
+
+#define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \
+ ( ( (proc_ad) & 0xff000000 ) | \
+ ( (((size) - 1) >> 8) & 0x00ff0000 ) | \
+ ( ((pci_ad) >> 16) & 0x0000ff00 ) )
+
+#define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \
+ ((win1) << 16) | \
+ ((win2) << 8))
+
+#define MPC52xx_PCI_IWCR_DISABLE 0x0
+#define MPC52xx_PCI_IWCR_ENABLE 0x1
+#define MPC52xx_PCI_IWCR_READ 0x0
+#define MPC52xx_PCI_IWCR_READ_LINE 0x2
+#define MPC52xx_PCI_IWCR_READ_MULTI 0x4
+#define MPC52xx_PCI_IWCR_MEM 0x0
+#define MPC52xx_PCI_IWCR_IO 0x8
+
+#define MPC52xx_PCI_TCR_P 0x01000000
+#define MPC52xx_PCI_TCR_LD 0x00010000
+
+#define MPC52xx_PCI_TBATR_DISABLE 0x0
+#define MPC52xx_PCI_TBATR_ENABLE 0x1
+
+
+#ifndef __ASSEMBLY__
+
+struct mpc52xx_pci {
+ u32 idr; /* PCI + 0x00 */
+ u32 scr; /* PCI + 0x04 */
+ u32 ccrir; /* PCI + 0x08 */
+ u32 cr1; /* PCI + 0x0C */
+ u32 bar0; /* PCI + 0x10 */
+ u32 bar1; /* PCI + 0x14 */
+ u8 reserved1[16]; /* PCI + 0x18 */
+ u32 ccpr; /* PCI + 0x28 */
+ u32 sid; /* PCI + 0x2C */
+ u32 erbar; /* PCI + 0x30 */
+ u32 cpr; /* PCI + 0x34 */
+ u8 reserved2[4]; /* PCI + 0x38 */
+ u32 cr2; /* PCI + 0x3C */
+ u8 reserved3[32]; /* PCI + 0x40 */
+ u32 gscr; /* PCI + 0x60 */
+ u32 tbatr0; /* PCI + 0x64 */
+ u32 tbatr1; /* PCI + 0x68 */
+ u32 tcr; /* PCI + 0x6C */
+ u32 iw0btar; /* PCI + 0x70 */
+ u32 iw1btar; /* PCI + 0x74 */
+ u32 iw2btar; /* PCI + 0x78 */
+ u8 reserved4[4]; /* PCI + 0x7C */
+ u32 iwcr; /* PCI + 0x80 */
+ u32 icr; /* PCI + 0x84 */
+ u32 isr; /* PCI + 0x88 */
+ u32 arb; /* PCI + 0x8C */
+ u8 reserved5[104]; /* PCI + 0x90 */
+ u32 car; /* PCI + 0xF8 */
+ u8 reserved6[4]; /* PCI + 0xFC */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* __SYSLIB_MPC52xx_PCI_H__ */
diff -Nru a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
--- a/include/asm-ppc/mpc52xx.h 2005-03-12 00:02:18 +01:00
+++ b/include/asm-ppc/mpc52xx.h 2005-03-12 00:02:18 +01:00
@@ -393,6 +393,8 @@
extern void mpc52xx_calibrate_decr(void);
extern void mpc52xx_add_board_devices(struct ocp_def board_ocp[]);
+extern void mpc52xx_find_bridges(void);
+
#endif /* __ASSEMBLY__ */
diff -Nru a/include/linux/pci_ids.h b/include/linux/pci_ids.h
--- a/include/linux/pci_ids.h 2005-03-12 00:02:18 +01:00
+++ b/include/linux/pci_ids.h 2005-03-12 00:02:18 +01:00
@@ -807,6 +807,7 @@
#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806
#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803
#define PCI_VENDOR_ID_PROMISE 0x105a
#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
[-- Attachment #3: linux-2.5-mpc52xx-pending-20050311-sparsecleanup.diff --]
[-- Type: text/x-patch, Size: 9865 bytes --]
# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
# 2005/03/11 23:47:54+01:00 tnt@246tNt.com
# ppc32: sparse clean ups for the Freescale MPC52xx related code
#
# Theses clean-ups are mainly missing __iomem qualifier,
# unnecessary (and 'wrong') casting, missing static.
#
#
# Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
#
# drivers/serial/mpc52xx_uart.c
# 2005/03/11 23:46:11+01:00 tnt@246tNt.com +6 -6
# ppc32: sparse clean ups for the Freescale MPC52xx related code
#
# arch/ppc/syslib/mpc52xx_setup.c
# 2005/03/11 23:46:11+01:00 tnt@246tNt.com +13 -13
# ppc32: sparse clean ups for the Freescale MPC52xx related code
#
# arch/ppc/syslib/mpc52xx_pic.c
# 2005/03/11 23:46:11+01:00 tnt@246tNt.com +9 -14
# ppc32: sparse clean ups for the Freescale MPC52xx related code
#
# arch/ppc/platforms/mpc5200.c
# 2005/03/11 23:46:11+01:00 tnt@246tNt.com +1 -1
# ppc32: sparse clean ups for the Freescale MPC52xx related code
#
# arch/ppc/platforms/lite5200.c
# 2005/03/11 23:46:11+01:00 tnt@246tNt.com +3 -4
# ppc32: sparse clean ups for the Freescale MPC52xx related code
#
# arch/ppc/boot/simple/mpc52xx_tty.c
# 2005/03/11 23:46:11+01:00 tnt@246tNt.com +7 -6
# ppc32: sparse clean ups for the Freescale MPC52xx related code
#
diff -Nru a/arch/ppc/boot/simple/mpc52xx_tty.c b/arch/ppc/boot/simple/mpc52xx_tty.c
--- a/arch/ppc/boot/simple/mpc52xx_tty.c 2005-03-12 00:01:44 +01:00
+++ b/arch/ppc/boot/simple/mpc52xx_tty.c 2005-03-12 00:01:44 +01:00
@@ -33,18 +33,19 @@
#error "MPC52xx_PF_CONSOLE_PORT not defined"
#endif
-static struct mpc52xx_psc *psc = (struct mpc52xx_psc *)MPC52xx_CONSOLE;
+static struct mpc52xx_psc __iomem *psc =
+ (struct mpc52xx_psc __iomem *) MPC52xx_CONSOLE;
/* The decrementer counts at the system bus clock frequency
* divided by four. The most accurate time base is connected to the
* rtc. We read the decrementer change during one rtc tick (one second)
* and multiply by 4 to get the system bus clock frequency.
*/
-int
+static int
mpc52xx_ipbfreq(void)
{
- struct mpc52xx_rtc *rtc = (struct mpc52xx_rtc*)MPC52xx_RTC;
- struct mpc52xx_cdm *cdm = (struct mpc52xx_cdm*)MPC52xx_CDM;
+ struct mpc52xx_rtc __iomem *rtc = (struct mpc52xx_rtc __iomem *)MPC52xx_RTC;
+ struct mpc52xx_cdm __iomem *cdm = (struct mpc52xx_cdm __iomem *)MPC52xx_CDM;
int current_time, previous_time;
int tbl_start, tbl_end;
int xlbfreq, ipbfreq;
@@ -67,7 +68,7 @@
unsigned long
serial_init(int ignored, void *ignored2)
{
- struct mpc52xx_gpio *gpio = (struct mpc52xx_gpio *)MPC52xx_GPIO;
+ struct mpc52xx_gpio __iomem *gpio = (struct mpc52xx_gpio __iomem *)MPC52xx_GPIO;
int divisor;
int mode1;
int mode2;
@@ -117,7 +118,7 @@
void
serial_putc(void *ignored, const char c)
{
- serial_init(0, 0);
+ serial_init(0, NULL);
while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP)) ;
out_8(&psc->mpc52xx_psc_buffer_8, c);
diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
--- a/arch/ppc/platforms/lite5200.c 2005-03-12 00:01:44 +01:00
+++ b/arch/ppc/platforms/lite5200.c 2005-03-12 00:01:44 +01:00
@@ -53,7 +53,7 @@
* driver ( eg drivers/serial/mpc52xx_uart.c for the PSC in uart mode )
*/
-struct ocp_def board_ocp[] = {
+static struct ocp_def board_ocp[] = {
{
.vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_PSC_UART,
@@ -82,13 +82,12 @@
static void __init
lite5200_setup_cpu(void)
{
- struct mpc52xx_intr *intr;
+ struct mpc52xx_intr __iomem *intr;
u32 intr_ctrl;
/* Map zones */
- intr = (struct mpc52xx_intr *)
- ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
+ intr = ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
if (!intr) {
printk("lite5200.c: Error while mapping INTR during lite5200_setup_cpu\n");
diff -Nru a/arch/ppc/platforms/mpc5200.c b/arch/ppc/platforms/mpc5200.c
--- a/arch/ppc/platforms/mpc5200.c 2005-03-12 00:01:44 +01:00
+++ b/arch/ppc/platforms/mpc5200.c 2005-03-12 00:01:44 +01:00
@@ -17,7 +17,7 @@
#include <asm/mpc52xx.h>
-struct ocp_fs_i2c_data mpc5200_i2c_def = {
+static struct ocp_fs_i2c_data mpc5200_i2c_def = {
.flags = FS_I2C_CLOCK_5200,
};
diff -Nru a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c
--- a/arch/ppc/syslib/mpc52xx_pic.c 2005-03-12 00:01:44 +01:00
+++ b/arch/ppc/syslib/mpc52xx_pic.c 2005-03-12 00:01:44 +01:00
@@ -33,8 +33,8 @@
#include <asm/mpc52xx.h>
-static struct mpc52xx_intr *intr;
-static struct mpc52xx_sdma *sdma;
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
static void
mpc52xx_ic_disable(unsigned int irq)
@@ -166,14 +166,11 @@
}
static struct hw_interrupt_type mpc52xx_ic = {
- "MPC52xx",
- NULL, /* startup(irq) */
- NULL, /* shutdown(irq) */
- mpc52xx_ic_enable, /* enable(irq) */
- mpc52xx_ic_disable, /* disable(irq) */
- mpc52xx_ic_disable_and_ack, /* disable_and_ack(irq) */
- mpc52xx_ic_end, /* end(irq) */
- 0 /* set_affinity(irq, cpumask) SMP. */
+ .typename = " MPC52xx ",
+ .enable = mpc52xx_ic_enable,
+ .disable = mpc52xx_ic_disable,
+ .ack = mpc52xx_ic_disable_and_ack,
+ .end = mpc52xx_ic_end,
};
void __init
@@ -183,10 +180,8 @@
u32 intr_ctrl;
/* Remap the necessary zones */
- intr = (struct mpc52xx_intr *)
- ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
- sdma = (struct mpc52xx_sdma *)
- ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
+ intr = ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
+ sdma = ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
if ((intr==NULL) || (sdma==NULL))
panic("Can't ioremap PIC/SDMA register for init_irq !");
diff -Nru a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
--- a/arch/ppc/syslib/mpc52xx_setup.c 2005-03-12 00:01:44 +01:00
+++ b/arch/ppc/syslib/mpc52xx_setup.c 2005-03-12 00:01:44 +01:00
@@ -39,7 +39,8 @@
void
mpc52xx_restart(char *cmd)
{
- struct mpc52xx_gpt* gpt0 = (struct mpc52xx_gpt*) MPC52xx_GPTx(0);
+ struct mpc52xx_gpt __iomem *gpt0 =
+ (struct mpc52xx_gpt __iomem *) MPC52xx_GPTx(0);
local_irq_disable();
@@ -102,7 +103,7 @@
#endif
static void
-mpc52xx_psc_putc(struct mpc52xx_psc * psc, unsigned char c)
+mpc52xx_psc_putc(struct mpc52xx_psc __iomem *psc, unsigned char c)
{
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY));
@@ -112,8 +113,9 @@
void
mpc52xx_progress(char *s, unsigned short hex)
{
- struct mpc52xx_psc *psc = (struct mpc52xx_psc *)MPC52xx_CONSOLE;
char c;
+ struct mpc52xx_psc __iomem *psc =
+ (struct mpc52xx_psc __iomem *)MPC52xx_CONSOLE;
while ((c = *s++) != 0) {
if (c == '\n')
@@ -138,11 +140,11 @@
* else get size from sdram config registers
*/
if (ramsize == 0) {
- struct mpc52xx_mmap_ctl *mmap_ctl;
+ struct mpc52xx_mmap_ctl __iomem *mmap_ctl;
u32 sdram_config_0, sdram_config_1;
/* Temp BAT2 mapping active when this is called ! */
- mmap_ctl = (struct mpc52xx_mmap_ctl*) MPC52xx_MMAP_CTL;
+ mmap_ctl = (struct mpc52xx_mmap_ctl __iomem *) MPC52xx_MMAP_CTL;
sdram_config_0 = in_be32(&mmap_ctl->sdram0);
sdram_config_1 = in_be32(&mmap_ctl->sdram1);
@@ -169,13 +171,11 @@
/* if bootloader didn't pass bus frequencies, calculate them */
if (xlbfreq == 0) {
/* Get RTC & Clock manager modules */
- struct mpc52xx_rtc *rtc;
- struct mpc52xx_cdm *cdm;
+ struct mpc52xx_rtc __iomem *rtc;
+ struct mpc52xx_cdm __iomem *cdm;
- rtc = (struct mpc52xx_rtc*)
- ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
- cdm = (struct mpc52xx_cdm*)
- ioremap(MPC52xx_CDM, sizeof(struct mpc52xx_cdm));
+ rtc = ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
+ cdm = ioremap(MPC52xx_CDM, sizeof(struct mpc52xx_cdm));
if ((rtc==NULL) || (cdm==NULL))
panic("Can't ioremap RTC/CDM while computing bus freq");
@@ -212,8 +212,8 @@
__res.bi_pcifreq = pcifreq;
/* Release mapping */
- iounmap((void*)rtc);
- iounmap((void*)cdm);
+ iounmap(rtc);
+ iounmap(cdm);
}
divisor = 4;
diff -Nru a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
--- a/drivers/serial/mpc52xx_uart.c 2005-03-12 00:01:44 +01:00
+++ b/drivers/serial/mpc52xx_uart.c 2005-03-12 00:01:44 +01:00
@@ -86,7 +86,7 @@
* the console_init
*/
-#define PSC(port) ((struct mpc52xx_psc *)((port)->membase))
+#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
/* Forward declaration of the interruption handling routine */
@@ -190,7 +190,7 @@
static int
mpc52xx_uart_startup(struct uart_port *port)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
/* Reset/activate the port, clear and enable interrupts */
out_8(&psc->command,MPC52xx_PSC_RST_RX);
@@ -217,7 +217,7 @@
static void
mpc52xx_uart_shutdown(struct uart_port *port)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
/* Shut down the port, interrupt and all */
out_8(&psc->command,MPC52xx_PSC_RST_RX);
@@ -231,7 +231,7 @@
mpc52xx_uart_set_termios(struct uart_port *port, struct termios *new,
struct termios *old)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
unsigned long flags;
unsigned char mr1, mr2;
unsigned short ctr;
@@ -562,7 +562,7 @@
mpc52xx_console_get_options(struct uart_port *port,
int *baud, int *parity, int *bits, int *flow)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
unsigned char mr1;
/* Read the mode registers */
@@ -592,7 +592,7 @@
mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
{
struct uart_port *port = &mpc52xx_uart_ports[co->index];
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
unsigned int i, j;
/* Disable interrupts */
^ permalink raw reply
* Re: boot time scheduling while atomic
From: Takeharu KATO @ 2005-03-11 22:21 UTC (permalink / raw)
To: Joerg Dorchain; +Cc: linuxppc-dev
In-Reply-To: <20050310072803.GR4017@Redstar.dorchain.net>
Hi
>
> I came to the same idea. This explains as well why the i386 party does
> not notice the effect, as their first interrupt happen later (different
> HZ value)
>
FYI, i386 party's kernel_thread function calls do_fork directly,
however, do_fork is called via syscall trap(clone syscall) in powerpc.
So, this difference may be taken place.
IMHO, from this point of view, the real fix for this problem is change
the way to implement kernel_thread function of PowerPC like as other
architecture does.
Regards,
--
Takeharu KATO
^ permalink raw reply
* [PATCH] ppc32: emulate load/store string instructions
From: Kumar Gala @ 2005-03-11 22:12 UTC (permalink / raw)
To: Andrew Morton; +Cc: linux-kernel, linuxppc-embedded
Andrew,
Some Book-E implementations (e500) do not implement the userland
load/store string instructions. Apparently these instructions are rather
painful to implement do to the fact that they modify the destination
register differently then ever other instruction. Matt did the inital
work some time ago, and I finally got around to cleaning it up.
Signed-off-by: Matt McClintock
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
--- a/arch/ppc/kernel/traps.c 2005-03-11 15:07:28 -06:00
+++ b/arch/ppc/kernel/traps.c 2005-03-11 15:07:28 -06:00
@@ -389,6 +389,87 @@
#define INST_MCRXR 0x7c000400
#define INST_MCRXR_MASK 0x7c0007fe
+#define INST_STRING 0x7c00042a
+#define INST_STRING_MASK 0x7c0007fe
+#define INST_STRING_GEN_MASK 0x7c00067e
+#define INST_LSWI 0x7c0004aa
+#define INST_LSWX 0x7c00042a
+#define INST_STSWI 0x7c0005aa
+#define INST_STSWX 0x7c00052a
+
+static int emulate_string_inst(struct pt_regs *regs, u32 instword)
+{
+ u8 rT = (instword >> 21) & 0x1f;
+ u8 rA = (instword >> 16) & 0x1f;
+ u8 NB_RB = (instword >> 11) & 0x1f;
+ u32 num_bytes;
+ u32 EA;
+ int pos = 0;
+
+ /* Early out if we are an invalid form of lswx */
+ if ((instword & INST_STRING_MASK) == INST_LSWX)
+ if ((rA >= rT) || (NB_RB >= rT) || (rT == rA) || (rT == NB_RB))
+ return -EINVAL;
+
+ /* Early out if we are an invalid form of lswi */
+ if ((instword & INST_STRING_MASK) == INST_LSWX)
+ if ((rA >= rT) || (rT == rA))
+ return -EINVAL;
+
+ EA = (rA == 0) ? 0 : regs->gpr[rA];
+
+ switch (instword & INST_STRING_MASK) {
+ case INST_LSWX:
+ case INST_STSWX:
+ EA += NB_RB;
+ num_bytes = regs->xer & 0x7f;
+ break;
+ case INST_LSWI:
+ case INST_STSWI:
+ num_bytes = (NB_RB == 0) ? 32 : NB_RB;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ while (num_bytes != 0)
+ {
+ u8 val;
+ u32 shift = 8 * (3 - (pos & 0x3));
+
+ switch ((instword & INST_STRING_MASK)) {
+ case INST_LSWX:
+ case INST_LSWI:
+ if (get_user(val, (u8 __user *)EA))
+ return -EFAULT;
+ /* first time updating this reg,
+ * zero it out */
+ if (pos == 0)
+ regs->gpr[rT] = 0;
+ regs->gpr[rT] |= val << shift;
+ break;
+ case INST_STSWI:
+ case INST_STSWX:
+ val = regs->gpr[rT] >> shift;
+ if (put_user(val, (u8 __user *)EA))
+ return -EFAULT;
+ break;
+ }
+ /* move EA to next address */
+ EA += 1;
+ num_bytes--;
+
+ /* manage our position within the register */
+ if (++pos == 4) {
+ pos = 0;
+ if (++rT == 32)
+ rT = 0;
+ }
+ }
+
+ return 0;
+}
+
static int emulate_instruction(struct pt_regs *regs)
{
u32 instword;
@@ -422,6 +503,10 @@
regs->xer &= ~0xf0000000UL;
return 0;
}
+
+ /* Emulate load/store string insn. */
+ if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
+ return emulate_string_inst(regs, instword);
return -EINVAL;
}
^ permalink raw reply
* [PATCH 2.6.12] PPC32: Update chestnut platform files
From: Mark A. Greer @ 2005-03-11 22:05 UTC (permalink / raw)
To: akpm; +Cc: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 307 bytes --]
Update Chestnut platform files.
- Set up mtd partition from arch-specific platform file and remove
obsoleted mtd map.
- Update default config file (now enables embedded ethernet driver).
- Make some minor fixups.
- General code cleanup.
Please apply.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: chestnut.patch --]
[-- Type: text/plain, Size: 22857 bytes --]
diff -Nru a/arch/ppc/configs/chestnut_defconfig b/arch/ppc/configs/chestnut_defconfig
--- a/arch/ppc/configs/chestnut_defconfig 2005-03-11 14:51:08 -07:00
+++ b/arch/ppc/configs/chestnut_defconfig 2005-03-11 14:51:08 -07:00
@@ -1,11 +1,12 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.10-rc2
-# Tue Dec 7 16:02:09 2004
+# Linux kernel version: 2.6.11
+# Fri Mar 11 14:32:49 2005
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
@@ -35,6 +36,7 @@
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -44,6 +46,7 @@
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
#
# Loadable module support
@@ -78,7 +81,9 @@
#
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_APUS is not set
+# CONFIG_KATANA is not set
# CONFIG_WILLOW is not set
+# CONFIG_CPCI690 is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
CONFIG_CHESTNUT=y
@@ -91,6 +96,7 @@
# CONFIG_PRPMC750 is not set
# CONFIG_PRPMC800 is not set
# CONFIG_SANDPOINT is not set
+# CONFIG_RADSTONE_PPC7D is not set
# CONFIG_ADIR is not set
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
@@ -101,7 +107,9 @@
# CONFIG_RPX8260 is not set
# CONFIG_TQM8260 is not set
# CONFIG_ADS8272 is not set
+# CONFIG_PQ2FADS is not set
# CONFIG_LITE5200 is not set
+# CONFIG_MPC834x_SYS is not set
CONFIG_MV64360=y
CONFIG_MV64X60=y
@@ -128,6 +136,15 @@
CONFIG_PCI_NAMES=y
#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
# Advanced setup
#
CONFIG_ADVANCED_OPTIONS=y
@@ -154,6 +171,7 @@
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
#
# Memory Technology Devices (MTD)
@@ -181,6 +199,9 @@
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -198,13 +219,16 @@
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_CHESTNUT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xfc000000
+CONFIG_MTD_PHYSMAP_LEN=0x02000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
#
# Self-contained MTD device drivers
@@ -214,6 +238,7 @@
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
@@ -244,11 +269,13 @@
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
@@ -262,6 +289,7 @@
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
#
# ATA/ATAPI/MFM/RLL support
@@ -404,7 +432,6 @@
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
CONFIG_E100=y
-# CONFIG_E100_NAPI is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
@@ -429,6 +456,10 @@
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+# CONFIG_MV643XX_ETH_2 is not set
#
# Ethernet (10000 Mbit)
@@ -485,14 +516,6 @@
# CONFIG_INPUT_EVBUG is not set
#
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-
-#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
@@ -502,6 +525,13 @@
# CONFIG_INPUT_MISC is not set
#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+
+#
# Character devices
#
CONFIG_VT=y
@@ -520,6 +550,7 @@
#
# Non-8250 serial port support
#
+# CONFIG_SERIAL_MPSC is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
@@ -550,6 +581,11 @@
# CONFIG_RAW_DRIVER is not set
#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
# I2C support
#
# CONFIG_I2C is not set
@@ -606,6 +642,16 @@
# CONFIG_USB_GADGET is not set
#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
# File systems
#
CONFIG_EXT2_FS=y
@@ -614,6 +660,10 @@
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
@@ -664,6 +714,7 @@
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_FS_NOR_ECC is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
@@ -686,7 +737,6 @@
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
-# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -725,6 +775,7 @@
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_PRINTK_TIME is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
#
@@ -737,3 +788,7 @@
# Cryptographic options
#
# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -Nru a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c
--- a/arch/ppc/platforms/chestnut.c 2005-03-11 14:51:08 -07:00
+++ b/arch/ppc/platforms/chestnut.c 2005-03-11 14:51:08 -07:00
@@ -28,6 +28,7 @@
#include <linux/ide.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
+#include <linux/mtd/physmap.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
@@ -42,8 +43,8 @@
#include <asm/mv64x60.h>
#include <platforms/chestnut.h>
-static u32 boot_base; /* Virtual addr of 8bit boot */
-static u32 cpld_base; /* Virtual addr of CPLD Regs */
+static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
+static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
static mv64x60_handle_t bh;
@@ -65,7 +66,8 @@
*
****/
static void __init
-chestnut_calibrate_decr(void){
+chestnut_calibrate_decr(void)
+{
ulong freq;
freq = CHESTNUT_BUS_SPEED / 4;
@@ -75,8 +77,6 @@
tb_ticks_per_jiffy = freq / HZ;
tb_to_us = mulhwu_scale_factor(freq, 1000000);
-
- return;
}
static int
@@ -103,7 +103,7 @@
mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
MV64x60_TYPE_MV64460);
}
- return(mem_size);
+ return mem_size;
}
#if defined(CONFIG_SERIAL_8250)
@@ -155,7 +155,7 @@
};
const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return (PCI_IRQ_TABLE_LOOKUP);
+ return PCI_IRQ_TABLE_LOOKUP;
}
@@ -193,24 +193,30 @@
si.pci_0.pci_cmd_bits = 0;
si.pci_0.latency_timer = 0x80;
- si.window_preserve_mask_32_lo = CHESTNUT_PRESERVE_MASK;
-
for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
+#if defined(CONFIG_NOT_COHERENT_CACHE)
si.cpu_prot_options[i] = 0;
-#ifdef CONFIG_NOT_CACHE_COHERENT
- si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_NONE;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
+
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_NONE |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
- si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_WB; /* risky */
-#endif
- si.pci_0.acc_cntl_options[i] =
-#ifdef CONFIG_NOT_CACHE_COHERENT
- MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-#else
- MV64360_PCI_ACC_CNTL_SNOOP_WB | /* risky */
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
+
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_WB |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
- MV64360_PCI_ACC_CNTL_SWAP_NONE |
- MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
- MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
}
/* Lookup host bridge - on CPU 0 - no SMP support */
@@ -227,55 +233,44 @@
bh.hose_a->first_busno = 0;
bh.hose_a->last_busno = 0xff;
bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
-
}
void __init
chestnut_setup_peripherals(void)
{
-
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
+
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
+ cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
+
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
- /* Set up window for internal sram (256KByte insize) */
- mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
- boot_base = (u32)ioremap(CHESTNUT_BOOT_8BIT_BASE,
- CHESTNUT_BOOT_8BIT_SIZE);
- cpld_base = (u32)ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
+ CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
- /*
- * Configure internal SRAM -
- * Cache coherent write back, incase
- * CONFIG_MV64360_SRAM_CACHE_COHERENT set
- * Parity enabled.
- * Parity error propagation
- * Arbitration not parked for CPU only
- * Other bits are reserved.
- */
-#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
- mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
-#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
+#else
+ mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
+ sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
+ memset(sram_base, 0, MV64360_SRAM_SIZE);
- /*
- * Setting the SRAM to 0. Note that this generates parity errors on
- * internal data path in SRAM since it's first time accessing it
- * while after reset it's not configured
- */
- memset((void *)CHESTNUT_INTERNAL_SRAM_BASE, 0, CHESTNUT_INTERNAL_SRAM_SIZE);
/*
* Configure MPP pins for PCI DMA
*
@@ -312,9 +307,9 @@
(0xf << 20) | /* MPPSel13 GPIO[13] */
(0xf << 24) | /* MPPSel14 GPIO[14] */
(0xf << 28)); /* MPPSel15 GPIO[15] */
- mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL,
+ mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) |
- BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15)); /* Output */
+ BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15));
/*
* Configure the following MPP pins to indicate a level
@@ -364,7 +359,7 @@
/*
* Dismiss and then enable interrupt on CPU #0 high cause register
* BIT27 summarizes GPP interrupts 24-31
- */
+ */
mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
if (ppc_md.progress)
@@ -423,14 +418,32 @@
/* Identify the system */
printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
- printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc. (source@mvista.com)\n");
+ printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
+ " (source@mvista.com)\n");
if (ppc_md.progress)
ppc_md.progress("chestnut_setup_arch: exit", 0);
+}
+
+#ifdef CONFIG_MTD_PHYSMAP
+static struct mtd_partition ptbl;
+
+static int __init
+chestnut_setup_mtd(void)
+{
+ memset(&ptbl, 0, sizeof(ptbl));
- return;
+ ptbl.name = "User FS";
+ ptbl.size = CHESTNUT_32BIT_SIZE;
+
+ physmap_map.size = CHESTNUT_32BIT_SIZE;
+ physmap_set_partitions(&ptbl, 1);
+ return 0;
}
+arch_initcall(chestnut_setup_mtd);
+#endif
+
/**************************************************************************
* FUNCTION: chestnut_restart
*
@@ -450,7 +463,7 @@
*
* MPP24 - board reset
*/
- writeb(0x1, (void __iomem *)(cpld_base+3));
+ writeb(0x1, cpld_base + 3);
/* GPP pin tied to MPP earlier */
mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
@@ -474,37 +487,6 @@
/* NOTREACHED */
}
-#define SET_PCI_COMMAND_INVALIDATE
-#ifdef SET_PCI_COMMAND_INVALIDATE
-/*
- * Dave Wilhardt found that PCI_COMMAND_INVALIDATE must
- * be set for each device if you are using cache coherency.
- */
-static void __init
-set_pci_command_invalidate(void)
-{
- struct pci_dev *dev = NULL;
- u16 val;
-
- while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
- pci_read_config_word(dev, PCI_COMMAND, &val);
- val |= PCI_COMMAND_INVALIDATE;
- pci_write_config_word(dev, PCI_COMMAND, val);
-
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
- L1_CACHE_LINE_SIZE >> 2);
- }
-}
-#endif
-
-static void __init
-chestnut_pci_fixups(void)
-{
-#ifdef SET_PCI_COMMAND_INVALIDATE
- set_pci_command_invalidate();
-#endif
-}
-
/**************************************************************************
* FUNCTION: chestnut_map_io
*
@@ -514,27 +496,9 @@
static void __init
chestnut_map_io(void)
{
-#ifdef CONFIG_MV64360_SRAM_CACHEABLE
- io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE,
- _PAGE_KERNEL | _PAGE_GUARDED);
-#else
-#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
- io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE,
- _PAGE_KERNEL | _PAGE_GUARDED | _PAGE_COHERENT);
-#else
- io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_BASE,
- CHESTNUT_INTERNAL_SRAM_SIZE,
- _PAGE_IO);
-#endif /* !CONFIG_MV64360_SRAM_CACHE_COHERENT */
-#endif /* !CONFIG_MV64360_SRAM_CACHEABLE */
-
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000, _PAGE_IO);
+ io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
+ _PAGE_IO);
#endif
}
@@ -552,8 +516,6 @@
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xf000002a);
mb();
-
- return;
}
/**************************************************************************
@@ -587,7 +549,6 @@
ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
ppc_md.setup_io_mappings = chestnut_map_io;
- ppc_md.pcibios_fixup = chestnut_pci_fixups;
ppc_md.restart = chestnut_restart;
ppc_md.power_off = chestnut_power_off;
@@ -603,8 +564,6 @@
ppc_md.heartbeat = NULL;
- ppc_md.pcibios_fixup = chestnut_pci_fixups;
-
bh.p_base = CONFIG_MV64X60_NEW_BASE;
chestnut_set_bat();
@@ -618,6 +577,4 @@
if (ppc_md.progress)
ppc_md.progress("chestnut_init(): exit", 0);
-
- return;
}
diff -Nru a/arch/ppc/platforms/chestnut.h b/arch/ppc/platforms/chestnut.h
--- a/arch/ppc/platforms/chestnut.h 2005-03-11 14:51:08 -07:00
+++ b/arch/ppc/platforms/chestnut.h 2005-03-11 14:51:08 -07:00
@@ -24,11 +24,12 @@
* implement at 0xf1000000 only at this time
*
* 0xfff00000-0xffffffff - 8 Flash
+ * 0xffe00000-0xffefffff - BOOT SRAM
* 0xffd00000-0xffd00004 - CPLD
* 0xffc00000-0xffc0000f - UART
* 0xffb00000-0xffb07fff - FRAM
* 0xffa00000-0xffafffff - *** HOLE ***
- * 0xff900000-0xff9fffff - MV64460 Integrated SRAM
+ * 0xff800000-0xff9fffff - MV64460 Integrated SRAM
* 0xfe000000-0xff8fffff - *** HOLE ***
* 0xfc000000-0xfdffffff - 32bit Flash
* 0xf1010000-0xfbffffff - *** HOLE ***
@@ -49,9 +50,7 @@
#define CHESTNUT_UART_SIZE_ACTUAL 16
#define CHESTNUT_FRAM_BASE 0xffb00000
#define CHESTNUT_FRAM_SIZE_ACTUAL (32*1024)
-#define CHESTNUT_BRIDGE_REG_BASE 0xf1000000
-#define CHESTNUT_INTERNAL_SRAM_BASE 0xff900000
-#define CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL (256*1024)
+#define CHESTNUT_INTERNAL_SRAM_BASE 0xff800000
#define CHESTNUT_32BIT_BASE 0xfc000000
#define CHESTNUT_32BIT_SIZE (32*1024*1024)
@@ -65,14 +64,16 @@
CHESTNUT_UART_SIZE_ACTUAL)
#define CHESTNUT_FRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
CHESTNUT_FRAM_SIZE_ACTUAL)
-#define CHESTNUT_INTERNAL_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
- CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL)
#define CHESTNUT_BUS_SPEED 200000000
#define CHESTNUT_PIBS_DATABASE 0xf0000 /* from PIBS src code */
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT0 0x243c
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT1 0x283c
+#define KATANA_ETH0_PHY_ADDR 12
+#define KATANA_ETH1_PHY_ADDR 11
+#define KATANA_ETH2_PHY_ADDR 4
+
+#define CHESTNUT_ETH_TX_QUEUE_SIZE 800
+#define CHESTNUT_ETH_RX_QUEUE_SIZE 400
/*
* PCI windows
@@ -89,17 +90,17 @@
/*
* Board-specific IRQ info
*/
-#define CHESTNUT_PCI_SLOT0_IRQ 64+31
-#define CHESTNUT_PCI_SLOT1_IRQ 64+30
-#define CHESTNUT_PCI_SLOT2_IRQ 64+29
-#define CHESTNUT_PCI_SLOT3_IRQ 64+28
+#define CHESTNUT_PCI_SLOT0_IRQ (64 + 31)
+#define CHESTNUT_PCI_SLOT1_IRQ (64 + 30)
+#define CHESTNUT_PCI_SLOT2_IRQ (64 + 29)
+#define CHESTNUT_PCI_SLOT3_IRQ (64 + 28)
/* serial port definitions */
-#define CHESTNUT_UART0_IO_BASE CHESTNUT_UART_BASE+8
+#define CHESTNUT_UART0_IO_BASE (CHESTNUT_UART_BASE + 8)
#define CHESTNUT_UART1_IO_BASE CHESTNUT_UART_BASE
-#define UART0_INT 64+25
-#define UART1_INT 64+26
+#define UART0_INT (64 + 25)
+#define UART1_INT (64 + 26)
#ifdef CONFIG_SERIAL_MANY_PORTS
#define RS_TABLE_SIZE 64
@@ -108,7 +109,7 @@
#endif
/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
-#define BASE_BAUD ( 3686400 / 16 )
+#define BASE_BAUD (3686400 / 16)
#ifdef CONFIG_SERIAL_DETECT_IRQ
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
diff -Nru a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
--- a/drivers/mtd/maps/Kconfig 2005-03-11 14:51:08 -07:00
+++ b/drivers/mtd/maps/Kconfig 2005-03-11 14:51:08 -07:00
@@ -405,14 +405,6 @@
Redwood board. If you have one of these boards and would like to
use the flash chips on it, say 'Y'.
-config MTD_CHESTNUT
- tristate "CFI Flash devices mapped on IBM 750FX or IBM 750GX Eval Boards"
- depends on MTD_CFI && PPC32 && CHESTNUT && MTD_PARTITIONS
- help
- This enables access routines for the flash chips on the IBM
- 750FX and 750GX Eval Boards. If you have one of these boards and
- would like to use the flash chips on it, say 'Y'
-
config MTD_CSTM_MIPS_IXX
tristate "Flash chip mapping on ITE QED-4N-S01B, Globespan IVR or custom board"
depends on MIPS && MTD_CFI && MTD_JEDECPROBE && MTD_PARTITIONS
diff -Nru a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
--- a/drivers/mtd/maps/Makefile 2005-03-11 14:51:08 -07:00
+++ b/drivers/mtd/maps/Makefile 2005-03-11 14:51:08 -07:00
@@ -54,7 +54,6 @@
obj-$(CONFIG_MTD_IMPA7) += impa7.o
obj-$(CONFIG_MTD_FORTUNET) += fortunet.o
obj-$(CONFIG_MTD_REDWOOD) += redwood.o
-obj-$(CONFIG_MTD_CHESTNUT) += chestnut.o
obj-$(CONFIG_MTD_UCLINUX) += uclinux.o
obj-$(CONFIG_MTD_NETtel) += nettel.o
obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
diff -Nru a/drivers/mtd/maps/chestnut.c b/drivers/mtd/maps/chestnut.c
--- a/drivers/mtd/maps/chestnut.c 2005-03-11 14:51:08 -07:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,91 +0,0 @@
-/*
- * drivers/mtd/maps/chestnut.c
- *
- * $Id: chestnut.c,v 1.1 2005/01/05 16:59:50 dwmw2 Exp $
- *
- * Flash map driver for IBM Chestnut (750FXGX Eval)
- *
- * Chose not to enable 8 bit flash as it contains the firmware and board
- * info. Thus only the 32bit flash is supported.
- *
- * Author: <source@mvista.com>
- *
- * 2004 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <asm/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <platforms/chestnut.h>
-
-static struct map_info chestnut32_map = {
- .name = "User FS",
- .size = CHESTNUT_32BIT_SIZE,
- .bankwidth = 4,
- .phys = CHESTNUT_32BIT_BASE,
-};
-
-static struct mtd_partition chestnut32_partitions[] = {
- {
- .name = "User FS",
- .offset = 0,
- .size = CHESTNUT_32BIT_SIZE,
- }
-};
-
-static struct mtd_info *flash32;
-
-int __init init_chestnut(void)
-{
- /* 32-bit FLASH */
-
- chestnut32_map.virt = ioremap(chestnut32_map.phys, chestnut32_map.size);
-
- if (!chestnut32_map.virt) {
- printk(KERN_NOTICE "Failed to ioremap 32-bit flash\n");
- return -EIO;
- }
-
- simple_map_init(&chestnut32_map);
-
- flash32 = do_map_probe("cfi_probe", &chestnut32_map);
- if (flash32) {
- flash32->owner = THIS_MODULE;
- add_mtd_partitions(flash32, chestnut32_partitions,
- ARRAY_SIZE(chestnut32_partitions));
- } else {
- printk(KERN_NOTICE "map probe failed for 32-bit flash\n");
- return -ENXIO;
- }
-
- return 0;
-}
-
-static void __exit
-cleanup_chestnut(void)
-{
- if (flash32) {
- del_mtd_partitions(flash32);
- map_destroy(flash32);
- }
-
- if (chestnut32_map.virt) {
- iounmap((void *)chestnut32_map.virt);
- chestnut32_map.virt = 0;
- }
-}
-
-module_init(init_chestnut);
-module_exit(cleanup_chestnut);
-
-MODULE_DESCRIPTION("MTD map and partitions for IBM Chestnut (750fxgx Eval)");
-MODULE_AUTHOR("<source@mvista.com>");
-MODULE_LICENSE("GPL");
^ permalink raw reply
* Re: [PATCH 2/2] MPC52xx updates : PCI Support
From: Sylvain Munaut @ 2005-03-11 21:06 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: Tom Rini, linuxppc-embedded
In-Reply-To: <20050311204823.GA11928@xyzzy>
Dale Farnsworth wrote:
>The first hunk of arch/ppc/platforms/lite5200.c looks corrupted.
>See the line beginning "fdef CONFIG_PCI".
>
>-Dale
>
>
>
Damn, you're right and even the first patch is screwed, half of it is
missing.
Discard theses, I'll put them on-line somewhere and post the urls.
Sylvain
>On Fri, Mar 11, 2005 at 08:08:26PM +0000, Sylvain Munaut wrote:
>
>
>>And here's the second patch :
>>
>>
>
>[ deleted lines ]
>
>
>
>>diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
>>--- a/arch/ppc/platforms/lite5200.c 2005-03-11 20:41:56 +01:00
>>+++ b/arch/ppc/platforms/lite5200.c 2005-03-11 20:41:56 +01:00
>>@@ -35,6 +35,8 @@
>>#include <asm/ocp.h>
>>#include <asm/mpc52xx.h>
>>
>>+#include <syslib/mpc52xx_pci.h>
>>+
>>
>>extern int powersave_nap;
>>
>>fdef CONFIG_PCI
>>+static int
>>+lite5200_map_irq(struct pci_dev *dev, unsigned char idsel,
>>+ unsigned char pin) {
>>+ return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1;
>>+}
>>+#endif
>>
>>
>
>[ more deleted lines ]
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
>
^ permalink raw reply
* Re: [PATCH 1/2] MPC52xx updates : sparse clean-ups
From: Tom Rini @ 2005-03-11 21:00 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: LKML, Embedded PPC Linux list
In-Reply-To: <423203EC.1070003@246tNt.com>
On Fri, Mar 11, 2005 at 09:47:40PM +0100, Sylvain Munaut wrote:
[snip]
> static struct hw_interrupt_type mpc52xx_ic = {
> - "MPC52xx",
[snip]
> + .typename = "MPC52xx",
Shouldn't that be " MPC52xx ", or is that another field I'm thinking
of?
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Re: [PATCH 2/2] MPC52xx updates : PCI Support
From: Dale Farnsworth @ 2005-03-11 20:48 UTC (permalink / raw)
To: Sylvain Munaut, linuxppc-embedded
In-Reply-To: <4231FABA.2030809@246tNt.com>
The first hunk of arch/ppc/platforms/lite5200.c looks corrupted.
See the line beginning "fdef CONFIG_PCI".
-Dale
On Fri, Mar 11, 2005 at 08:08:26PM +0000, Sylvain Munaut wrote:
> And here's the second patch :
[ deleted lines ]
> diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
> --- a/arch/ppc/platforms/lite5200.c 2005-03-11 20:41:56 +01:00
> +++ b/arch/ppc/platforms/lite5200.c 2005-03-11 20:41:56 +01:00
> @@ -35,6 +35,8 @@
> #include <asm/ocp.h>
> #include <asm/mpc52xx.h>
>
> +#include <syslib/mpc52xx_pci.h>
> +
>
> extern int powersave_nap;
>
> fdef CONFIG_PCI
> +static int
> +lite5200_map_irq(struct pci_dev *dev, unsigned char idsel,
> + unsigned char pin) {
> + return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1;
> +}
> +#endif
[ more deleted lines ]
^ permalink raw reply
* Re: [PATCH 1/2] MPC52xx updates : sparse clean-ups
From: Sylvain Munaut @ 2005-03-11 20:47 UTC (permalink / raw)
To: Kumar Gala; +Cc: Tom Rini, LKML, Embedded PPC Linux list
In-Reply-To: <be4da82f8d12e20b54050e15fd27df36@freescale.com>
Kumar Gala wrote:
>>
>>
>> diff -Nru a/arch/ppc/syslib/mpc52xx_pic.c
>> b/arch/ppc/syslib/mpc52xx_pic.c
>> --- a/arch/ppc/syslib/mpc52xx_pic.c 2005-03-11 20:41:36 +01:00
>> +++ b/arch/ppc/syslib/mpc52xx_pic.c 2005-03-11 20:41:36 +01:00
>> @@ -33,8 +33,8 @@
>> #include <asm/mpc52xx.h>
>>
>>
>>
>> -static struct mpc52xx_intr *intr;
>> -static struct mpc52xx_sdma *sdma;
>> +static struct mpc52xx_intr __iomem *intr;
>> +static struct mpc52xx_sdma __iomem *sdma;
>>
>> static void
>> mpc52xx_ic_disable(unsigned int irq)
>> @@ -173,7 +173,7 @@
>> mpc52xx_ic_disable, /* disable(irq) */
>> mpc52xx_ic_disable_and_ack, /* disable_and_ack(irq) */
>> mpc52xx_ic_end, /* end(irq) */
>> - 0 /* set_affinity(irq, cpumask)
>> SMP. */
>> + NULL /* set_affinity(irq, cpumask)
>> SMP. */
>> };
>
>
> It looks like others have moved to a C99 initialization style for
> hw_interrupt_type, see syslib/ipic.c for an example.
>
Indeed. Here's a third patch ;)
It has been added to the bk tree as well.
# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
# 2005/03/11 21:37:08+01:00 tnt@246tNt.com
# ppc32: Change to a C99 initialization style for hw_interrupt_type
# in MPC52xx interrupt controller
#
# arch/ppc/syslib/mpc52xx_pic.c
# 2005/03/11 21:36:54+01:00 tnt@246tNt.com +5 -8
# ppc32: Change to a C99 initialization style for hw_interrupt_type
# in MPC52xx interrupt controller
#
diff -Nru a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c
--- a/arch/ppc/syslib/mpc52xx_pic.c 2005-03-11 21:45:50 +01:00
+++ b/arch/ppc/syslib/mpc52xx_pic.c 2005-03-11 21:45:50 +01:00
@@ -166,14 +166,11 @@
}
static struct hw_interrupt_type mpc52xx_ic = {
- "MPC52xx",
- NULL, /* startup(irq) */
- NULL, /* shutdown(irq) */
- mpc52xx_ic_enable, /* enable(irq) */
- mpc52xx_ic_disable, /* disable(irq) */
- mpc52xx_ic_disable_and_ack, /* disable_and_ack(irq) */
- mpc52xx_ic_end, /* end(irq) */
- NULL /* set_affinity(irq, cpumask)
SMP. */
+ .typename = "MPC52xx",
+ .enable = mpc52xx_ic_enable,
+ .disable = mpc52xx_ic_disable,
+ .ack = mpc52xx_ic_disable_and_ack,
+ .end = mpc52xx_ic_end,
};
void __init
^ permalink raw reply
* Re: query regarding I2C controller on MPC8260
From: Yuli Barcohen @ 2005-03-11 20:39 UTC (permalink / raw)
To: Vijay Padiyar; +Cc: linuxppc-embedded
In-Reply-To: <BAY1-DAV11E7EFC29304B234EEB9A38B530@phx.gbl>
>>>>> Vijay Padiyar writes:
Vijay> Hi there I am using an MPC8260-based target board. My target
Vijay> is running U-Boot 1.1.2 as the bootloader and Linux-2.6.10 as
Vijay> the kernel with BusyBox-1.0. I wish to use the I2C controller
Vijay> on the MPC8260 to access an external EEPROM connected to
Vijay> it. I need to do this from *user space*.
Vijay> From what I understand, we can open the I2C device with the
Vijay> open command from our application as follows:
Vijay> ret = open ("/dev/i2c-0", O_RDWR);
Vijay> After this, the device should be accessible using either
Vijay> standard I2C functions or SMBus functions.
Vijay> I read that if the I2C controller supports SMBus, it will be
Vijay> preferable to access the device via the SMBus read/write
Vijay> functions, as they seem to be more "efficient." What I want
Vijay> to know is, does the PowerPC I2C controller support the SMBus
Vijay> protocol? I don't think it does, judging from the MPC8260
Vijay> manual, but just want to be sure.
It does not support SMBus but since it's a full-featured I2C controller,
it's not a problem. SMBus emulation mode can be used on any I2C
controller.
Vijay> Also, do we need to create the /dev/i2c-0 device file
Vijay> manually or will it be created on the fly?
It depends on the /dev filesystem which you use. If it's devfs (or you
use udev), the file will be created on the fly, otherwise you have to
create it manually.
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli@arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply
* Re: [PATCH 1/2] MPC52xx updates : sparse clean-ups
From: Kumar Gala @ 2005-03-11 20:12 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: Tom Rini, LKML, Embedded PPC Linux list
In-Reply-To: <4231F9F9.5080506@246tNt.com>
On Mar 11, 2005, at 2:05 PM, Sylvain Munaut wrote:
> Hi Tom & all
>
> Here's some updates related to the Freescale MPC52xx. First some
> clean-ups for sparse warnings and then PCI support. I'd like to get
> theses approved & merged before I submit conversion to platform bus
> model.
>
> As usual, the patches can also be pulled of a bk repository :
> bk://tnt.bkbits.net/linux-2.5-mpc52xx-pending
>
> (note it's _NOT_ the same url as before even if it's close ;)
>
>
>
>
> =A0=A0=A0 Sylvain
>
> ---
>
> diff -Nru a/arch/ppc/syslib/mpc52xx_pic.c=20
> b/arch/ppc/syslib/mpc52xx_pic.c
> --- a/arch/ppc/syslib/mpc52xx_pic.c=A0=A0=A0=A0 2005-03-11 20:41:36 =
+01:00
> +++ b/arch/ppc/syslib/mpc52xx_pic.c=A0=A0=A0=A0 2005-03-11 20:41:36 =
+01:00
> @@ -33,8 +33,8 @@
> =A0#include <asm/mpc52xx.h>
>
>
>
> -static struct mpc52xx_intr *intr;
> -static struct mpc52xx_sdma *sdma;
> +static struct mpc52xx_intr __iomem *intr;
> +static struct mpc52xx_sdma __iomem *sdma;
>
> =A0static void
> =A0mpc52xx_ic_disable(unsigned int irq)
> @@ -173,7 +173,7 @@
> =A0=A0=A0=A0=A0=A0=A0 mpc52xx_ic_disable,=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0 /* disable(irq) */
> =A0=A0=A0=A0=A0=A0=A0 mpc52xx_ic_disable_and_ack,=A0=A0=A0=A0 /* =
disable_and_ack(irq) */
> =A0=A0=A0=A0=A0=A0=A0 mpc52xx_ic_end,=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0 /* end(irq) */
> -=A0=A0=A0=A0=A0=A0 0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* set_affinity(irq, cpumask)
> SMP. */
> +=A0=A0=A0=A0=A0=A0 NULL=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* set_affinity(irq, cpumask)
> SMP. */
> =A0};
It looks like others have moved to a C99 initialization style for=20
hw_interrupt_type, see syslib/ipic.c for an example.
> =A0void __init
> @@ -183,10 +183,8 @@
> =A0=A0=A0=A0=A0=A0=A0 u32 intr_ctrl;
>
> =A0=A0=A0=A0=A0=A0=A0 /* Remap the necessary zones */
> -=A0=A0=A0=A0=A0=A0 intr =3D (struct mpc52xx_intr *)
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 ioremap(MPC52xx_INTR, =
sizeof(struct mpc52xx_intr));
> -=A0=A0=A0=A0=A0=A0 sdma =3D (struct mpc52xx_sdma *)
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 ioremap(MPC52xx_SDMA, =
sizeof(struct mpc52xx_sdma));
> +=A0=A0=A0=A0=A0=A0 intr =3D ioremap(MPC52xx_INTR, sizeof(struct =
mpc52xx_intr));
> +=A0=A0=A0=A0=A0=A0 sdma =3D ioremap(MPC52xx_SDMA, sizeof(struct =
mpc52xx_sdma));
>
> =A0=A0=A0=A0=A0=A0=A0 if ((intr=3D=3DNULL) || (sdma=3D=3DNULL))
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 panic("Can't ioremap =
PIC/SDMA register for init_irq=20
> !");
> diff -Nru a/arch/ppc/syslib/mpc52xx_setup.c
> b/arch/ppc/syslib/mpc52xx_setup.c
> --- a/arch/ppc/syslib/mpc52xx_setup.c=A0=A0 2005-03-11 20:41:36 +01:00
> +++ b/arch/ppc/syslib/mpc52xx_setup.c=A0=A0 2005-03-11 20:41:36 =
+01:00
> @@ -39,7 +39,8 @@
> =A0void
> =A0mpc52xx_restart(char *cmd)
> =A0{
> -=A0=A0=A0=A0=A0=A0 struct mpc52xx_gpt* gpt0 =3D (struct =
mpc52xx_gpt*)=20
> MPC52xx_GPTx(0);
> +=A0=A0=A0=A0=A0=A0 struct mpc52xx_gpt __iomem *gpt0 =3D
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (struct mpc52xx_gpt =
__iomem *) MPC52xx_GPTx(0);
>
> =A0=A0=A0=A0=A0=A0=A0 local_irq_disable();
>
> @@ -102,7 +103,7 @@
> =A0#endif
>
> =A0static void
> -mpc52xx_psc_putc(struct mpc52xx_psc * psc, unsigned char c)
> +mpc52xx_psc_putc(struct mpc52xx_psc __iomem *psc, unsigned char c)
> =A0{
> =A0=A0=A0=A0=A0=A0=A0 while (!(in_be16(&psc->mpc52xx_psc_status) &
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
MPC52xx_PSC_SR_TXRDY));
> @@ -112,8 +113,9 @@
> =A0void
> =A0mpc52xx_progress(char *s, unsigned short hex)
> =A0{
> -=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc *psc =3D (struct mpc52xx_psc=20=
> *)MPC52xx_CONSOLE;
> =A0=A0=A0=A0=A0=A0=A0 char c;
> +=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc __iomem *psc =3D
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (struct mpc52xx_psc =
__iomem *)MPC52xx_CONSOLE;
>
> =A0=A0=A0=A0=A0=A0=A0 while ((c =3D *s++) !=3D 0) {
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if (c =3D=3D '\n')
> @@ -138,11 +140,11 @@
> =A0=A0=A0=A0=A0=A0=A0=A0 * else get size from sdram config registers
> =A0=A0=A0=A0=A0=A0=A0=A0 */
> =A0=A0=A0=A0=A0=A0=A0 if (ramsize =3D=3D 0) {
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct mpc52xx_mmap_ctl =
*mmap_ctl;
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct mpc52xx_mmap_ctl =
__iomem *mmap_ctl;
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 u32 sdram_config_0, =
sdram_config_1;
>
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* Temp BAT2 mapping =
active when this is called ! */
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 mmap_ctl =3D (struct =
mpc52xx_mmap_ctl*)=20
> MPC52xx_MMAP_CTL;
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 mmap_ctl =3D (struct =
mpc52xx_mmap_ctl __iomem *)
> MPC52xx_MMAP_CTL;
>
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 sdram_config_0 =3D =
in_be32(&mmap_ctl->sdram0);
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 sdram_config_1 =3D =
in_be32(&mmap_ctl->sdram1);
> @@ -169,13 +171,11 @@
> =A0=A0=A0=A0=A0=A0=A0 /* if bootloader didn't pass bus frequencies, =
calculate them=20
> */
> =A0=A0=A0=A0=A0=A0=A0 if (xlbfreq =3D=3D 0) {
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* Get RTC & Clock =
manager modules */
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct mpc52xx_rtc *rtc;
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct mpc52xx_cdm *cdm;
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct mpc52xx_rtc =
__iomem *rtc;
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct mpc52xx_cdm =
__iomem *cdm;
>
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rtc =3D (struct =
mpc52xx_rtc*)
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
ioremap(MPC52xx_RTC, sizeof(struct=20
> mpc52xx_rtc));
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 cdm =3D (struct =
mpc52xx_cdm*)
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
ioremap(MPC52xx_CDM, sizeof(struct=20
> mpc52xx_cdm));
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rtc =3D =
ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 cdm =3D =
ioremap(MPC52xx_CDM, sizeof(struct mpc52xx_cdm));
>
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if ((rtc=3D=3DNULL) || =
(cdm=3D=3DNULL))
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
panic("Can't ioremap RTC/CDM while computing=20
> bus
> freq");
> @@ -212,8 +212,8 @@
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 __res.bi_pcifreq =3D =
pcifreq;
>
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* Release mapping */
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 iounmap((void*)rtc);
> -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 iounmap((void*)cdm);
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 iounmap(rtc);
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 iounmap(cdm);
> =A0=A0=A0=A0=A0=A0=A0 }
>
> =A0=A0=A0=A0=A0=A0=A0 divisor =3D 4;
> diff -Nru a/drivers/serial/mpc52xx_uart.c=20
> b/drivers/serial/mpc52xx_uart.c
> --- a/drivers/serial/mpc52xx_uart.c=A0=A0=A0=A0 2005-03-11 20:41:36 =
+01:00
> +++ b/drivers/serial/mpc52xx_uart.c=A0=A0=A0=A0 2005-03-11 20:41:36 =
+01:00
> @@ -86,7 +86,7 @@
> =A0=A0=A0=A0=A0=A0=A0=A0 *=A0=A0=A0=A0=A0=A0=A0 the console_init
> =A0=A0=A0=A0=A0=A0=A0=A0 */
>
> -#define PSC(port) ((struct mpc52xx_psc *)((port)->membase))
> +#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
>
>
>
> =A0/* Forward declaration of the interruption handling routine */
> @@ -190,7 +190,7 @@
> =A0static int
> =A0mpc52xx_uart_startup(struct uart_port *port)
> =A0{
> -=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc *psc =3D PSC(port);
> +=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc __iomem *psc =3D PSC(port);
>
> =A0=A0=A0=A0=A0=A0=A0 /* Reset/activate the port, clear and enable =
interrupts */
> =A0=A0=A0=A0=A0=A0=A0 out_8(&psc->command,MPC52xx_PSC_RST_RX);
> @@ -217,7 +217,7 @@
> =A0static void
> =A0mpc52xx_uart_shutdown(struct uart_port *port)
> =A0{
> -=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc *psc =3D PSC(port);
> +=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc __iomem *psc =3D PSC(port);
>
> =A0=A0=A0=A0=A0=A0=A0 /* Shut down the port, interrupt and all */
> =A0=A0=A0=A0=A0=A0=A0 out_8(&psc->command,MPC52xx_PSC_RST_RX);
> @@ -231,7 +231,7 @@
> =A0mpc52xx_uart_set_termios(struct uart_port *port, struct termios =
*new,
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0 struct termios *old)
> =A0{
> -=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc *psc =3D PSC(port);
> +=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc __iomem *psc =3D PSC(port);
> =A0=A0=A0=A0=A0=A0=A0 unsigned long flags;
> =A0=A0=A0=A0=A0=A0=A0 unsigned char mr1, mr2;
> =A0=A0=A0=A0=A0=A0=A0 unsigned short ctr;
> @@ -562,7 +562,7 @@
> =A0mpc52xx_console_get_options(struct uart_port *port,
> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0 int *baud, int *parity, int *bits, int=20
> *flow)
> =A0{
> -=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc *psc =3D PSC(port);
> +=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc __iomem *psc =3D PSC(port);
> =A0=A0=A0=A0=A0=A0=A0 unsigned char mr1;
>
> =A0=A0=A0=A0=A0=A0=A0 /* Read the mode registers */
> @@ -592,7 +592,7 @@
> =A0mpc52xx_console_write(struct console *co, const char *s, unsigned =
int
> count)
> =A0{
> =A0=A0=A0=A0=A0=A0=A0 struct uart_port *port =3D =
&mpc52xx_uart_ports[co->index];
> -=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc *psc =3D PSC(port);
> +=A0=A0=A0=A0=A0=A0 struct mpc52xx_psc __iomem *psc =3D PSC(port);
> =A0=A0=A0=A0=A0=A0=A0 unsigned int i, j;
>
> =A0=A0=A0=A0=A0=A0=A0 /* Disable interrupts */
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: [PATCH 2/2] MPC52xx updates : PCI Support
From: Sylvain Munaut @ 2005-03-11 20:08 UTC (permalink / raw)
To: Embedded PPC Linux list; +Cc: Tom Rini, LKML
In-Reply-To: <4231F9F9.5080506@246tNt.com>
And here's the second patch :
# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
# 2005/03/11 19:58:21+01:00 tnt@246tNt.com
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# Note that this support has "known" problem but theses
# are believed to be due to hardware issues.
#
# Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
#
# arch/ppc/syslib/mpc52xx_pci.h
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +139 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# include/linux/pci_ids.h
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +1 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# include/asm-ppc/mpc52xx.h
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +2 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/syslib/mpc52xx_pci.h
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +0 -0
# BitKeeper file
/home/tnt/musicbox/kernel/linux-2.5-mpc52xx-pending/arch/ppc/syslib/mpc52xx_pci.h
#
# arch/ppc/syslib/mpc52xx_pci.c
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +235 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/syslib/Makefile
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +3 -0
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/platforms/lite5200.c
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +33 -3
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/Kconfig
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +1 -1
# ppc32: Add PCI bus support for Freescale MPC52xx
#
# arch/ppc/syslib/mpc52xx_pci.c
# 2005/03/11 19:57:56+01:00 tnt@246tNt.com +0 -0
# BitKeeper file
/home/tnt/musicbox/kernel/linux-2.5-mpc52xx-pending/arch/ppc/syslib/mpc52xx_pci.c
#
diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig 2005-03-11 20:41:56 +01:00
+++ b/arch/ppc/Kconfig 2005-03-11 20:41:56 +01:00
@@ -1097,7 +1097,7 @@
bool
config PCI
- bool "PCI support" if 40x || CPM2 || 83xx || 85xx
+ bool "PCI support" if 40x || CPM2 || 83xx || 85xx || PPC_MPC52xx
default y if !40x && !CPM2 && !8xx && !APUS && !83xx && !85xx
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
default PCI_QSPAN if !4xx && !CPM2 && 8xx
diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
--- a/arch/ppc/platforms/lite5200.c 2005-03-11 20:41:56 +01:00
+++ b/arch/ppc/platforms/lite5200.c 2005-03-11 20:41:56 +01:00
@@ -35,6 +35,8 @@
#include <asm/ocp.h>
#include <asm/mpc52xx.h>
+#include <syslib/mpc52xx_pci.h>
+
extern int powersave_nap;
fdef CONFIG_PCI
+static int
+lite5200_map_irq(struct pci_dev *dev, unsigned char idsel,
+ unsigned char pin) {
+ return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1;
+}
+#endif
+
static void __init
lite5200_setup_cpu(void)
{
+ struct mpc52xx_xlb __iomem *xlb;
struct mpc52xx_intr __iomem *intr;
u32 intr_ctrl;
/* Map zones */
+ xlb = ioremap(MPC52xx_XLB,sizeof(struct mpc52xx_xlb));
intr = ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
- if (!intr) {
- printk("lite5200.c: Error while mapping INTR during
lite5200_setup_cpu\n");
+ if (!xlb || !intr) {
+ printk("lite5200.c: Error while mapping XLB/INTR during
lite5200_setup_cpu\n");
goto unmap_regs;
}
+ /* Configure the XLB Arbiter */
+ out_be32(&xlb->master_pri_enable, 0xff);
+ out_be32(&xlb->master_priority, 0x11111111);
+
+ /* Enable ram snooping for 1GB window */
+ out_be32(&xlb->config, in_be32(&xlb->config) |
MPC52xx_XLB_CFG_SNOOP);
+ out_be32(&xlb->snoop_window, MPC52xx_PCI_TARGET_MEM | 0x1d);
+
/* IRQ[0-3] setup : IRQ0 - Level Active Low */
/* IRQ[1-3] - Level Active High */
intr_ctrl = in_be32(&intr->ctrl);
@@ -103,6 +123,7 @@
/* Unmap reg zone */
unmap_regs:
+ if (xlb) iounmap(xlb);
if (intr) iounmap(intr);
}
@@ -114,6 +135,11 @@
/* CPU & Port mux setup */
lite5200_setup_cpu();
+
+#ifdef CONFIG_PCI
+ /* PCI Bridge setup */
+ mpc52xx_find_bridges();
+#endif
}
void __init
@@ -152,7 +178,7 @@
/* BAT setup */
mpc52xx_set_bat();
- /* No ISA bus AFAIK */
+ /* No ISA bus by default */
isa_io_base = 0;
isa_mem_base = 0;
@@ -165,6 +191,10 @@
ppc_md.show_percpuinfo = NULL;
ppc_md.init_IRQ = mpc52xx_init_irq;
ppc_md.get_irq = mpc52xx_get_irq;
+
+#ifdef CONFIG_PCI
+ ppc_md.pci_map_irq = lite5200_map_irq;
+#endif
ppc_md.find_end_of_memory = mpc52xx_find_end_of_memory;
ppc_md.setup_io_mappings = mpc52xx_map_io;
diff -Nru a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile 2005-03-11 20:41:56 +01:00
+++ b/arch/ppc/syslib/Makefile 2005-03-11 20:41:56 +01:00
@@ -106,3 +106,6 @@
endif
obj-$(CONFIG_MPC8555_CDS) += todc_time.o
obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o
+ifeq ($(CONFIG_PPC_MPC52xx),y)
+obj-$(CONFIG_PCI) += mpc52xx_pci.o
+endif
diff -Nru a/arch/ppc/syslib/mpc52xx_pci.c b/arch/ppc/syslib/mpc52xx_pci.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/mpc52xx_pci.c 2005-03-11 20:41:56 +01:00
@@ -0,0 +1,235 @@
+/*
+ * arch/ppc/syslib/mpc52xx_pci.c
+ *
+ * PCI code for the Freescale MPC52xx embedded CPU.
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+
+#include <asm/pci.h>
+
+#include <asm/mpc52xx.h>
+#include "mpc52xx_pci.h"
+
+#include <asm/delay.h>
+
+
+static int
+mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ u32 value;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ out_be32(hose->cfg_addr,
+ (1 << 31) |
+ ((bus->number - hose->bus_offset) << 16) |
+ (devfn << 8) |
+ (offset & 0xfc));
+
+ value = in_le32(hose->cfg_data);
+
+ if (len != 4) {
+ value >>= ((offset & 0x3) << 3);
+ value &= 0xffffffff >> (32 - (len << 3));
+ }
+
+ *val = value;
+
+ out_be32(hose->cfg_addr, 0);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ u32 value, mask;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ out_be32(hose->cfg_addr,
+ (1 << 31) |
+ ((bus->number - hose->bus_offset) << 16) |
+ (devfn << 8) |
+ (offset & 0xfc));
+
+ if (len != 4) {
+ value = in_le32(hose->cfg_data);
+
+ offset = (offset & 0x3) << 3;
+ mask = (0xffffffff >> (32 - (len << 3)));
+ mask <<= offset;
+
+ value &= ~mask;
+ val = value | ((val << offset) & mask);
+ }
+
+ out_le32(hose->cfg_data, val);
+
+ out_be32(hose->cfg_addr, 0);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops mpc52xx_pci_ops = {
+ .read = mpc52xx_pci_read_config,
+ .write = mpc52xx_pci_write_config
+};
+
+
+static void __init
+mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
+{
+
+ /* Setup control regs */
+ /* Nothing to do afaik */
+
+ /* Setup windows */
+ out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
+ MPC52xx_PCI_MEM_START + MPC52xx_PCI_MEM_OFFSET,
+ MPC52xx_PCI_MEM_START,
+ MPC52xx_PCI_MEM_SIZE ));
+
+ out_be32(&pci_regs->iw1btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
+ MPC52xx_PCI_MMIO_START + MPC52xx_PCI_MEM_OFFSET,
+ MPC52xx_PCI_MMIO_START,
+ MPC52xx_PCI_MMIO_SIZE ));
+
+ out_be32(&pci_regs->iw2btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
+ MPC52xx_PCI_IO_BASE,
+ MPC52xx_PCI_IO_START,
+ MPC52xx_PCI_IO_SIZE ));
+
+ out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(
+ ( MPC52xx_PCI_IWCR_ENABLE | /* iw0btar */
+ MPC52xx_PCI_IWCR_READ_MULTI |
+ MPC52xx_PCI_IWCR_MEM ),
+ ( MPC52xx_PCI_IWCR_ENABLE | /* iw1btar */
+ MPC52xx_PCI_IWCR_READ |
+ MPC52xx_PCI_IWCR_MEM ),
+ ( MPC52xx_PCI_IWCR_ENABLE | /* iw2btar */
+ MPC52xx_PCI_IWCR_IO )
+ ));
+
+
+ out_be32(&pci_regs->tbatr0,
+ MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO );
+ out_be32(&pci_regs->tbatr1,
+ MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
+
+ out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
+
+ /* Reset the exteral bus ( internal PCI controller is NOT
resetted ) */
+ /* Not necessary and can be a bad thing if for example the
bootloader
+ is displaying a splash screen or ... Just left here for
+ documentation purpose if anyone need it */
+#if 0
+ u32 tmp;
+ tmp = in_be32(&pci_regs->gscr);
+ out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
+ udelay(50);
+ out_be32(&pci_regs->gscr, tmp);
+#endif
+}
+
+static void __init
+mpc52xx_pci_fixup_resources(struct pci_dev *dev)
+{
+ int i;
+
+ /* We don't rely on boot loader for PCI and resets all
+ devices */
+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+ struct resource *res = &dev->resource[i];
+ if (res->end > res->start) { /* Only valid resources */
+ res->end -= res->start;
+ res->start = 0;
+ res->flags |= IORESOURCE_UNSET;
+ }
+ }
+
+ /* The PCI Host bridge of MPC52xx has a prefetch memory resource
+ fixed to 1Gb. Doesn't fit in the resource system so we remove
it */
+ if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
+ (dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200) ) {
+ struct resource *res = &dev->resource[1];
+ res->start = res->end = res->flags = 0;
+ }
+}
+
+void __init
+mpc52xx_find_bridges(void)
+{
+ struct mpc52xx_pci __iomem *pci_regs;
+ struct pci_controller *hose;
+
+ pci_assign_all_busses = 1;
+
+ pci_regs = ioremap(MPC52xx_PCI, sizeof(struct mpc52xx_pci));
+ if (!pci_regs)
+ return;
+
+ hose = pcibios_alloc_controller();
+ if (!hose) {
+ iounmap(pci_regs);
+ return;
+ }
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+ hose->bus_offset = 0;
+ hose->ops = &mpc52xx_pci_ops;
+
+ mpc52xx_pci_setup(pci_regs);
+
+ hose->pci_mem_offset = MPC52xx_PCI_MEM_OFFSET;
+
+ isa_io_base =
+ (unsigned long) ioremap(MPC52xx_PCI_IO_BASE,
+ MPC52xx_PCI_IO_SIZE);
+ hose->io_base_virt = (void *) isa_io_base;
+
+ hose->cfg_addr = &pci_regs->car;
+ hose->cfg_data = (void __iomem *) isa_io_base;
+
+ /* Setup resources */
+ pci_init_resource(&hose->mem_resources[0],
+ MPC52xx_PCI_MEM_START,
+ MPC52xx_PCI_MEM_STOP,
+ IORESOURCE_MEM|IORESOURCE_PREFETCH,
+ "PCI prefetchable memory");
+
+ pci_init_resource(&hose->mem_resources[1],
+ MPC52xx_PCI_MMIO_START,
+ MPC52xx_PCI_MMIO_STOP,
+ IORESOURCE_MEM,
+ "PCI memory");
+
+ pci_init_resource(&hose->io_resource,
+ MPC52xx_PCI_IO_START,
+ MPC52xx_PCI_IO_STOP,
+ IORESOURCE_IO,
+ "PCI I/O");
+
+}
diff -Nru a/arch/ppc/syslib/mpc52xx_pci.h b/arch/ppc/syslib/mpc52xx_pci.h
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/mpc52xx_pci.h 2005-03-11 20:41:56 +01:00
@@ -0,0 +1,139 @@
+/*
+ * arch/ppc/syslib/mpc52xx_pci.h
+ *
+ * PCI Include file the Freescale MPC52xx embedded cpu chips
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Inspired from code written by Dale Farnsworth <dfarnsworth@mvista.com>
+ * for the 2.4 kernel.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __SYSLIB_MPC52xx_PCI_H__
+#define __SYSLIB_MPC52xx_PCI_H__
+
+/*
======================================================================== */
+/* PCI windows
config */
+/*
======================================================================== */
+
+/*
+ * Master windows : MPC52xx -> PCI
+ *
+ * 0x80000000 -> 0x9FFFFFFF PCI Mem prefetchable IW0BTAR
+ * 0xA0000000 -> 0xAFFFFFFF PCI Mem IW1BTAR
+ * 0xB0000000 -> 0xB0FFFFFF PCI IO IW2BTAR
+ *
+ * Slave windows : PCI -> MPC52xx
+ *
+ * 0xF0000000 -> 0xF003FFFF MPC52xx MBAR TBATR0
+ * 0x00000000 -> 0x3FFFFFFF MPC52xx local memory TBATR1
+ */
+
+#define MPC52xx_PCI_MEM_OFFSET 0x00000000 /* Offset for
MEM MMIO */
+
+#define MPC52xx_PCI_MEM_START 0x80000000
+#define MPC52xx_PCI_MEM_SIZE 0x20000000
+#define MPC52xx_PCI_MEM_STOP
(MPC52xx_PCI_MEM_START+MPC52xx_PCI_MEM_SIZE-1)
+
+#define MPC52xx_PCI_MMIO_START 0xa0000000
+#define MPC52xx_PCI_MMIO_SIZE 0x10000000
+#define MPC52xx_PCI_MMIO_STOP
(MPC52xx_PCI_MMIO_START+MPC52xx_PCI_MMIO_SIZE-1)
+
+#define MPC52xx_PCI_IO_BASE 0xb0000000
+
+#define MPC52xx_PCI_IO_START 0x00000000
+#define MPC52xx_PCI_IO_SIZE 0x01000000
+#define MPC52xx_PCI_IO_STOP (MPC52xx_PCI_IO_START+MPC52xx_PCI_IO_SIZE-1)
+
+
+#define MPC52xx_PCI_TARGET_IO MPC52xx_MBAR
+#define MPC52xx_PCI_TARGET_MEM 0x00000000
+
+
+/*
======================================================================== */
+/* Structures mapping & Defines for PCI
Unit */
+/*
======================================================================== */
+
+#define MPC52xx_PCI_GSCR_BM 0x40000000
+#define MPC52xx_PCI_GSCR_PE 0x20000000
+#define MPC52xx_PCI_GSCR_SE 0x10000000
+#define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000
+#define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24
+#define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000
+#define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16
+#define MPC52xx_PCI_GSCR_BME 0x00004000
+#define MPC52xx_PCI_GSCR_PEE 0x00002000
+#define MPC52xx_PCI_GSCR_SEE 0x00001000
+#define MPC52xx_PCI_GSCR_PR 0x00000001
+
+
+#define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \
+ ( ( (proc_ad) & 0xff000000 ) | \
+ ( (((size) - 1) >> 8) & 0x00ff0000 ) | \
+ ( ((pci_ad) >> 16) & 0x0000ff00 ) )
+
+#define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \
+ ((win1) << 16) | \
+ ((win2) << 8))
+
+#define MPC52xx_PCI_IWCR_DISABLE 0x0
+#define MPC52xx_PCI_IWCR_ENABLE 0x1
+#define MPC52xx_PCI_IWCR_READ 0x0
+#define MPC52xx_PCI_IWCR_READ_LINE 0x2
+#define MPC52xx_PCI_IWCR_READ_MULTI 0x4
+#define MPC52xx_PCI_IWCR_MEM 0x0
+#define MPC52xx_PCI_IWCR_IO 0x8
+
+#define MPC52xx_PCI_TCR_P 0x01000000
+#define MPC52xx_PCI_TCR_LD 0x00010000
+
+#define MPC52xx_PCI_TBATR_DISABLE 0x0
+#define MPC52xx_PCI_TBATR_ENABLE 0x1
+
+
+#ifndef __ASSEMBLY__
+
+struct mpc52xx_pci {
+ u32 idr; /* PCI + 0x00 */
+ u32 scr; /* PCI + 0x04 */
+ u32 ccrir; /* PCI + 0x08 */
+ u32 cr1; /* PCI + 0x0C */
+ u32 bar0; /* PCI + 0x10 */
+ u32 bar1; /* PCI + 0x14 */
+ u8 reserved1[16]; /* PCI + 0x18 */
+ u32 ccpr; /* PCI + 0x28 */
+ u32 sid; /* PCI + 0x2C */
+ u32 erbar; /* PCI + 0x30 */
+ u32 cpr; /* PCI + 0x34 */
+ u8 reserved2[4]; /* PCI + 0x38 */
+ u32 cr2; /* PCI + 0x3C */
+ u8 reserved3[32]; /* PCI + 0x40 */
+ u32 gscr; /* PCI + 0x60 */
+ u32 tbatr0; /* PCI + 0x64 */
+ u32 tbatr1; /* PCI + 0x68 */
+ u32 tcr; /* PCI + 0x6C */
+ u32 iw0btar; /* PCI + 0x70 */
+ u32 iw1btar; /* PCI + 0x74 */
+ u32 iw2btar; /* PCI + 0x78 */
+ u8 reserved4[4]; /* PCI + 0x7C */
+ u32 iwcr; /* PCI + 0x80 */
+ u32 icr; /* PCI + 0x84 */
+ u32 isr; /* PCI + 0x88 */
+ u32 arb; /* PCI + 0x8C */
+ u8 reserved5[104]; /* PCI + 0x90 */
+ u32 car; /* PCI + 0xF8 */
+ u8 reserved6[4]; /* PCI + 0xFC */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* __SYSLIB_MPC52xx_PCI_H__ */
diff -Nru a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
--- a/include/asm-ppc/mpc52xx.h 2005-03-11 20:41:56 +01:00
+++ b/include/asm-ppc/mpc52xx.h 2005-03-11 20:41:56 +01:00
@@ -393,6 +393,8 @@
extern void mpc52xx_calibrate_decr(void);
extern void mpc52xx_add_board_devices(struct ocp_def board_ocp[]);
+extern void mpc52xx_find_bridges(void);
+
#endif /* __ASSEMBLY__ */
diff -Nru a/include/linux/pci_ids.h b/include/linux/pci_ids.h
--- a/include/linux/pci_ids.h 2005-03-11 20:41:56 +01:00
+++ b/include/linux/pci_ids.h 2005-03-11 20:41:56 +01:00
@@ -807,6 +807,7 @@
#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806
#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803
#define PCI_VENDOR_ID_PROMISE 0x105a
#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
^ permalink raw reply
* [PATCH 1/2] MPC52xx updates : sparse clean-ups
From: Sylvain Munaut @ 2005-03-11 20:05 UTC (permalink / raw)
To: Embedded PPC Linux list, LKML, Tom Rini
Hi Tom & all
Here's some updates related to the Freescale MPC52xx. First some
clean-ups for sparse warnings and then PCI support. I'd like to get
theses approved & merged before I submit conversion to platform bus
model.
As usual, the patches can also be pulled of a bk repository :
bk://tnt.bkbits.net/linux-2.5-mpc52xx-pending
(note it's _NOT_ the same url as before even if it's close ;)
Sylvain
---
diff -Nru a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c
--- a/arch/ppc/syslib/mpc52xx_pic.c 2005-03-11 20:41:36 +01:00
+++ b/arch/ppc/syslib/mpc52xx_pic.c 2005-03-11 20:41:36 +01:00
@@ -33,8 +33,8 @@
#include <asm/mpc52xx.h>
-static struct mpc52xx_intr *intr;
-static struct mpc52xx_sdma *sdma;
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
static void
mpc52xx_ic_disable(unsigned int irq)
@@ -173,7 +173,7 @@
mpc52xx_ic_disable, /* disable(irq) */
mpc52xx_ic_disable_and_ack, /* disable_and_ack(irq) */
mpc52xx_ic_end, /* end(irq) */
- 0 /* set_affinity(irq, cpumask)
SMP. */
+ NULL /* set_affinity(irq, cpumask)
SMP. */
};
void __init
@@ -183,10 +183,8 @@
u32 intr_ctrl;
/* Remap the necessary zones */
- intr = (struct mpc52xx_intr *)
- ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
- sdma = (struct mpc52xx_sdma *)
- ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
+ intr = ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
+ sdma = ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
if ((intr==NULL) || (sdma==NULL))
panic("Can't ioremap PIC/SDMA register for init_irq !");
diff -Nru a/arch/ppc/syslib/mpc52xx_setup.c
b/arch/ppc/syslib/mpc52xx_setup.c
--- a/arch/ppc/syslib/mpc52xx_setup.c 2005-03-11 20:41:36 +01:00
+++ b/arch/ppc/syslib/mpc52xx_setup.c 2005-03-11 20:41:36 +01:00
@@ -39,7 +39,8 @@
void
mpc52xx_restart(char *cmd)
{
- struct mpc52xx_gpt* gpt0 = (struct mpc52xx_gpt*) MPC52xx_GPTx(0);
+ struct mpc52xx_gpt __iomem *gpt0 =
+ (struct mpc52xx_gpt __iomem *) MPC52xx_GPTx(0);
local_irq_disable();
@@ -102,7 +103,7 @@
#endif
static void
-mpc52xx_psc_putc(struct mpc52xx_psc * psc, unsigned char c)
+mpc52xx_psc_putc(struct mpc52xx_psc __iomem *psc, unsigned char c)
{
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY));
@@ -112,8 +113,9 @@
void
mpc52xx_progress(char *s, unsigned short hex)
{
- struct mpc52xx_psc *psc = (struct mpc52xx_psc *)MPC52xx_CONSOLE;
char c;
+ struct mpc52xx_psc __iomem *psc =
+ (struct mpc52xx_psc __iomem *)MPC52xx_CONSOLE;
while ((c = *s++) != 0) {
if (c == '\n')
@@ -138,11 +140,11 @@
* else get size from sdram config registers
*/
if (ramsize == 0) {
- struct mpc52xx_mmap_ctl *mmap_ctl;
+ struct mpc52xx_mmap_ctl __iomem *mmap_ctl;
u32 sdram_config_0, sdram_config_1;
/* Temp BAT2 mapping active when this is called ! */
- mmap_ctl = (struct mpc52xx_mmap_ctl*) MPC52xx_MMAP_CTL;
+ mmap_ctl = (struct mpc52xx_mmap_ctl __iomem *)
MPC52xx_MMAP_CTL;
sdram_config_0 = in_be32(&mmap_ctl->sdram0);
sdram_config_1 = in_be32(&mmap_ctl->sdram1);
@@ -169,13 +171,11 @@
/* if bootloader didn't pass bus frequencies, calculate them */
if (xlbfreq == 0) {
/* Get RTC & Clock manager modules */
- struct mpc52xx_rtc *rtc;
- struct mpc52xx_cdm *cdm;
+ struct mpc52xx_rtc __iomem *rtc;
+ struct mpc52xx_cdm __iomem *cdm;
- rtc = (struct mpc52xx_rtc*)
- ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
- cdm = (struct mpc52xx_cdm*)
- ioremap(MPC52xx_CDM, sizeof(struct mpc52xx_cdm));
+ rtc = ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
+ cdm = ioremap(MPC52xx_CDM, sizeof(struct mpc52xx_cdm));
if ((rtc==NULL) || (cdm==NULL))
panic("Can't ioremap RTC/CDM while computing bus
freq");
@@ -212,8 +212,8 @@
__res.bi_pcifreq = pcifreq;
/* Release mapping */
- iounmap((void*)rtc);
- iounmap((void*)cdm);
+ iounmap(rtc);
+ iounmap(cdm);
}
divisor = 4;
diff -Nru a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
--- a/drivers/serial/mpc52xx_uart.c 2005-03-11 20:41:36 +01:00
+++ b/drivers/serial/mpc52xx_uart.c 2005-03-11 20:41:36 +01:00
@@ -86,7 +86,7 @@
* the console_init
*/
-#define PSC(port) ((struct mpc52xx_psc *)((port)->membase))
+#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
/* Forward declaration of the interruption handling routine */
@@ -190,7 +190,7 @@
static int
mpc52xx_uart_startup(struct uart_port *port)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
/* Reset/activate the port, clear and enable interrupts */
out_8(&psc->command,MPC52xx_PSC_RST_RX);
@@ -217,7 +217,7 @@
static void
mpc52xx_uart_shutdown(struct uart_port *port)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
/* Shut down the port, interrupt and all */
out_8(&psc->command,MPC52xx_PSC_RST_RX);
@@ -231,7 +231,7 @@
mpc52xx_uart_set_termios(struct uart_port *port, struct termios *new,
struct termios *old)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
unsigned long flags;
unsigned char mr1, mr2;
unsigned short ctr;
@@ -562,7 +562,7 @@
mpc52xx_console_get_options(struct uart_port *port,
int *baud, int *parity, int *bits, int *flow)
{
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
unsigned char mr1;
/* Read the mode registers */
@@ -592,7 +592,7 @@
mpc52xx_console_write(struct console *co, const char *s, unsigned int
count)
{
struct uart_port *port = &mpc52xx_uart_ports[co->index];
- struct mpc52xx_psc *psc = PSC(port);
+ struct mpc52xx_psc __iomem *psc = PSC(port);
unsigned int i, j;
/* Disable interrupts */
^ permalink raw reply
* MPC5200 clock manipulation
From: Sauro Salomoni @ 2005-03-11 17:12 UTC (permalink / raw)
To: Linux-Embedded
Good afternoon.
I am using 2.4.25 denx Linux kernel in a MPC5200 custom board and I am
looking for solutions to reduce power consumption. One possible
solution is to reduce the frequencies using the CDM Registers.
But then I have a problem: the MPC5200 User Manual states that the
Power On Configuration Register is a read only register, then I can
only configure it using straps and reseting the board. And the CDM
Configurations Register, which controls IPB and PCI clocks, is already
configured for low frequencies by default.
Does anyone have a sugestion on how to reduce the frequencies (Fsystem
and XLB) without the need of a reset? Maybe there is a way of
configuring the clocks that I couldn't figure out.
Thanks in advance
--
Sauro Salomoni
Engeneer
Ztec
Fone: +55 61 322-2544 FAX:+55 61 224-7171
www.ztec.com.br
^ permalink raw reply
* query regarding I2C controller on MPC8260
From: Vijay Padiyar @ 2005-03-11 12:58 UTC (permalink / raw)
To: LinuxPPC Support
Hi there
I am using an MPC8260-based target board. My target is running U-Boot 1.1.2
as the bootloader and Linux-2.6.10 as the kernel with BusyBox-1.0. I wish to
use the I2C controller on the MPC8260 to access an external EEPROM connected
to it. I need to do this from *user space*.
>From what I understand, we can open the I2C device with the open command
from our application as follows:
ret = open ("/dev/i2c-0", O_RDWR);
After this, the device should be accessible using either standard I2C
functions or SMBus functions.
I read that if the I2C controller supports SMBus, it will be preferable to
access the device via the SMBus read/write functions, as they seem to be
more "efficient." What I want to know is, does the PowerPC I2C controller
support the SMBus protocol? I don't think it does, judging from the MPC8260
manual, but just want to be sure.
Also, do we need to create the /dev/i2c-0 device file manually or will it be
created on the fly?
Regards
Vijay Padiyar
http://www.vijaypadiyar.eu.tf
^ permalink raw reply
* Re: boot time scheduling hile atomic
From: Takeharu KATO @ 2005-03-11 6:19 UTC (permalink / raw)
To: Takeharu KATO; +Cc: linuxppc-dev
In-Reply-To: <423073A9.70404@ybb.ne.jp>
Hi Joerg:
First of all, I am sorry to making mistake on my stack analysis.
After all, I found what is wrong.
The syscall_exit_work is called(jumped) by fork, strictly speaking,
this is caused by kernel_thead for init process.
At this point, kernel set a need_resched flag in thread_info struct
(flags member).
So, the system executes syscall_exit_work when
the swapper thread exited from syscall.
However, the syscall_exit_work routine does not check
preempt counts when it calls schedule function.
FYI, I post the patch which fix this problem.
I've confirmed the problem has been removed by this patch,
but I can not figure out whether it is truely
correct or not.
Please review this.
Signed-off-by: Takeharu KATO <kato.takeharu@jp.fujitsu.com>
--- linux-2.6.11/arch/ppc/kernel/entry.S 2005-03-09 12:57:32.000000000 +0900
+++ linux-2.6.11-wdt/arch/ppc/kernel/entry.S 2005-03-11 14:39:16.345490784 +0900
@@ -314,10 +314,16 @@ syscall_exit_work:
SYNC
MTMSRD(r10) /* disable interrupts again */
rlwinm r12,r1,0,0,18 /* current_thread_info() */
- lwz r9,TI_FLAGS(r12)
5:
+#ifdef CONFIG_PREEMPT
+ lwz r0,TI_PREEMPT(r12)
+ cmpwi 0,r0,0 /* if non-zero, we can not reschedule here */
+ bne 6f
+#endif
+ lwz r9,TI_FLAGS(r12)
andi. r0,r9,_TIF_NEED_RESCHED
bne 1f
+6:
lwz r5,_MSR(r1)
andi. r5,r5,MSR_PR
beq syscall_exit_cont
--
Takeharu KATO
Fujitsu Limited
Email:kato.takeharu at jp.fujitsu.com
^ permalink raw reply
* MPC5200 PCI TX/RX FIFO
From: Nick Barendt @ 2005-03-11 0:27 UTC (permalink / raw)
To: linuxppc-dev
Has anyone had luck getting the MPC5200 PCI RX or TX FIFOs
working, either directly or with Bestcomm DMA support? I've been trying to
do so for a few weeks, on and off, with little luck. I'm probably missing
something obvious.
I'm using Wolfgang's kernel tree, on a board similar to the IceCube.
I'd like to use the PCI RX FIFO to speed up moving data from a PCI
device - it looks like the RX FIFO is the most straight-forward mechanism
for bursting. I've had some luck getting the RX FIFO to pull data back
from a PCI device, and can get a peripheral interrupt from the RX FIFO, but
no matter what I do (read data from FIFO to DDR, clear status bits, etc.),
I can't seem to acknowledge the interrupt at the peripheral end, so it
continues to fire. I can't find anything in the MPC5200 user manual about
acknowledging the interrupt in the PCI controller, unlike the FEC, say,
which has documentation on how to ack FEC interrupts.
I then went the Bestcomm route, using the Bestcomm API, but I'm
clearly missing something there, because the DMA engine indicates a TEA
after a very long timeout. That problem might be related to my PCI RX FIFO
interrupt problem, or might be completely different. Might it be that the
Alarm signal to the DMA engine is the same as the interrupt signal to the core?
In the end, I'd like to go the DMA route. It is likely that using
the RX FIFO would be a significant improvement over what I have right now,
though, and it is (hopefully) easier to get up and running.
Does anyone have any wisdom (or, better yet, sample code :-) they
can share on this?
Nick Barendt
VXI Technology, Inc.
Cleveland Instruments Division
5425 Warner Road, Suite 13
Valley View, OH 44125
PH: 216-447-4059
FAX: 216-447-8951
nbarendt@vxitech.com
^ permalink raw reply
* Re: RFC: PHY Abstraction Layer II
From: Benjamin Herrenschmidt @ 2005-03-10 23:27 UTC (permalink / raw)
To: Jeff Garzik; +Cc: netdev, linuxppc-embedded, David S. Miller
In-Reply-To: <4230D7F4.8060900@pobox.com>
On Thu, 2005-03-10 at 18:27 -0500, Jeff Garzik wrote:
> I haven't had time to review the phy abstraction layer, but my gut
> feeling is that there are several common code patterns which could be
> abstracted out, to save code.
>
> Typically there will be one or more phy-specific functions in each
> 10/100 or GigE driver, falling back to a default 'genphy' driver when
> things are completely MII/GMII-compatible.
Exactly. One thing for which i usually need PHY specific functions
(pretty much all the time) is PHY init (thanks Broadcom) and suspend.
Ben.
^ permalink raw reply
* Re: RFC: PHY Abstraction Layer II
From: Jeff Garzik @ 2005-03-10 23:27 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: netdev, linuxppc-embedded, David S. Miller
In-Reply-To: <1110495992.32525.290.camel@gaston>
Benjamin Herrenschmidt wrote:
> On Thu, 2005-03-10 at 23:01 +0000, James Chapman wrote:
>
>>Hi Andy,
>>
>>Can you elaborate on why this phy abstraction is needed?
>>
>>In your original post, you mentioned that you were going to post a
>>patch to show how your code would be hooked up in an existing net
>>driver. Did I miss it? It would help in understanding the pros and cons
>>of using genphy over using plain old mii.c.
>>
>>btw, I recently posted a patch to add GigE support to mii.c which is
>>in Jeff's netdev-2.6 queue. Some register definitions were added in
>>mii.h that will collide with yours.
>
>
> A variety of PHY chips require special cases that aren't handled by the
> generic mii code. The PHY driver layer allows to plug PHY specific
> drivers, with genphy just being the "default" for sane chips.
>
> Also, I think Andy added more to the PHY layer than what mii does, like
> support for the interrupt or timer based link management etc... which
> tend to be the same in a lot of drivers.
Nod.
I haven't had time to review the phy abstraction layer, but my gut
feeling is that there are several common code patterns which could be
abstracted out, to save code.
Typically there will be one or more phy-specific functions in each
10/100 or GigE driver, falling back to a default 'genphy' driver when
things are completely MII/GMII-compatible.
Jeff
^ permalink raw reply
* Re: RFC: PHY Abstraction Layer II
From: Benjamin Herrenschmidt @ 2005-03-10 23:06 UTC (permalink / raw)
To: James Chapman; +Cc: netdev, David S. Miller, linuxppc-embedded
In-Reply-To: <4230D1AC.5070506@katalix.com>
On Thu, 2005-03-10 at 23:01 +0000, James Chapman wrote:
> Hi Andy,
>
> Can you elaborate on why this phy abstraction is needed?
>
> In your original post, you mentioned that you were going to post a
> patch to show how your code would be hooked up in an existing net
> driver. Did I miss it? It would help in understanding the pros and cons
> of using genphy over using plain old mii.c.
>
> btw, I recently posted a patch to add GigE support to mii.c which is
> in Jeff's netdev-2.6 queue. Some register definitions were added in
> mii.h that will collide with yours.
A variety of PHY chips require special cases that aren't handled by the
generic mii code. The PHY driver layer allows to plug PHY specific
drivers, with genphy just being the "default" for sane chips.
Also, I think Andy added more to the PHY layer than what mii does, like
support for the interrupt or timer based link management etc... which
tend to be the same in a lot of drivers.
Ben.
^ permalink raw reply
* Re: RFC: PHY Abstraction Layer II
From: James Chapman @ 2005-03-10 23:01 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-embedded, David S. Miller, netdev
In-Reply-To: <57a429f8eb807987d88b06129861d507@freescale.com>
Hi Andy,
Can you elaborate on why this phy abstraction is needed?
In your original post, you mentioned that you were going to post a
patch to show how your code would be hooked up in an existing net
driver. Did I miss it? It would help in understanding the pros and cons
of using genphy over using plain old mii.c.
btw, I recently posted a patch to add GigE support to mii.c which is
in Jeff's netdev-2.6 queue. Some register definitions were added in
mii.h that will collide with yours.
/james
Andy Fleming wrote:
>
> On Mar 8, 2005, at 21:50, Benjamin Herrenschmidt wrote:
>
>> On Tue, 2005-03-08 at 19:42 -0800, David S. Miller wrote:
>>
>>> On Wed, 09 Mar 2005 13:14:16 +1100
>>> Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>>>
>>>> I'll have a closer look when I find some time, see if it makes sense to
>>>> adapt sungem or not.
>>>
>>>
>>> Especially because of the Broadcom PHYs I bet it doesn't.
>>>
>>> Too many chips have to reset the MAC, or do other fancy stuff
>>> when programming the PHY to make this genphy thing very useful.
>>
>>
>> Oh, I think genphy is just a generic driver, but his layer has hooks for
>> other PHY drivers (wasn't it based on sungem_phy in the first place ?)
>
>
> Definitely. Much of this code was culled from the sungem and ibm_emac
> drivers, with some input from mii.c. The genphy driver is just one of
> the 6 PHY drivers in the patch I sent (the others are Marvell, Davicom,
> Cicada, QS, LXT). Actually, several of those files have multiple
> drivers in them. The genphy driver is the fallback driver. It exists
> for those PHYs which never get a driver, but don't need special attention.
>
>>
>> I discussed several steps of the design with Andy, the idea was to have
>> something a bit like sungem_phy.c with addditional common library for
>> doing the link polling & fallback stuff etc... that could be easily
>> shared by drivers.
>
>
> Yup. I look forward to your input on how well the code meshes with what
> people need for their drivers.
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* Re: [PATCH 2.6.12] PPC32: Add rtc hooks to katana + fw bug workaround
From: Mark A. Greer @ 2005-03-10 16:45 UTC (permalink / raw)
To: Embedded PPC Linux list
In-Reply-To: <42307939.5060301@mvista.com>
Sorry again for the spam.
Mark
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox