* Re: [PATCH 2.6.12] PPC32: Add rtc hooks to katana + fw bug workaround
From: Mark A. Greer @ 2005-03-10 16:45 UTC (permalink / raw)
To: Embedded PPC Linux list
In-Reply-To: <42307939.5060301@mvista.com>
Sorry again for the spam.
Mark
^ permalink raw reply
* [PATCH 2.6.12] PPC32: Add rtc hooks to katana + fw bug workaround
From: Mark A. Greer @ 2005-03-10 16:44 UTC (permalink / raw)
To: akpm; +Cc: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 442 bytes --]
Add rtc hooks to katana and workaround firmware bug.
- Now that the mv64xxx i2c and m41t00 i2c rtc drivers are in the source
base, add hooks to the katana file to use that rtc.
- A recent version of the katana firmware incorrectly changes the
mv64x60's pci vendor & device id so this patch puts back the proper values.
- Misc. cleanup and update of the default config file.
Please apply.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
[-- Attachment #2: katana_rtc.patch --]
[-- Type: text/plain, Size: 18630 bytes --]
diff -Nru a/arch/ppc/configs/katana_defconfig b/arch/ppc/configs/katana_defconfig
--- a/arch/ppc/configs/katana_defconfig 2005-03-10 09:34:32 -07:00
+++ b/arch/ppc/configs/katana_defconfig 2005-03-10 09:34:32 -07:00
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc4
-# Tue Feb 15 14:27:12 2005
+# Linux kernel version: 2.6.11
+# Tue Mar 8 17:31:00 2005
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
@@ -36,6 +36,7 @@
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -45,6 +46,7 @@
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
#
# Loadable module support
@@ -70,6 +72,7 @@
CONFIG_ALTIVEC=y
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
+# CONFIG_83xx is not set
CONFIG_PPC_STD_MMU=y
CONFIG_NOT_COHERENT_CACHE=y
@@ -93,6 +96,7 @@
# CONFIG_PRPMC750 is not set
# CONFIG_PRPMC800 is not set
# CONFIG_SANDPOINT is not set
+# CONFIG_RADSTONE_PPC7D is not set
# CONFIG_ADIR is not set
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
@@ -428,7 +432,6 @@
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
CONFIG_E100=y
-# CONFIG_E100_NAPI is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
@@ -453,6 +456,10 @@
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+CONFIG_MV643XX_ETH_2=y
#
# Ethernet (10000 Mbit)
@@ -575,7 +582,90 @@
#
# I2C support
#
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+CONFIG_SENSORS_M41T00=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
@@ -753,6 +843,7 @@
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_PRINTK_TIME is not set
#
# Security options
diff -Nru a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
--- a/arch/ppc/platforms/katana.c 2005-03-10 09:34:32 -07:00
+++ b/arch/ppc/platforms/katana.c 2005-03-10 09:34:32 -07:00
@@ -3,7 +3,7 @@
*
* Board setup routines for the Artesyn Katana cPCI boards.
*
- * Athor: Tim Montgomery <timm@artesyncp.com>
+ * Author: Tim Montgomery <timm@artesyncp.com>
* Maintained by: Mark A. Greer <mgreer@mvista.com>
*
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
@@ -50,6 +50,8 @@
static u32 katana_flash_size_0;
static u32 katana_flash_size_1;
+static u32 katana_bus_frequency;
+
unsigned char __res[sizeof(bd_t)];
/* PCI Interrupt routing */
@@ -183,44 +185,102 @@
}
static void __init
-katana_enable_ipmi(void)
+katana_setup_bridge(void)
{
- u8 reset_out;
+ struct pci_controller hose;
+ struct mv64x60_setup_info si;
+ void __iomem *vaddr;
+ int i;
+ u16 val;
+ u8 save_exclude;
- /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
- reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
- reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
- out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
-}
+ /*
+ * Some versions of the Katana firmware mistakenly change the vendor
+ * & device id fields in the bridge's pci device (visible via pci
+ * config accesses). This breaks mv64x60_init() because those values
+ * are used to identify the type of bridge that's there. Artesyn
+ * claims that the subsystem vendor/device id's will have the correct
+ * Marvell values so this code puts back the correct values from there.
+ */
+ memset(&hose, 0, sizeof(hose));
+ vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
+ setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
+ vaddr + MV64x60_PCI0_CONFIG_DATA);
+ save_exclude = mv64x60_pci_exclude_bridge;
+ mv64x60_pci_exclude_bridge = 0;
+
+ early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
+
+ if (val != PCI_VENDOR_ID_MARVELL) {
+ early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_SUBSYSTEM_VENDOR_ID, &val);
+ early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_VENDOR_ID, val);
+ early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_SUBSYSTEM_ID, &val);
+ early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_DEVICE_ID, val);
+ }
-static u32
-katana_bus_freq(void)
-{
- u8 bd_cfg_0;
+ mv64x60_pci_exclude_bridge = save_exclude;
+ iounmap(vaddr);
- bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0);
+ memset(&si, 0, sizeof(si));
- switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
- case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
- return 200000000;
- break;
+ si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
- case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
- return 166666666;
- break;
+ si.pci_1.enable_bus = 1;
+ si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
+ si.pci_1.pci_io.pci_base_hi = 0;
+ si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
+ si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
+ si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
+ si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
+ si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
+ si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
+ si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_1.pci_cmd_bits = 0;
+ si.pci_1.latency_timer = 0x80;
- case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
- return 133333333;
- break;
+ for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
- case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
- return 100000000;
- break;
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_NONE |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+#else
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
- default:
- return 133333333;
- break;
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_WB |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
+#endif
}
+
+ /* Lookup PCI host bridges */
+ if (mv64x60_init(&bh, &si))
+ printk(KERN_WARNING "Bridge initialization failed.\n");
+
+ pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = katana_map_irq;
+ ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
+
+ mv64x60_set_bus(&bh, 1, 0);
+ bh.hose_b->first_busno = 0;
+ bh.hose_b->last_busno = 0xff;
}
/* Bridge & platform setup routines */
@@ -356,138 +416,16 @@
}
static void __init
-katana_setup_bridge(void)
-{
- struct mv64x60_setup_info si;
- int i;
-
- memset(&si, 0, sizeof(si));
-
- si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
- si.pci_1.enable_bus = 1;
- si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
- si.pci_1.pci_io.pci_base_hi = 0;
- si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
- si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
- si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
- si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
- si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
- si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
- si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
- si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
- si.pci_1.pci_cmd_bits = 0;
- si.pci_1.latency_timer = 0x80;
-
- for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
-#if defined(CONFIG_NOT_COHERENT_CACHE)
- si.cpu_prot_options[i] = 0;
- si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
- si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
- si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
-
- si.pci_1.acc_cntl_options[i] =
- MV64360_PCI_ACC_CNTL_SNOOP_NONE |
- MV64360_PCI_ACC_CNTL_SWAP_NONE |
- MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
- MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-#else
- si.cpu_prot_options[i] = 0;
- si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
- si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
- si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
-
- si.pci_1.acc_cntl_options[i] =
- MV64360_PCI_ACC_CNTL_SNOOP_WB |
- MV64360_PCI_ACC_CNTL_SWAP_NONE |
- MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
- MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
-#endif
- }
-
- /* Lookup PCI host bridges */
- if (mv64x60_init(&bh, &si))
- printk(KERN_WARNING "Bridge initialization failed.\n");
-
- pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = katana_map_irq;
- ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
- mv64x60_set_bus(&bh, 1, 0);
- bh.hose_b->first_busno = 0;
- bh.hose_b->last_busno = 0xff;
-}
-
-#ifdef CONFIG_MTD_PHYSMAP
-
-#ifndef MB
-#define MB (1 << 20)
-#endif
-
-/*
- * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
- *
- * FLASH Amount: 128 64 32 16
- * ------------- --- -- -- --
- * Monitor: 1 1 1 1
- * Primary Kernel: 1.5 1.5 1.5 1.5
- * Primary fs: 30 30 <end> <end>
- * Secondary Kernel: 1.5 1.5 N/A N/A
- * Secondary fs: <end> <end> N/A N/A
- * User: <overlays entire FLASH except for "Monitor" section>
- */
-static int __init
-katana_setup_mtd(void)
+katana_enable_ipmi(void)
{
- u32 size;
- int ptbl_entries;
- static struct mtd_partition *ptbl;
-
- size = katana_flash_size_0 + katana_flash_size_1;
- if (!size)
- return -ENOMEM;
-
- ptbl_entries = (size >= (64*MB)) ? 6 : 4;
-
- if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
- GFP_KERNEL)) == NULL) {
-
- printk(KERN_WARNING "Can't alloc MTD partition table\n");
- return -ENOMEM;
- }
- memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
-
- ptbl[0].name = "Monitor";
- ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
- ptbl[1].name = "Primary Kernel";
- ptbl[1].offset = MTDPART_OFS_NXTBLK;
- ptbl[1].size = 0x00180000; /* 1.5 MB */
- ptbl[2].name = "Primary Filesystem";
- ptbl[2].offset = MTDPART_OFS_APPEND;
- ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
- ptbl[ptbl_entries-1].name = "User FLASH";
- ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
- ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
-
- if (size >= (64*MB)) {
- ptbl[2].size = 30*MB;
- ptbl[3].name = "Secondary Kernel";
- ptbl[3].offset = MTDPART_OFS_NXTBLK;
- ptbl[3].size = 0x00180000; /* 1.5 MB */
- ptbl[4].name = "Secondary Filesystem";
- ptbl[4].offset = MTDPART_OFS_APPEND;
- ptbl[4].size = MTDPART_SIZ_FULL;
- }
+ u8 reset_out;
- physmap_map.size = size;
- physmap_set_partitions(ptbl, ptbl_entries);
- return 0;
+ /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
+ reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
+ reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
+ out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
}
-arch_initcall(katana_setup_mtd);
-#endif
-
static void __init
katana_setup_arch(void)
{
@@ -528,6 +466,8 @@
katana_setup_peripherals();
katana_enable_ipmi();
+ katana_bus_frequency = katana_bus_freq(cpld_base);
+
printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: exit", 0);
@@ -550,7 +490,7 @@
* TCLK == SysCLK but on 64460, they are separate pins.
* SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
*/
- pdata->brg_clk_freq = min(katana_bus_freq(), MV64x60_TCLK_FREQ_MAX);
+ pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
}
#endif
@@ -606,6 +546,75 @@
return 0;
}
+#ifdef CONFIG_MTD_PHYSMAP
+
+#ifndef MB
+#define MB (1 << 20)
+#endif
+
+/*
+ * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
+ *
+ * FLASH Amount: 128 64 32 16
+ * ------------- --- -- -- --
+ * Monitor: 1 1 1 1
+ * Primary Kernel: 1.5 1.5 1.5 1.5
+ * Primary fs: 30 30 <end> <end>
+ * Secondary Kernel: 1.5 1.5 N/A N/A
+ * Secondary fs: <end> <end> N/A N/A
+ * User: <overlays entire FLASH except for "Monitor" section>
+ */
+static int __init
+katana_setup_mtd(void)
+{
+ u32 size;
+ int ptbl_entries;
+ static struct mtd_partition *ptbl;
+
+ size = katana_flash_size_0 + katana_flash_size_1;
+ if (!size)
+ return -ENOMEM;
+
+ ptbl_entries = (size >= (64*MB)) ? 6 : 4;
+
+ if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
+ GFP_KERNEL)) == NULL) {
+
+ printk(KERN_WARNING "Can't alloc MTD partition table\n");
+ return -ENOMEM;
+ }
+ memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
+
+ ptbl[0].name = "Monitor";
+ ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
+ ptbl[1].name = "Primary Kernel";
+ ptbl[1].offset = MTDPART_OFS_NXTBLK;
+ ptbl[1].size = 0x00180000; /* 1.5 MB */
+ ptbl[2].name = "Primary Filesystem";
+ ptbl[2].offset = MTDPART_OFS_APPEND;
+ ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
+ ptbl[ptbl_entries-1].name = "User FLASH";
+ ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
+ ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
+
+ if (size >= (64*MB)) {
+ ptbl[2].size = 30*MB;
+ ptbl[3].name = "Secondary Kernel";
+ ptbl[3].offset = MTDPART_OFS_NXTBLK;
+ ptbl[3].size = 0x00180000; /* 1.5 MB */
+ ptbl[4].name = "Secondary Filesystem";
+ ptbl[4].offset = MTDPART_OFS_APPEND;
+ ptbl[4].size = MTDPART_SIZ_FULL;
+ }
+
+ physmap_map.size = size;
+ physmap_set_partitions(ptbl, ptbl_entries);
+ return 0;
+}
+
+arch_initcall(katana_setup_mtd);
+#endif
+
static void
katana_restart(char *cmd)
{
@@ -672,7 +681,7 @@
seq_printf(m, "PLD rev\t\t: 0x%x\n",
in_8(cpld_base + KATANA_CPLD_PLD_VER));
seq_printf(m, "PLB freq\t: %ldMhz\n",
- (long)katana_bus_freq() / 1000000);
+ (long)katana_bus_frequency / 1000000);
seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-");
return 0;
@@ -683,7 +692,7 @@
{
u32 freq;
- freq = katana_bus_freq() / 4;
+ freq = katana_bus_frequency / 4;
printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
(long)freq / 1000000, (long)freq % 1000000);
@@ -698,6 +707,27 @@
return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
MV64x60_TYPE_MV64360);
}
+
+#if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00)
+extern ulong m41t00_get_rtc_time(void);
+extern int m41t00_set_rtc_time(ulong);
+
+static int __init
+katana_rtc_hookup(void)
+{
+ struct timespec tv;
+
+ ppc_md.get_rtc_time = m41t00_get_rtc_time;
+ ppc_md.set_rtc_time = m41t00_set_rtc_time;
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = (ppc_md.get_rtc_time)();
+ do_settimeofday(&tv);
+
+ return 0;
+}
+late_initcall(katana_rtc_hookup);
+#endif
static inline void
katana_set_bat(void)
diff -Nru a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h
--- a/arch/ppc/platforms/katana.h 2005-03-10 09:34:32 -07:00
+++ b/arch/ppc/platforms/katana.h 2005-03-10 09:34:32 -07:00
@@ -3,7 +3,8 @@
*
* Definitions for Artesyn Katana750i/3750 board.
*
- * Tim Montgomery <timm@artesyncp.com>
+ * Author: Tim Montgomery <timm@artesyncp.com>
+ * Maintained by: Mark A. Greer <mgreer@mvista.com>
*
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
* Based on code done by Mark A. Greer <mgreer@mvista.com>
@@ -221,4 +222,34 @@
#endif
-#endif /* __PPC_PLATFORMS_KATANA_H */
+static inline u32
+katana_bus_freq(void __iomem *cpld_base)
+{
+ u8 bd_cfg_0;
+
+ bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0);
+
+ switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
+ return 200000000;
+ break;
+
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
+ return 166666666;
+ break;
+
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
+ return 133333333;
+ break;
+
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
+ return 100000000;
+ break;
+
+ default:
+ return 133333333;
+ break;
+ }
+}
+
+#endif /* __PPC_PLATFORMS_KATANA_H */
^ permalink raw reply
* [PATCH 2.6.12] PPC32: Add rtc hooks to katana + fw bug workaround
From: Mark A. Greer @ 2005-03-10 16:43 UTC (permalink / raw)
To: akpm; +Cc: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 442 bytes --]
Add rtc hooks to katana and workaround firmware bug.
- Now that the mv64xxx i2c and m41t00 i2c rtc drivers are in the source
base, add hooks to the katana file to use that rtc.
- A recent version of the katana firmware incorrectly changes the
mv64x60's pci vendor & device id so this patch puts back the proper values.
- Misc. cleanup and update of the default config file.
Please apply.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
[-- Attachment #2: katana_rtc.patch --]
[-- Type: text/plain, Size: 18630 bytes --]
diff -Nru a/arch/ppc/configs/katana_defconfig b/arch/ppc/configs/katana_defconfig
--- a/arch/ppc/configs/katana_defconfig 2005-03-10 09:34:32 -07:00
+++ b/arch/ppc/configs/katana_defconfig 2005-03-10 09:34:32 -07:00
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc4
-# Tue Feb 15 14:27:12 2005
+# Linux kernel version: 2.6.11
+# Tue Mar 8 17:31:00 2005
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
@@ -36,6 +36,7 @@
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -45,6 +46,7 @@
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
#
# Loadable module support
@@ -70,6 +72,7 @@
CONFIG_ALTIVEC=y
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
+# CONFIG_83xx is not set
CONFIG_PPC_STD_MMU=y
CONFIG_NOT_COHERENT_CACHE=y
@@ -93,6 +96,7 @@
# CONFIG_PRPMC750 is not set
# CONFIG_PRPMC800 is not set
# CONFIG_SANDPOINT is not set
+# CONFIG_RADSTONE_PPC7D is not set
# CONFIG_ADIR is not set
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
@@ -428,7 +432,6 @@
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
CONFIG_E100=y
-# CONFIG_E100_NAPI is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
@@ -453,6 +456,10 @@
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+CONFIG_MV643XX_ETH_2=y
#
# Ethernet (10000 Mbit)
@@ -575,7 +582,90 @@
#
# I2C support
#
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+CONFIG_SENSORS_M41T00=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
@@ -753,6 +843,7 @@
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_PRINTK_TIME is not set
#
# Security options
diff -Nru a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
--- a/arch/ppc/platforms/katana.c 2005-03-10 09:34:32 -07:00
+++ b/arch/ppc/platforms/katana.c 2005-03-10 09:34:32 -07:00
@@ -3,7 +3,7 @@
*
* Board setup routines for the Artesyn Katana cPCI boards.
*
- * Athor: Tim Montgomery <timm@artesyncp.com>
+ * Author: Tim Montgomery <timm@artesyncp.com>
* Maintained by: Mark A. Greer <mgreer@mvista.com>
*
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
@@ -50,6 +50,8 @@
static u32 katana_flash_size_0;
static u32 katana_flash_size_1;
+static u32 katana_bus_frequency;
+
unsigned char __res[sizeof(bd_t)];
/* PCI Interrupt routing */
@@ -183,44 +185,102 @@
}
static void __init
-katana_enable_ipmi(void)
+katana_setup_bridge(void)
{
- u8 reset_out;
+ struct pci_controller hose;
+ struct mv64x60_setup_info si;
+ void __iomem *vaddr;
+ int i;
+ u16 val;
+ u8 save_exclude;
- /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
- reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
- reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
- out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
-}
+ /*
+ * Some versions of the Katana firmware mistakenly change the vendor
+ * & device id fields in the bridge's pci device (visible via pci
+ * config accesses). This breaks mv64x60_init() because those values
+ * are used to identify the type of bridge that's there. Artesyn
+ * claims that the subsystem vendor/device id's will have the correct
+ * Marvell values so this code puts back the correct values from there.
+ */
+ memset(&hose, 0, sizeof(hose));
+ vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
+ setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
+ vaddr + MV64x60_PCI0_CONFIG_DATA);
+ save_exclude = mv64x60_pci_exclude_bridge;
+ mv64x60_pci_exclude_bridge = 0;
+
+ early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
+
+ if (val != PCI_VENDOR_ID_MARVELL) {
+ early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_SUBSYSTEM_VENDOR_ID, &val);
+ early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_VENDOR_ID, val);
+ early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_SUBSYSTEM_ID, &val);
+ early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
+ PCI_DEVICE_ID, val);
+ }
-static u32
-katana_bus_freq(void)
-{
- u8 bd_cfg_0;
+ mv64x60_pci_exclude_bridge = save_exclude;
+ iounmap(vaddr);
- bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0);
+ memset(&si, 0, sizeof(si));
- switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
- case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
- return 200000000;
- break;
+ si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
- case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
- return 166666666;
- break;
+ si.pci_1.enable_bus = 1;
+ si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
+ si.pci_1.pci_io.pci_base_hi = 0;
+ si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
+ si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
+ si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
+ si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
+ si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
+ si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
+ si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_1.pci_cmd_bits = 0;
+ si.pci_1.latency_timer = 0x80;
- case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
- return 133333333;
- break;
+ for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
- case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
- return 100000000;
- break;
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_NONE |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+#else
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
- default:
- return 133333333;
- break;
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_WB |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
+#endif
}
+
+ /* Lookup PCI host bridges */
+ if (mv64x60_init(&bh, &si))
+ printk(KERN_WARNING "Bridge initialization failed.\n");
+
+ pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = katana_map_irq;
+ ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
+
+ mv64x60_set_bus(&bh, 1, 0);
+ bh.hose_b->first_busno = 0;
+ bh.hose_b->last_busno = 0xff;
}
/* Bridge & platform setup routines */
@@ -356,138 +416,16 @@
}
static void __init
-katana_setup_bridge(void)
-{
- struct mv64x60_setup_info si;
- int i;
-
- memset(&si, 0, sizeof(si));
-
- si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
- si.pci_1.enable_bus = 1;
- si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
- si.pci_1.pci_io.pci_base_hi = 0;
- si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
- si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
- si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
- si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
- si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
- si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
- si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
- si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
- si.pci_1.pci_cmd_bits = 0;
- si.pci_1.latency_timer = 0x80;
-
- for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
-#if defined(CONFIG_NOT_COHERENT_CACHE)
- si.cpu_prot_options[i] = 0;
- si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
- si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
- si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
-
- si.pci_1.acc_cntl_options[i] =
- MV64360_PCI_ACC_CNTL_SNOOP_NONE |
- MV64360_PCI_ACC_CNTL_SWAP_NONE |
- MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
- MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-#else
- si.cpu_prot_options[i] = 0;
- si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
- si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
- si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
-
- si.pci_1.acc_cntl_options[i] =
- MV64360_PCI_ACC_CNTL_SNOOP_WB |
- MV64360_PCI_ACC_CNTL_SWAP_NONE |
- MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
- MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
-#endif
- }
-
- /* Lookup PCI host bridges */
- if (mv64x60_init(&bh, &si))
- printk(KERN_WARNING "Bridge initialization failed.\n");
-
- pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = katana_map_irq;
- ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
- mv64x60_set_bus(&bh, 1, 0);
- bh.hose_b->first_busno = 0;
- bh.hose_b->last_busno = 0xff;
-}
-
-#ifdef CONFIG_MTD_PHYSMAP
-
-#ifndef MB
-#define MB (1 << 20)
-#endif
-
-/*
- * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
- *
- * FLASH Amount: 128 64 32 16
- * ------------- --- -- -- --
- * Monitor: 1 1 1 1
- * Primary Kernel: 1.5 1.5 1.5 1.5
- * Primary fs: 30 30 <end> <end>
- * Secondary Kernel: 1.5 1.5 N/A N/A
- * Secondary fs: <end> <end> N/A N/A
- * User: <overlays entire FLASH except for "Monitor" section>
- */
-static int __init
-katana_setup_mtd(void)
+katana_enable_ipmi(void)
{
- u32 size;
- int ptbl_entries;
- static struct mtd_partition *ptbl;
-
- size = katana_flash_size_0 + katana_flash_size_1;
- if (!size)
- return -ENOMEM;
-
- ptbl_entries = (size >= (64*MB)) ? 6 : 4;
-
- if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
- GFP_KERNEL)) == NULL) {
-
- printk(KERN_WARNING "Can't alloc MTD partition table\n");
- return -ENOMEM;
- }
- memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
-
- ptbl[0].name = "Monitor";
- ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
- ptbl[1].name = "Primary Kernel";
- ptbl[1].offset = MTDPART_OFS_NXTBLK;
- ptbl[1].size = 0x00180000; /* 1.5 MB */
- ptbl[2].name = "Primary Filesystem";
- ptbl[2].offset = MTDPART_OFS_APPEND;
- ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
- ptbl[ptbl_entries-1].name = "User FLASH";
- ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
- ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
-
- if (size >= (64*MB)) {
- ptbl[2].size = 30*MB;
- ptbl[3].name = "Secondary Kernel";
- ptbl[3].offset = MTDPART_OFS_NXTBLK;
- ptbl[3].size = 0x00180000; /* 1.5 MB */
- ptbl[4].name = "Secondary Filesystem";
- ptbl[4].offset = MTDPART_OFS_APPEND;
- ptbl[4].size = MTDPART_SIZ_FULL;
- }
+ u8 reset_out;
- physmap_map.size = size;
- physmap_set_partitions(ptbl, ptbl_entries);
- return 0;
+ /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
+ reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
+ reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
+ out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
}
-arch_initcall(katana_setup_mtd);
-#endif
-
static void __init
katana_setup_arch(void)
{
@@ -528,6 +466,8 @@
katana_setup_peripherals();
katana_enable_ipmi();
+ katana_bus_frequency = katana_bus_freq(cpld_base);
+
printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: exit", 0);
@@ -550,7 +490,7 @@
* TCLK == SysCLK but on 64460, they are separate pins.
* SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
*/
- pdata->brg_clk_freq = min(katana_bus_freq(), MV64x60_TCLK_FREQ_MAX);
+ pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
}
#endif
@@ -606,6 +546,75 @@
return 0;
}
+#ifdef CONFIG_MTD_PHYSMAP
+
+#ifndef MB
+#define MB (1 << 20)
+#endif
+
+/*
+ * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
+ *
+ * FLASH Amount: 128 64 32 16
+ * ------------- --- -- -- --
+ * Monitor: 1 1 1 1
+ * Primary Kernel: 1.5 1.5 1.5 1.5
+ * Primary fs: 30 30 <end> <end>
+ * Secondary Kernel: 1.5 1.5 N/A N/A
+ * Secondary fs: <end> <end> N/A N/A
+ * User: <overlays entire FLASH except for "Monitor" section>
+ */
+static int __init
+katana_setup_mtd(void)
+{
+ u32 size;
+ int ptbl_entries;
+ static struct mtd_partition *ptbl;
+
+ size = katana_flash_size_0 + katana_flash_size_1;
+ if (!size)
+ return -ENOMEM;
+
+ ptbl_entries = (size >= (64*MB)) ? 6 : 4;
+
+ if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
+ GFP_KERNEL)) == NULL) {
+
+ printk(KERN_WARNING "Can't alloc MTD partition table\n");
+ return -ENOMEM;
+ }
+ memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
+
+ ptbl[0].name = "Monitor";
+ ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
+ ptbl[1].name = "Primary Kernel";
+ ptbl[1].offset = MTDPART_OFS_NXTBLK;
+ ptbl[1].size = 0x00180000; /* 1.5 MB */
+ ptbl[2].name = "Primary Filesystem";
+ ptbl[2].offset = MTDPART_OFS_APPEND;
+ ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
+ ptbl[ptbl_entries-1].name = "User FLASH";
+ ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
+ ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
+
+ if (size >= (64*MB)) {
+ ptbl[2].size = 30*MB;
+ ptbl[3].name = "Secondary Kernel";
+ ptbl[3].offset = MTDPART_OFS_NXTBLK;
+ ptbl[3].size = 0x00180000; /* 1.5 MB */
+ ptbl[4].name = "Secondary Filesystem";
+ ptbl[4].offset = MTDPART_OFS_APPEND;
+ ptbl[4].size = MTDPART_SIZ_FULL;
+ }
+
+ physmap_map.size = size;
+ physmap_set_partitions(ptbl, ptbl_entries);
+ return 0;
+}
+
+arch_initcall(katana_setup_mtd);
+#endif
+
static void
katana_restart(char *cmd)
{
@@ -672,7 +681,7 @@
seq_printf(m, "PLD rev\t\t: 0x%x\n",
in_8(cpld_base + KATANA_CPLD_PLD_VER));
seq_printf(m, "PLB freq\t: %ldMhz\n",
- (long)katana_bus_freq() / 1000000);
+ (long)katana_bus_frequency / 1000000);
seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-");
return 0;
@@ -683,7 +692,7 @@
{
u32 freq;
- freq = katana_bus_freq() / 4;
+ freq = katana_bus_frequency / 4;
printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
(long)freq / 1000000, (long)freq % 1000000);
@@ -698,6 +707,27 @@
return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
MV64x60_TYPE_MV64360);
}
+
+#if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00)
+extern ulong m41t00_get_rtc_time(void);
+extern int m41t00_set_rtc_time(ulong);
+
+static int __init
+katana_rtc_hookup(void)
+{
+ struct timespec tv;
+
+ ppc_md.get_rtc_time = m41t00_get_rtc_time;
+ ppc_md.set_rtc_time = m41t00_set_rtc_time;
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = (ppc_md.get_rtc_time)();
+ do_settimeofday(&tv);
+
+ return 0;
+}
+late_initcall(katana_rtc_hookup);
+#endif
static inline void
katana_set_bat(void)
diff -Nru a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h
--- a/arch/ppc/platforms/katana.h 2005-03-10 09:34:32 -07:00
+++ b/arch/ppc/platforms/katana.h 2005-03-10 09:34:32 -07:00
@@ -3,7 +3,8 @@
*
* Definitions for Artesyn Katana750i/3750 board.
*
- * Tim Montgomery <timm@artesyncp.com>
+ * Author: Tim Montgomery <timm@artesyncp.com>
+ * Maintained by: Mark A. Greer <mgreer@mvista.com>
*
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
* Based on code done by Mark A. Greer <mgreer@mvista.com>
@@ -221,4 +222,34 @@
#endif
-#endif /* __PPC_PLATFORMS_KATANA_H */
+static inline u32
+katana_bus_freq(void __iomem *cpld_base)
+{
+ u8 bd_cfg_0;
+
+ bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0);
+
+ switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
+ return 200000000;
+ break;
+
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
+ return 166666666;
+ break;
+
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
+ return 133333333;
+ break;
+
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
+ return 100000000;
+ break;
+
+ default:
+ return 133333333;
+ break;
+ }
+}
+
+#endif /* __PPC_PLATFORMS_KATANA_H */
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Gerhard Jaeger @ 2005-03-10 16:29 UTC (permalink / raw)
To: Matt Porter; +Cc: linuxppc-embedded
In-Reply-To: <20050310091227.B27661@cox.net>
On Thursday 10 March 2005 17:12, Matt Porter wrote:
> On Thu, Mar 10, 2005 at 08:03:56AM -0800, Eugene Surovegin wrote:
> > On Thu, Mar 10, 2005 at 11:06:53AM +0100, Gerhard Jaeger wrote:
> > > the patch has been posted in October last year (wow, thought it was in
> > > december or so):
> > > http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015811.html
> > >
> > > I think it needs some cleanup to apply correctly, but the issue is still
> > > the same - the RGMII bridge needs to be setup again after the EMAC has
> > > been reset. This problem occurs, when the speed is != 100Mbs, then
> > > the clocking for the phy is not correct.
> > > I have attached an updated patch, which first checks the PHY speed, then
> > > according to that speed the RGMII and ZMII will be setup...
> >
> > [snip]
> >
> > OK, from quick look it seems that this is infamous problem with PHYs
> > which don't generate Rx clock if there is no link.
>
> Ok, good, I was just looking an wondering if it was the same issue.
>
> > Current driver works sometimes probably just by luck.
> >
> > Gerhard, there is an experimental NAPI driver for 4xx at
> > http://kernel.ebshome.net (for current 2.4 & 2.6 BK trees). I recently
> > added full 440GX support. We (Matt and I) are thinking about
> > scraping the current driver and using my new version sometimes in the
> > future. It'd be great if you could find some time and try this new
> > driver on your board. Enable "PHY Rx clock workaround" in driver
> > config.
>
> In the meantime, I'll see how this work-around works on some platforms
> I have here.
>
> Gerhard: what's the list of 4xx systems (and phys) you have tested
> this against? I assume this patch is used on all 4xx platforms you
> support in your distro?
In the end this patch is used on our 2.4 kernel series (with backported
2.6 EMAC driver). Tested on Walnut, Ebony, Ocotoea and two custom 440gx
boards, one PHY there is the mentionend DP83865 phy and the other phy
is the AMD79C875 (same as on Ebony and Ocotea). I thought, that this
problem is somewhat phy independant and more or less related to the
way, the phy is connected - here via GMII!
Ciao,
Gerhard
^ permalink raw reply
* Re: boot time scheduling hile atomic
From: Takeharu KATO @ 2005-03-10 16:19 UTC (permalink / raw)
To: Joerg Dorchain; +Cc: linuxppc-dev
In-Reply-To: <20050310072803.GR4017@Redstar.dorchain.net>
Hi Joerg:
> I came to the same idea. This explains as well why the i386 party does
> not notice the effect, as their first interrupt happen later (different
> HZ value)
>
As far as I know, current HZ value for PPC is 1000
as same as i386 family.
Please see following:
-- include/asm-i386/param.h
1 #ifndef _ASMi386_PARAM_H
2 #define _ASMi386_PARAM_H
3
4 #ifdef __KERNEL__
5 # define HZ 1000 /* Internal kernel timer
frequency */
-- include/asm-i386/param.h
-- include/asm-ppc/param.h
1 #ifndef _ASM_PPC_PARAM_H
2 #define _ASM_PPC_PARAM_H
3
4 #ifdef __KERNEL__
5 #define HZ 1000 /* internal timer frequency */
6 #define USER_HZ 100 /* for user interfaces in
"ticks" */
-- include/asm-ppc/param.h
FYI, Kernel preemption ought not to be taken place at this point,
because preemption count is a positive number.
According to my observation, the problem occur on second call of
proc_root_init.But I could not who call it.
IIRC,the value of LR(link register) pointed at the start of BSS.
Regards,
--
Takeharu KATO
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Gerhard Jaeger @ 2005-03-10 16:24 UTC (permalink / raw)
To: Matt Porter; +Cc: linuxppc-embedded
In-Reply-To: <20050310090327.A27661@cox.net>
On Thursday 10 March 2005 17:03, Matt Porter wrote:
> On Thu, Mar 10, 2005 at 08:37:08AM +0100, Gerhard Jaeger wrote:
> > On Wednesday 09 March 2005 18:11, Sanjay Bajaj wrote:
> > > Has anybody used PPC 440GX with NS DP83865 phy? If you have or have any
> > > information to set it up, please share.
> > >
> > We're using this PHY on a custom 440GX board. Connected via GMII!
> > After setting up the RGMII bridge correctly (see manual), you also have to
> > tweak the EMAC driver. I have sent a patch (which has been rejected) a few
> > weeks ago to the list which changes the setup procedure of the EMAC to work
> > with a DP83865 PHY. THe current implementation will not work.
>
> FWIW, I did go back and see the patch from 22 October in my mbox. It's
> not rejected...just missed amongst a lot of other things. If things
> are quiet, it's best to ping in case somebody missed your patch.
>
Matt - no problem. The answer in october, I got from Eugene was, that
you guys are working on a "new" EMAC driver with NAPI support and I also
had a running setup - so - no worries ;)
Gerhard
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Gerhard Jaeger @ 2005-03-10 16:22 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
In-Reply-To: <20050310160356.GD19275@gate.ebshome.net>
On Thursday 10 March 2005 17:03, Eugene Surovegin wrote:
> On Thu, Mar 10, 2005 at 11:06:53AM +0100, Gerhard Jaeger wrote:
> > the patch has been posted in October last year (wow, thought it was in
> > december or so):
> > http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015811.html
> >
> > I think it needs some cleanup to apply correctly, but the issue is still
> > the same - the RGMII bridge needs to be setup again after the EMAC has
> > been reset. This problem occurs, when the speed is != 100Mbs, then
> > the clocking for the phy is not correct.
> > I have attached an updated patch, which first checks the PHY speed, then
> > according to that speed the RGMII and ZMII will be setup...
>
> [snip]
>
> OK, from quick look it seems that this is infamous problem with PHYs
> which don't generate Rx clock if there is no link.
>
> Current driver works sometimes probably just by luck.
>
> Gerhard, there is an experimental NAPI driver for 4xx at
> http://kernel.ebshome.net (for current 2.4 & 2.6 BK trees). I recently
> added full 440GX support. We (Matt and I) are thinking about
> scraping the current driver and using my new version sometimes in the
> future. It'd be great if you could find some time and try this new
> driver on your board. Enable "PHY Rx clock workaround" in driver
> config.
>
> Feel free to contact me directly if you have any problems with this
> driver (e.g. applying patch to an older kernel version, etc).
>
Eugene, I will give it a try ASAP. As we are using a heavily patched 2.4
kernel on the customers board, where came up, it might took some time
for making it work - but I'll keep you informed.
Thanx
Gerhard
--
Gerhard Jaeger <gjaeger@sysgo.com>
SYSGO AG Embedded and Real-Time Software
www.sysgo.com | www.elinos.com | www.pikeos.com | www.osek.de
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Matt Porter @ 2005-03-10 16:12 UTC (permalink / raw)
To: Gerhard Jaeger, linuxppc-embedded
In-Reply-To: <20050310160356.GD19275@gate.ebshome.net>
On Thu, Mar 10, 2005 at 08:03:56AM -0800, Eugene Surovegin wrote:
> On Thu, Mar 10, 2005 at 11:06:53AM +0100, Gerhard Jaeger wrote:
> > the patch has been posted in October last year (wow, thought it was in
> > december or so):
> > http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015811.html
> >
> > I think it needs some cleanup to apply correctly, but the issue is still
> > the same - the RGMII bridge needs to be setup again after the EMAC has
> > been reset. This problem occurs, when the speed is != 100Mbs, then
> > the clocking for the phy is not correct.
> > I have attached an updated patch, which first checks the PHY speed, then
> > according to that speed the RGMII and ZMII will be setup...
>
> [snip]
>
> OK, from quick look it seems that this is infamous problem with PHYs
> which don't generate Rx clock if there is no link.
Ok, good, I was just looking an wondering if it was the same issue.
> Current driver works sometimes probably just by luck.
>
> Gerhard, there is an experimental NAPI driver for 4xx at
> http://kernel.ebshome.net (for current 2.4 & 2.6 BK trees). I recently
> added full 440GX support. We (Matt and I) are thinking about
> scraping the current driver and using my new version sometimes in the
> future. It'd be great if you could find some time and try this new
> driver on your board. Enable "PHY Rx clock workaround" in driver
> config.
In the meantime, I'll see how this work-around works on some platforms
I have here.
Gerhard: what's the list of 4xx systems (and phys) you have tested
this against? I assume this patch is used on all 4xx platforms you
support in your distro?
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Eugene Surovegin @ 2005-03-10 16:03 UTC (permalink / raw)
To: Gerhard Jaeger; +Cc: linuxppc-embedded
In-Reply-To: <200503101106.53345.g.jaeger@sysgo.com>
On Thu, Mar 10, 2005 at 11:06:53AM +0100, Gerhard Jaeger wrote:
> the patch has been posted in October last year (wow, thought it was in
> december or so):
> http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015811.html
>
> I think it needs some cleanup to apply correctly, but the issue is still
> the same - the RGMII bridge needs to be setup again after the EMAC has
> been reset. This problem occurs, when the speed is != 100Mbs, then
> the clocking for the phy is not correct.
> I have attached an updated patch, which first checks the PHY speed, then
> according to that speed the RGMII and ZMII will be setup...
[snip]
OK, from quick look it seems that this is infamous problem with PHYs
which don't generate Rx clock if there is no link.
Current driver works sometimes probably just by luck.
Gerhard, there is an experimental NAPI driver for 4xx at
http://kernel.ebshome.net (for current 2.4 & 2.6 BK trees). I recently
added full 440GX support. We (Matt and I) are thinking about
scraping the current driver and using my new version sometimes in the
future. It'd be great if you could find some time and try this new
driver on your board. Enable "PHY Rx clock workaround" in driver
config.
Feel free to contact me directly if you have any problems with this
driver (e.g. applying patch to an older kernel version, etc).
--
Eugene
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Matt Porter @ 2005-03-10 16:03 UTC (permalink / raw)
To: Gerhard Jaeger; +Cc: Sanjay Bajaj, linuxppc-embedded
In-Reply-To: <200503100837.08717.g.jaeger@sysgo.com>
On Thu, Mar 10, 2005 at 08:37:08AM +0100, Gerhard Jaeger wrote:
> On Wednesday 09 March 2005 18:11, Sanjay Bajaj wrote:
> > Has anybody used PPC 440GX with NS DP83865 phy? If you have or have any
> > information to set it up, please share.
> >
> We're using this PHY on a custom 440GX board. Connected via GMII!
> After setting up the RGMII bridge correctly (see manual), you also have to
> tweak the EMAC driver. I have sent a patch (which has been rejected) a few
> weeks ago to the list which changes the setup procedure of the EMAC to work
> with a DP83865 PHY. THe current implementation will not work.
FWIW, I did go back and see the patch from 22 October in my mbox. It's
not rejected...just missed amongst a lot of other things. If things
are quiet, it's best to ping in case somebody missed your patch.
Thanks,
Matt
^ permalink raw reply
* Re: build failure for 2.6.11-mm2
From: Tom Rini @ 2005-03-10 14:33 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list
In-Reply-To: <d10a9ba3f7ed768cff5f439840c96aec@freescale.com>
On Thu, Mar 10, 2005 at 08:06:04AM -0600, Kumar Gala wrote:
> right, but if you look back in the pervious -mm builds that past, they
> also did not have mkImage but still succeeded.
>
> It appear some change is now report the lack of mkImage as a build
> error. If this is desired behavior, should we maybe look at having a
> copy of its source in the kernel tree?
I think what's happened, but I haven't verified is that Andrew took an
incorrect patch to make 'mkuboot.sh', which invokes mkimage to produce a
uImage, fail if mkimage isn't found. This isn't right. The problem the
patch was trying to fix is that mkuboot.sh will say that it made a
uImage, even if mkimage isn't found.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Re: build failure for 2.6.11-mm2
From: Kumar Gala @ 2005-03-10 14:06 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: Tom Rini, linuxppc-dev list
In-Reply-To: <20050310082639.GA19275@gate.ebshome.net>
right, but if you look back in the pervious -mm builds that past, they
also did not have mkImage but still succeeded.
It appear some change is now report the lack of mkImage as a build
error. If this is desired behavior, should we maybe look at having a
copy of its source in the kernel tree?
- kumar
On Mar 10, 2005, at 2:26 AM, Eugene Surovegin wrote:
> On Thu, Mar 10, 2005 at 02:10:04AM -0600, Kumar Gala wrote:
> > Do you have any ideas on what changes occurred in the makefiles to
> > cause the uImage related failures:
> >
> > http://l4x.org/k/?d=2173
>
> This looks like mkimage is just not present on build host. I don't
> think it's included anywhere in kernel tree, so it must be installed
> separately.
>
> --
> Eugene
^ permalink raw reply
* RE: [Bugme-new] [Bug 4310] New: ppc 8260 fcc ethernet driver cann ot read LXT971 PHY id
From: Balasaygun, Oray (Oray) @ 2005-03-10 13:45 UTC (permalink / raw)
To: 'Andrew Morton', Balasaygun, Oray (Oray)
Cc: linuxppc-dev, Nikoonezhad, Danesh (Danesh),
Balasaygun, Oray (Oray), netdev
Andrew,
I retested the patch. It works fine.
Oray
-----Original Message-----
From: Andrew Morton [mailto:akpm@osdl.org]
Sent: Wednesday, March 09, 2005 6:49 PM
To: Balasaygun, Oray (Oray)
Cc: oray@lucent.com; linuxppc-dev@ozlabs.org; netdev@oss.sgi.com;
dnikoonezhad@lucent.com
Subject: Re: [Bugme-new] [Bug 4310] New: ppc 8260 fcc ethernet driver
cann ot read LXT971 PHY id
"Balasaygun, Oray (Oray)" <oray@lucent.com> wrote:
>
> Attached please find the diff output of the fcc_enet.c that I am running with and the original 2.6.10 version of it.
Patch looks reasonable, if unconvnetionally presented ;) Thanks.
I fixed a bit of whitespace and converted mii_display_config() and
mii_relink() to take an unsigned long arguments as they're now a tasklet
callback.
Perhaps you could retest this sometime, please?
From: "Balasaygun, Oray (Oray)" <oray@lucent.com>
- fix for Bug 4310
- The fcc_enet.c, as distributed in 2.6.10, does not compile. Evidently
the 2.6 kernel no longer supports the schedule_task() and "struct
tq_struct" to go with it. Lines 73 through and including 96 of the
diffout file show the changes I made to port schedule_task() into
tasklet_schedule(). I should have reported this as a bug too but I
forgot about it.
- customize fcc_enet.c to work with my custom board. These changes are
conditional on CONFIG_EON8260 being defined.
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
25-akpm/arch/ppc/8260_io/fcc_enet.c | 91 ++++++++++++++++++++++++++++++------
1 files changed, 78 insertions(+), 13 deletions(-)
diff -puN arch/ppc/8260_io/fcc_enet.c~ppc-8260-fcc-ethernet-driver-cannot-read-lxt971-phy-id arch/ppc/8260_io/fcc_enet.c
--- 25/arch/ppc/8260_io/fcc_enet.c~ppc-8260-fcc-ethernet-driver-cannot-read-lxt971-phy-id 2005-03-09 15:40:26.000000000 -0800
+++ 25-akpm/arch/ppc/8260_io/fcc_enet.c 2005-03-09 15:47:23.000000000 -0800
@@ -177,6 +177,54 @@ static int fcc_enet_set_mac_address(stru
#define CMX1_CLK_MASK ((uint)0xff000000)
#endif
+#ifdef CONFIG_EON8260
+
+#define MAKE_BITMASK(n) (1 << (31-n))
+
+#define PA8 MAKE_BITMASK(8)
+#define PA9 MAKE_BITMASK(9)
+
+#define PB18 MAKE_BITMASK(18)
+#define PB19 MAKE_BITMASK(19)
+#define PB20 MAKE_BITMASK(20)
+#define PB21 MAKE_BITMASK(21)
+#define PB22 MAKE_BITMASK(22)
+#define PB23 MAKE_BITMASK(23)
+#define PB24 MAKE_BITMASK(24)
+#define PB25 MAKE_BITMASK(25)
+#define PB26 MAKE_BITMASK(26)
+#define PB27 MAKE_BITMASK(27)
+#define PB28 MAKE_BITMASK(28)
+#define PB29 MAKE_BITMASK(29)
+#define PB30 MAKE_BITMASK(30)
+#define PB31 MAKE_BITMASK(31)
+
+#define PB2_TXER PB31
+#define PB2_RXDV PB30
+#define PB2_TXEN PB29
+#define PB2_RXER PB28
+#define PB2_COL PB27
+#define PB2_CRS PB26
+#define PB2_TXDAT (PB22 | PB23 | PB24 | PB25)
+#define PB2_RXDAT (PB18 | PB19 | PB20 | PB21)
+#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
+ PB2_RXER | PB2_RXDV | PB2_TXER)
+#define PB2_PSORB1 (PB2_TXEN)
+#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
+#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
+
+/* CLK16 (PC16) is receive, CLK15 (PC17) is transmit */
+
+#define PC_F2RXCLK ((uint)0x00008000)
+#define PC_F2TXCLK ((uint)0x00004000)
+
+#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
+#define CMX2_CLK_ROUTE (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK15)
+#define CMX2_CLK_MASK ((uint)0x00ff0000)
+
+#else /* #ifdef CONFIG_EON8260 */
+
/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
* but there is little variation among the choices.
*/
@@ -208,6 +256,8 @@ static int fcc_enet_set_mac_address(stru
#define CMX2_CLK_MASK ((uint)0x00ff0000)
#endif
+#endif /* #ifdef CONFIG_EON8260 */
+
/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
* but there is little variation among the choices.
*/
@@ -234,7 +284,11 @@ static int fcc_enet_set_mac_address(stru
/* MII status/control serial interface.
*/
-#ifdef CONFIG_TQM8260
+#if defined (CONFIG_EON8260)
+/* EON8260 has MDIO and MDCK on PC31 and PC30 respectively */
+#define PC_MDIO ((uint)0x00000001)
+#define PC_MDCK ((uint)0x00000002)
+#elif defined (CONFIG_TQM8260)
/* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
#define PC_MDIO ((uint)0x00000002)
#define PC_MDCK ((uint)0x00000001)
@@ -268,7 +322,7 @@ static fcc_info_t fcc_ports[] = {
#ifdef CONFIG_FCC1_ENET
{ 0, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
(PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
-# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
+# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272) || defined(CONFIG_EON8260)
PC_MDIO, PC_MDCK },
# else
0x00000004, 0x00000100 },
@@ -277,7 +331,7 @@ static fcc_info_t fcc_ports[] = {
#ifdef CONFIG_FCC2_ENET
{ 1, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
(PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
-# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
+# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272) || defined(CONFIG_EON8260)
PC_MDIO, PC_MDCK },
# elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260)
0x00400000, 0x00200000 },
@@ -288,7 +342,7 @@ static fcc_info_t fcc_ports[] = {
#ifdef CONFIG_FCC3_ENET
{ 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
(PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
-# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
+# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272) || defined(CONFIG_EON8260)
PC_MDIO, PC_MDCK },
# else
0x00000001, 0x00000040 },
@@ -329,7 +383,7 @@ struct fcc_enet_private {
uint phy_id_done;
uint phy_status;
phy_info_t *phy;
- struct tq_struct phy_task;
+ struct tasklet_struct phy_task;
uint sequence_done;
@@ -1191,8 +1245,9 @@ static void mii_display_status(struct ne
printk(".\n");
}
-static void mii_display_config(struct net_device *dev)
+static void mii_display_config(unsigned long arg)
{
+ struct net_device *dev = (struct net_device *)arg;
volatile struct fcc_enet_private *fep = dev->priv;
uint s = fep->phy_status;
@@ -1222,8 +1277,9 @@ static void mii_display_config(struct ne
fep->sequence_done = 1;
}
-static void mii_relink(struct net_device *dev)
+static void mii_relink(unsigned long arg)
{
+ struct net_device *dev = (struct net_device *)arg;
struct fcc_enet_private *fep = dev->priv;
int duplex;
@@ -1246,18 +1302,18 @@ static void mii_queue_relink(uint mii_re
{
struct fcc_enet_private *fep = dev->priv;
- fep->phy_task.routine = (void *)mii_relink;
+ fep->phy_task.func = mii_relink;
fep->phy_task.data = dev;
- schedule_task(&fep->phy_task);
+ tasklet_schedule(&fep->phy_task);
}
static void mii_queue_config(uint mii_reg, struct net_device *dev)
{
struct fcc_enet_private *fep = dev->priv;
- fep->phy_task.routine = (void *)mii_display_config;
+ fep->phy_task.func = mii_display_config;
fep->phy_task.data = dev;
- schedule_task(&fep->phy_task);
+ tasklet_schedule(&fep->phy_task);
}
@@ -1464,6 +1520,9 @@ static int __init fec_enet_init(void)
return -ENOMEM;
cep = dev->priv;
+ cep->phy_task.next = NULL;
+ cep->phy_task.state = 0;
+ cep->phy_task.count.counter = 0;
spin_lock_init(&cep->lock);
cep->fip = fip;
@@ -1698,6 +1757,11 @@ init_fcc_param(fcc_info_t *fip, struct n
* non-static part of the address.
*/
eap = (unsigned char *)&(ep->fen_paddrh);
+#if defined(CONFIG_EON8260)
+ for (i = 5; i >=0 ; i--) {
+ *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
+ }
+#else /* if defined(CONFIG_EON8260) */
for (i=5; i>=0; i--) {
#ifdef CONFIG_SBC82xx
if (i == 5) {
@@ -1718,6 +1782,7 @@ init_fcc_param(fcc_info_t *fip, struct n
*eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
}
}
+#endif /* if defined(CONFIG_EON8260) */
ep->fen_taddrh = 0;
ep->fen_taddrm = 0;
@@ -1940,10 +2005,10 @@ mii_send_receive(fcc_info_t *fip, uint c
{
FCC_PDATC_MDC(1);
retval <<= 1;
- if (io->iop_pdatc & fip->fc_mdio)
- retval++;
udelay(1);
FCC_PDATC_MDC(0);
+ if (io->iop_pdatc & fip->fc_mdio)
+ retval++;
udelay(1);
}
}
_
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Gerhard Jaeger @ 2005-03-10 10:06 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
On Thursday 10 March 2005 09:34, Eugene Surovegin wrote:
> On Thu, Mar 10, 2005 at 08:37:08AM +0100, Gerhard Jaeger wrote:
>
> [snip]
>
> > I have sent a patch (which has been rejected) a few
> > weeks ago to the list which changes the setup procedure of the EMAC to work
> > with a DP83865 PHY. THe current implementation will not work.
>
> Gerhard, I wasn't able to find that patch in the patch tracker
> (http://ozlabs.org/ppc32-patches/) and I missed it when you posted it.
>
> Could you re-send it or post a link to the relevant message in
> archive.
>
Hi Eugene,
the patch has been posted in October last year (wow, thought it was in
december or so):
http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015811.html
I think it needs some cleanup to apply correctly, but the issue is still
the same - the RGMII bridge needs to be setup again after the EMAC has
been reset. This problem occurs, when the speed is != 100Mbs, then
the clocking for the phy is not correct.
I have attached an updated patch, which first checks the PHY speed, then
according to that speed the RGMII and ZMII will be setup...
Gerhard
--
Gerhard Jaeger <gjaeger@sysgo.com>
SYSGO AG Embedded and Real-Time Software
www.sysgo.com | www.elinos.com | www.pikeos.com | www.osek.de
[PATCH][PPC32]IBM-EMAC GMII
This patch fixes problems with a Gigabit PHY being connected via GMII
interface. It seems, that the RGMII bridge needs to be setup again after
the EMAC has been reset. It causes also some troubles to enable RX & TX
without having a link. Tested on PPC440GP, GX and PPC405 boards.
Signed-off-by: Gerhard Jaeger <gjaeger@sysgo.com>
--- linux-2.6.11/drivers/net/ibm_emac/ibm_emac_core.c.orig 2004-10-18 23:53:06.000000000 +0200
+++ linux-2.6.11/drivers/net/ibm_emac/ibm_emac_core.c 2004-10-22 08:43:12.000000000 +0200
@@ -1018,28 +1018,45 @@ static int emac_start_xmit(struct sk_buf
return 0;
}
+static int emac_setup_mii_bridges(struct ocp_enet_private *fep )
+{
+ /* set speed (default is 10Mb) */
+ switch (fep->phy_mii.speed) {
+ case SPEED_1000:
+ if (fep->rgmii_dev)
+ emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
+ 1000);
+ break;
+ case SPEED_100:
+ if (fep->rgmii_dev)
+ emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
+ 100);
+ if (fep->zmii_dev)
+ emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
+ 100);
+ break;
+ case SPEED_10:
+ default:
+ if (fep->rgmii_dev)
+ emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
+ 10);
+ if (fep->zmii_dev)
+ emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
+ 10);
+ }
+ return 0;
+}
+
static int emac_adjust_to_link(struct ocp_enet_private *fep)
{
emac_t *emacp = fep->emacp;
unsigned long mode_reg;
- int full_duplex, speed;
-
- full_duplex = 0;
- speed = SPEED_10;
/* set mode register 1 defaults */
mode_reg = EMAC_M1_DEFAULT;
- /* Read link mode on PHY */
- if (fep->phy_mii.def->ops->read_link(&fep->phy_mii) == 0) {
- /* If an error occurred, we don't deal with it yet */
- full_duplex = (fep->phy_mii.duplex == DUPLEX_FULL);
- speed = fep->phy_mii.speed;
- }
-
-
/* set speed (default is 10Mb) */
- switch (speed) {
+ switch (fep->phy_mii.speed) {
case SPEED_1000:
mode_reg |= EMAC_M1_JUMBO_ENABLE | EMAC_M1_RFS_16K;
if (fep->rgmii_dev) {
@@ -1050,41 +1067,28 @@ static int emac_adjust_to_link(struct oc
mode_reg |= EMAC_M1_MF_1000GPCS;
else
mode_reg |= EMAC_M1_MF_1000MBPS;
-
- emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
- 1000);
}
break;
case SPEED_100:
mode_reg |= EMAC_M1_MF_100MBPS | EMAC_M1_RFS_4K;
- if (fep->rgmii_dev)
- emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
- 100);
- if (fep->zmii_dev)
- emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
- 100);
break;
case SPEED_10:
default:
mode_reg = (mode_reg & ~EMAC_M1_MF_100MBPS) | EMAC_M1_RFS_4K;
- if (fep->rgmii_dev)
- emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
- 10);
- if (fep->zmii_dev)
- emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
- 10);
}
- if (full_duplex)
+ if (fep->phy_mii.duplex)
mode_reg |= EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_IST;
else
mode_reg &= ~(EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_ILE);
- LINK_DEBUG(("%s: adjust to link, speed: %d, duplex: %d, opened: %d\n",
- fep->ndev->name, speed, full_duplex, fep->opened));
-
+ LINK_DEBUG(("%s: adjust to link, speed: %d, duplex: %d, opened: %d\n",
+ fep->ndev->name, fep->phy_mii.speed,
+ fep->phy_mii.full_duplex, fep->opened));
+
printk(KERN_INFO "%s: Speed: %d, %s duplex.\n",
- fep->ndev->name, speed, full_duplex ? "Full" : "Half");
+ fep->ndev->name, fep->phy_mii.speed,
+ (fep->phy_mii.duplex == DUPLEX_FULL) ? "Full" : "Half");
if (fep->opened)
out_be32(&emacp->em0mr1, mode_reg);
@@ -1312,15 +1316,23 @@ static void emac_reset_configure(struct
* soft reset without a PHY clock present.
*/
if (fep->phy_mii.def->ops->poll_link(&fep->phy_mii)) {
+
+ /* Read link mode on PHY */
+ fep->phy_mii.def->ops->read_link(&fep->phy_mii);
+
/* Reset the EMAC */
out_be32(&emacp->em0mr0, EMAC_M0_SRST);
- udelay(20);
+
+ /* it seems, that this is necessary for some configs
+ * to come out of the reset
+ */
+ emac_setup_mii_bridges( fep );
+
for (i = 0; i < 100; i++) {
if ((in_be32(&emacp->em0mr0) & EMAC_M0_SRST) == 0)
break;
udelay(10);
}
-
if (i >= 100) {
printk(KERN_ERR "%s: Cannot reset EMAC\n",
fep->ndev->name);
@@ -1630,7 +1642,10 @@ static int emac_open(struct net_device *
}
/* Kick the chip rx & tx channels into life */
spin_lock_irq(&fep->lock);
- emac_kick(fep);
+
+ /* no link, no need to kick the interface */
+ if (netif_carrier_ok(fep->ndev))
+ emac_kick(fep);
spin_unlock_irq(&fep->lock);
netif_start_queue(dev);
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Eugene Surovegin @ 2005-03-10 8:34 UTC (permalink / raw)
To: Gerhard Jaeger; +Cc: linuxppc-embedded
In-Reply-To: <200503100837.08717.g.jaeger@sysgo.com>
On Thu, Mar 10, 2005 at 08:37:08AM +0100, Gerhard Jaeger wrote:
[snip]
> I have sent a patch (which has been rejected) a few
> weeks ago to the list which changes the setup procedure of the EMAC to work
> with a DP83865 PHY. THe current implementation will not work.
Gerhard, I wasn't able to find that patch in the patch tracker
(http://ozlabs.org/ppc32-patches/) and I missed it when you posted it.
Could you re-send it or post a link to the relevant message in
archive.
Thanks,
Eugene
^ permalink raw reply
* Re: build failure for 2.6.11-mm2
From: Eugene Surovegin @ 2005-03-10 8:26 UTC (permalink / raw)
To: Kumar Gala; +Cc: Tom Rini, linuxppc-dev list
In-Reply-To: <d5ec5d6983bd5bb2276f3d73c49edc3e@freescale.com>
On Thu, Mar 10, 2005 at 02:10:04AM -0600, Kumar Gala wrote:
> Do you have any ideas on what changes occurred in the makefiles to
> cause the uImage related failures:
>
> http://l4x.org/k/?d=2173
This looks like mkimage is just not present on build host. I don't
think it's included anywhere in kernel tree, so it must be installed
separately.
--
Eugene
^ permalink raw reply
* build failure for 2.6.11-mm2
From: Kumar Gala @ 2005-03-10 8:10 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-dev list
Tom,
Do you have any ideas on what changes occurred in the makefiles to
cause the uImage related failures:
http://l4x.org/k/?d=2173
- kumar
^ permalink raw reply
* Re: PPC 440GX with NS DP83865 phy
From: Gerhard Jaeger @ 2005-03-10 7:37 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: Sanjay Bajaj
In-Reply-To: <0007F077BB3476449151699150E8FEA205928C@exchange.tsi-telsys.com>
On Wednesday 09 March 2005 18:11, Sanjay Bajaj wrote:
> Has anybody used PPC 440GX with NS DP83865 phy? If you have or have any
> information to set it up, please share.
>
We're using this PHY on a custom 440GX board. Connected via GMII!
After setting up the RGMII bridge correctly (see manual), you also have to
tweak the EMAC driver. I have sent a patch (which has been rejected) a few
weeks ago to the list which changes the setup procedure of the EMAC to work
with a DP83865 PHY. THe current implementation will not work.
Regards
Gerhard
--
Gerhard Jaeger <gjaeger@sysgo.com>
SYSGO AG Embedded and Real-Time Software
www.sysgo.com | www.elinos.com | www.pikeos.com | www.osek.de
^ permalink raw reply
* Re: RFC/Commit: New ocp id for CANbus devs
From: Andrey Volkov @ 2005-03-10 7:35 UTC (permalink / raw)
To: Kumar Gala; +Cc: Sylvain Munaut, paulus, linuxppc-embedded
In-Reply-To: <6bac59cd11e3d6fd005b8630e67bee33@freescale.com>
Ok, accepted, I'll be delayed until driver will be done.
Andrey
Kumar Gala wrote:
> I would assume you plan on moving your driver over to the driver model
> which will make all of this moot.
>
> So I think Sylvain's suggestion of allocating a number for the time
> being makes the most sense until we get 52xx convert over to platform
> devices.
>
> - kumar
>
> On Mar 10, 2005, at 12:57 AM, Andrey Volkov wrote:
>
>> Sylvain Munaut wrote:
>> >
>> >> Sylvain, but what I wish now - only single number
>> >> (until driver will done).
>> >
>> > If you only need a temporary ocp ID, just fix it youself in your local
>> > tree, no need to try to push that upstream.
>>
>> I already use it as temp, but I don't want pitfalls in future (when
>> smb. take this number).
>>
>> Also, since CAN ocp present not only in MPC5200, but, AFAIK, in another
>> chips too, IMHO, it must be well known constant id.
>>
>> Regards
>> Andrey
>
>
>
^ permalink raw reply
* [PATCH] ppc32: Consolidate Kconfig support for 83xx (fwd)
From: Kumar Gala @ 2005-03-10 7:30 UTC (permalink / raw)
To: linuxppc-embedded
---------- Forwarded message ----------
Date: Wed, 9 Mar 2005 21:31:05 -0600 (CST)
From: Kumar Gala <galak@freescale.com>
To: akpm@osdl.org
Cc: linuxppc-embedded@ozlab.org, trini@kernel.crashing.org
Subject: [PATCH] ppc32: Consolidate Kconfig support for 83xx
Andrew,
(Note this removes arch/ppc/platforms/83xx/Kconfig)
Consolidate Kconfig options between arch/ppc/platforms/83xx/Kconfig and
arch/ppc/Kconfig at Tom Rini's request.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig 2005-03-09 21:23:40 -06:00
+++ b/arch/ppc/Kconfig 2005-03-09 21:23:41 -06:00
@@ -228,7 +228,6 @@
If in doubt, say Y here.
source arch/ppc/platforms/4xx/Kconfig
-source arch/ppc/platforms/83xx/Kconfig
source arch/ppc/platforms/85xx/Kconfig
config PPC64BRIDGE
@@ -476,7 +475,7 @@
choice
prompt "Machine Type"
- depends on (6xx && !83xx) || POWER3 || POWER4
+ depends on 6xx || POWER3 || POWER4
default PPC_MULTIPLATFORM
---help---
Linux currently supports several different kinds of PowerPC-based
@@ -643,6 +642,11 @@
much but it's only been tested on this board version. I think this
board is also known as IceCube.
+config MPC834x_SYS
+ bool "Freescale MPC834x SYS"
+ help
+ This option enables support for the MPC 834x SYS evaluation board.
+
endchoice
config PQ2ADS
@@ -665,7 +669,7 @@
config 8260
bool "CPM2 Support" if WILLOW
- depends on 6xx && !83xx
+ depends on 6xx
default y if TQM8260 || RPX8260 || EST8260 || SBS8260 || SBC82xx || PQ2FADS
help
The MPC8260 is a typical embedded CPU made by Motorola. Selecting
@@ -681,6 +685,14 @@
The MPC8272 CPM has a different internal dpram setup than other CPM2
devices
+config 83xx
+ bool
+ default y if MPC834x_SYS
+
+config MPC834x
+ bool
+ default y if MPC834x_SYS
+
config CPM2
bool
depends on 8260 || MPC8560 || MPC8555
@@ -720,7 +732,8 @@
bool
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE || \
PRPMC750 || K2 || PRPMC800 || LOPEC || \
- (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D
+ (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D || \
+ MPC834x_SYS
default y
config FORCE
diff -Nru a/arch/ppc/platforms/83xx/Kconfig b/arch/ppc/platforms/83xx/Kconfig
--- a/arch/ppc/platforms/83xx/Kconfig 2005-03-09 21:23:40 -06:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,30 +0,0 @@
-config 83xx
- bool "PowerQUICC II Pro (83xx) Support"
- depends on 6xx
-
-menu "Freescale 83xx options"
- depends on 83xx
-
-choice
- prompt "Machine Type"
- depends on 83xx
- default MPC834x_SYS
-
-config MPC834x_SYS
- bool "Freescale MPC834x SYS"
- help
- This option enables support for the MPC 834x SYS evaluation board.
-
-endchoice
-
-config MPC834x
- bool
- depends on MPC834x_SYS
- default y
-
-config PPC_GEN550
- bool
- depends on 83xx
- default y
-
-endmenu
^ permalink raw reply
* Re: [PATCH] gianfar: Update Marvell PHY name
From: Kumar Gala @ 2005-03-10 7:30 UTC (permalink / raw)
To: Jeff Garzik; +Cc: Netdev, inuxppc-embedded List
In-Reply-To: <Pine.LNX.4.61.0503040150480.16127@blarg.somerset.sps.mot.com>
Jeff,
Just wondering if this got lost? Might be moot depending what=20
likelihood of getting Andy's PHY Abstraction Layer changes into the=20
kernel.
- kumar
On Mar 4, 2005, at 1:55 AM, Kumar Gala wrote:
> Jeff,
>
> This patch updates the name identifier to list both of the Marvell =
PHYs
> that are supported.
>
> Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
>
> ---
> diff -Nru a/drivers/net/gianfar_phy.c b/drivers/net/gianfar_phy.c
> --- a/drivers/net/gianfar_phy.c 2005-03-02 14:20:27 -06:00
> +++ b/drivers/net/gianfar_phy.c 2005-03-02 14:20:27 -06:00
> @@ -572,7 +572,7 @@
> =A0static struct phy_info phy_info_marvell =3D {
> =A0=A0=A0=A0=A0=A0=A0 .phy_id =A0=A0=A0=A0=A0=A0=A0 =3D 0x01410c00,
> =A0=A0=A0=A0=A0=A0=A0 .phy_id_mask=A0=A0=A0 =3D 0xffffff00,
> -=A0=A0=A0=A0=A0=A0 .name=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =3D "Marvell =
88E1101",
> +=A0=A0=A0=A0=A0=A0 .name=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =3D "Marvell =
88E1101/88E1111",
> =A0=A0=A0=A0=A0=A0=A0 .features=A0=A0=A0=A0=A0=A0 =3D =
MII_GBIT_FEATURES,
> =A0=A0=A0=A0=A0=A0=A0 .config_aneg=A0=A0=A0 =3D &marvell_config_aneg,
> =A0=A0=A0=A0=A0=A0=A0 .read_status=A0=A0=A0 =3D &marvell_read_status,
> _______________________________________________
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^ permalink raw reply
* Re: boot time scheduling hile atomic
From: Joerg Dorchain @ 2005-03-10 7:28 UTC (permalink / raw)
To: Takeharu KATO; +Cc: linuxppc-dev
In-Reply-To: <422FD24F.4070108@jp.fujitsu.com>
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On Thu, Mar 10, 2005 at 01:51:27PM +0900, Takeharu KATO wrote:
> > I am more wondering what in proc_root_init or immediately after it
> > causes a call to the exit_work syscall.
> >
> This is not called by proc_root_init.
> It seems be called by timer interrupt
> (I confirmed it by viewing trap number in
> interrupt context with ICE).
I came to the same idea. This explains as well why the i386 party does
not notice the effect, as their first interrupt happen later (different
HZ value)
At this point, I was out of clue, so thank you for your help.
Bye,
Joerg
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^ permalink raw reply
* Re: RFC/Commit: New ocp id for CANbus devs
From: Kumar Gala @ 2005-03-10 7:10 UTC (permalink / raw)
To: Andrey Volkov; +Cc: Sylvain Munaut, paulus, linuxppc-embedded
In-Reply-To: <422FEFBE.4070903@varma-el.com>
I would assume you plan on moving your driver over to the driver model
which will make all of this moot.
So I think Sylvain's suggestion of allocating a number for the time
being makes the most sense until we get 52xx convert over to platform
devices.
- kumar
On Mar 10, 2005, at 12:57 AM, Andrey Volkov wrote:
> Sylvain Munaut wrote:
> >
> >> Sylvain, but what I wish now - only single number
> >> (until driver will done).
> >
> > If you only need a temporary ocp ID, just fix it youself in your
> local
> > tree, no need to try to push that upstream.
>
> I already use it as temp, but I don't want pitfalls in future (when
> smb. take this number).
>
> Also, since CAN ocp present not only in MPC5200, but, AFAIK, in another
> chips too, IMHO, it must be well known constant id.
>
> Regards
> Andrey
^ permalink raw reply
* Re: RFC/Commit: New ocp id for CANbus devs
From: Andrey Volkov @ 2005-03-10 6:57 UTC (permalink / raw)
To: Sylvain Munaut, Kumar Gala; +Cc: paulus, linuxppc-embedded
In-Reply-To: <422F534A.1020107@246tNt.com>
Sylvain Munaut wrote:
>
>> Sylvain, but what I wish now - only single number
>> (until driver will done).
>
> If you only need a temporary ocp ID, just fix it youself in your local
> tree, no need to try to push that upstream.
I already use it as temp, but I don't want pitfalls in future (when
smb. take this number).
Also, since CAN ocp present not only in MPC5200, but, AFAIK, in another
chips too, IMHO, it must be well known constant id.
Regards
Andrey
^ permalink raw reply
* Re: boot time scheduling hile atomic
From: Takeharu KATO @ 2005-03-10 4:51 UTC (permalink / raw)
To: Joerg Dorchain; +Cc: linuxppc-dev
In-Reply-To: <20050304075703.GA15637@Redstar.dorchain.net>
Hi
Joerg Dorchain wrote:
> On Thu, Mar 03, 2005 at 03:18:32PM +0100, Joerg Dorchain wrote:
>
>>>>scheduling while atomic: swapper/0x00000002/0
>>>>Call trace:
>>>> [c0007620] dump_stack+0x18/0x28
>>>> [c01de704] schedule+0x678/0x67c
>>>> [c0004500] syscall_exit_work+0x108/0x10c
>>>> [c02a97b4] proc_root_init+0x168/0x174
>>>> [ff847288] 0xff847288
>>>> [c02945e8] start_kernel+0x144/0x170
>>>> [00003a30] 0x3a30
>>
>>I'll do tonight.
>
> I am more wondering what in proc_root_init or immediately after it
> causes a call to the exit_work syscall.
>
This is not called by proc_root_init.
It seems be called by timer interrupt
(I confirmed it by viewing trap number in
interrupt context with ICE).
As long as I investigate the problem,
proc_root_init is called twice.
At first time, it's called from
start_kernel in init/main.c.
Second case, it seems to be called by some kind of
init call facility.
proc_root_init is not init_call function, I could not
figure out concretely why it called twice.
I will investigate the problem as long as I can.
I wishes this report to become your help.
Regards,
--
Takeharu KATO
Fujitsu Limited
Email:kato.takeharu at jp.fujitsu.com
^ permalink raw reply
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