* Re: Heartbeat apps thoughts
From: Geert Uytterhoeven @ 2005-03-14 16:02 UTC (permalink / raw)
To: Joerg Dorchain; +Cc: linuxppc-dev list
In-Reply-To: <20050314154504.GA7267@Redstar.dorchain.net>
On Mon, 14 Mar 2005, Joerg Dorchain wrote:
> I am pondering a heartbeat functionality implementation. Currently, I
> have a patch that adds a few line to the timer interrupt to switch the
> led on and off when appropriate.
>
> On the list, there were opinions that switching the led on and off would
> be best done via userspace. While I in principle agree, I have some
> considerations:
And then we (kernel hackers) cannot use it anymore to see whether interrupts
are still working...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* I2C RTC recommendations?
From: Ed Goforth @ 2005-03-14 16:35 UTC (permalink / raw)
To: linuxppc-embedded
I'm looking to add a RTC to a custom 440gx-based board. The board
developer has indicated that they would prefer use an I2C device (vs.
eg. something like the DS1743 that's on the reference board).
Does anyone have any recommendations or comments? The primary
consideration is that it be easily supported with a 2.4.x kernel. The
only important function is the timekeeper function (though a WD
capability might be useful in the future).
Thanks in advance,
Ed
^ permalink raw reply
* Re: DMA appears broken in 2.6.11 for Mac 7200
From: linuxppcdev @ 2005-03-14 17:52 UTC (permalink / raw)
To: linuxppc-dev
Ben Said:
> On Mon, 2005-03-14 at 03:51 +0000, linuxppcdev@qbjnet.com wrote:
> > Just updated a couple of old Mac 7200 (601) boxen and ran into trouble with
> > the ide driver and a promise PDC20267 card.
> >
> > The very same drives and card work fine on a 9500 but hang on a 7200. If
> > I set the kernel arg ide=nodma I get in the dmesg:
> > ide_setup: ide=nodma : Prevented DMA
> > and the 7200 boots and runs fine.
> >
> > Another suspect, the mace ethernet driver (which also appears to use DMA)
> > doesn't work on the 7200 with 2.6.11 but does with 2.4.28 and it works
> > with 2.6.11 on the 9500.
>
> Interesting. Not sure what's up, though. Those old machines were known
> to have bugs relative to cache coherency... also check wetehr we are
> setting the cache line size properly in PCI devices. You can also try to
> disable use of PCI memory write & invalidate command in all devices.
Here is some info from a 7200 booted off of 2.6.11:
dmesg
Total memory = 112MB; using 256kB for hash table (at c04c0000)
Linux version 2.6.11.2 (root@dev) (gcc version 3.3.4 (Debian 1:3.3.4-9ubuntu5))
#8 Sun Mar 13 12:50:26 CST 2005
Found a Grand Central mac-io controller, rev: 2, mapped at 0xfdf00000
PowerMac motherboard: PowerMac 7200/7300
Cache coherency enabled for bandit/PSX
Found Bandit PCI host bridge at 0xf2000000. Firmware bus number: 0->0
nvram: OF partition at 0x1800
nvram: XP partition at 0x1300
nvram: NR partition at 0x1400
On node 0 totalpages: 28672
DMA zone: 28672 pages, LIFO batch:7
Normal zone: 0 pages, LIFO batch:1
HighMem zone: 0 pages, LIFO batch:1
Built 1 zonelists
Kernel command line: root=/dev/hda2 video=platinumfb ide=nodma
ide_setup: ide=nodma : Prevented DMA
System has 32 possible interrupts
PID hash table entries: 512 (order: 9, 8192 bytes)
.
.
.
Forcing PCI IDE into native mode: 0000:00:0d.0
Rewrite of PROGIF failed !
.
.
PDC20267: IDE controller at PCI slot 0000:00:0d.0
PDC20267: chipset revision 2
PDC20267: ROM enabled at 0x80860000
PDC20267: 100% native mode on irq 23
PDC20267: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
ide0: BM-DMA at 0x0480-0x0487, BIOS settings: hda:pio, hdb:pio
ide1: BM-DMA at 0x0488-0x048f, BIOS settings: hdc:pio, hdd:pio
Probing IDE interface ide0...
.
.
eth0: Digital DS21143 Tulip rev 33 at c805a000, 00:40:F6:84:F8:C0, IRQ 25.
pmac: can't request resource 0!
lspci -vv
0000:00:0b.0 Host bridge: Apple Computer Inc. Bandit PowerPC host bridge (rev 03)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 32, Cache Line Size: 0x08 (32 bytes)
Interrupt: pin ? routed to IRQ 22
0000:00:0d.0 RAID bus controller: Promise Technology, Inc. 20267 (rev 02)
Subsystem: Promise Technology, Inc.: Unknown device 4d32
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Interrupt: pin A routed to IRQ 23
Region 0: I/O ports at 04f0 [size=80860000]
Region 1: I/O ports at 04e0 [size=4]
Region 2: I/O ports at 04d0 [size=8]
Region 3: I/O ports at 04c0 [size=4]
Region 4: I/O ports at 0480 [size=64]
Region 5: Memory at 80840000 (32-bit, non-prefetchable) [size=128K]
Expansion ROM at 00010000 [disabled]
Capabilities: [58] Power Management version 1
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
.
.
0000:00:0f.0 Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 21)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (5000ns min, 10000ns max), Cache Line Size: 0x08 (32 bytes)
Interrupt: pin A routed to IRQ 25
Region 0: I/O ports at 0400 [size=80800000]
Region 1: Memory at 80871000 (32-bit, non-prefetchable) [size=128]
Expansion ROM at 00040000 [disabled]
0000:00:10.0 Class ff00: Apple Computer Inc. Grand Central I/O (rev 02)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+
Latency: 32, Cache Line Size: 0x08 (32 bytes)
Interrupt: pin ? routed to IRQ 22
Region 0: Memory at f3000000 (32-bit, non-prefetchable)
Does this help at all?
Bob
^ permalink raw reply
* Re:problem opening I2C device on MPC8260
From: David Bruce @ 2005-03-14 19:18 UTC (permalink / raw)
To: linuxppc-embedded
Look back into the February logs of this group that was having simular
discussions.
In short:
a.) 2.6 has some problems with the I2C. You may have to port over 2.4
i2c code. I don't know the specific details.
b.) you need an adapter interface to create your device(s) (/dev/i2c-0).
See ./drivers/i2c/i2c-pm826.c. You should be able to use this untouched.
It is part of the configuration in 2.4.x.
c.) The 2.4 version of i2c-algo-8260.c has a potential bug where all the
__pa()'s need to be replaced by iopa().
I am using 2.4.24 of the ELDK and had problems with the i2c. Items b & c
corrected them except that with "b" I had to load it *after* boot as a
module. Don't know why but it works and have successfully used the i2c
since.
--
David Bruce
MIT Lincoln Laboratory
244 Wood Street
Lexington, MA 02420
781.981.3863
mailto:dbruce@ll.mit.edu
^ permalink raw reply
* Re: [RFC][PATCH] combining header files
From: Linas Vepstas @ 2005-03-14 19:36 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc64-dev, linuxppc-dev
In-Reply-To: <20050310134216.5b9b27ef.sfr@canb.auug.org.au>
On Thu, Mar 10, 2005 at 01:42:16PM +1100, Stephen Rothwell was heard to remark:
> On Wed, 9 Mar 2005 14:01:09 -0600 Linas Vepstas <linas@austin.ibm.com> wrote:
> >
> > Why not #include <asm-generic/whatever.h> instead?
>
> Because I am talking about similarities between ppc and ppc64 not ppc64
> and the generic code (though there may be some of those to be exploited as
> well).
Hmm. well, yes. I just figured that since you're looking at this anyway,
may as well look to see if it can be made generic.
--linas
^ permalink raw reply
* Re: mpc8560ads PCI bus
From: Greg Weeks @ 2005-03-14 21:24 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <4235B13C.9010604@anagramm.de>
Switch bank SW1 switch #4 was on which stops config accesses from making
it on the bus. It works fine now.
Greg Weeks
Clemens Koller wrote:
> Hello, Greg,
>
> I am working on an mpc8540_ads-like board and recently, I ran into data
> corruption problems with a Silicon Motion SM501 (Rev AA) PCI graphics
> card. From my current point of view it seems that Kernel 2.6.11 PCI
> works well. I am about to check the hardware and signal integrity.
>
> BTW: I am working with a Promise Ultra-TX133 IDE controller (PDC20269)
> which is fine with 66MHz PCICLK.
>
> Greets,
>
> Clemens
>
>
>> Has anyone else tried to get the PCI bus working on the mpc8560ads
>> board at 2.6.11? The card enumerates, but the I/O resource regions
>> aren't getting set up.
>>
>> -bash-2.05b# lspci -vv
>> 00:03.0 Unknown mass storage controller: Silicon Image, Inc.
>> (formerly CMD Technology Inc) PCI0680 Ultra ATA-133 Host Controller
>> (rev 02)
>> Subsystem: Silicon Image, Inc. (formerly CMD Technology Inc)
>> PCI0680 Ultra ATA-133 Host Controller
>> Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
>> ParErr- Stepping- SERR- FastB2B-
>> Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium
>> >TAbort- <TAbort- <MAbort- >SERR- <PERR+
>> Interrupt: pin A routed to IRQ 100
>> Region 0: I/O ports at <unassigned> [disabled]
>> Region 1: I/O ports at <unassigned> [disabled]
>> Region 2: I/O ports at <unassigned> [disabled]
>> Region 3: I/O ports at <unassigned> [disabled]
>> Region 4: I/O ports at <unassigned> [disabled]
>> Capabilities: [60] Power Management version 2
>> Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA
>> PME(D0-,D1-,D2-,D3hot-,D3cold-)
>> Status: D0 PME-Enable- DSel=0 DScale=2 PME-
>>
>> Greg Weeks
>> _______________________________________________
>> Linuxppc-embedded mailing list
>> Linuxppc-embedded@ozlabs.org
>> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>>
>
^ permalink raw reply
* Re: RFC: PHY Abstraction Layer II
From: Andy Fleming @ 2005-03-15 0:41 UTC (permalink / raw)
To: James Chapman; +Cc: netdev, David S. Miller, linuxppc-embedded
In-Reply-To: <4230D1AC.5070506@katalix.com>
On Mar 10, 2005, at 17:01, James Chapman wrote:
> Hi Andy,
>
> Can you elaborate on why this phy abstraction is needed?
>
> In your original post, you mentioned that you were going to post a
> patch to show how your code would be hooked up in an existing net
> driver. Did I miss it? It would help in understanding the pros and cons
> of using genphy over using plain old mii.c.
Hi James,
I haven't posted it yet, since it's a large patch (it deletes a lot of
code from my driver), but I can give a basic overview of how my driver
hooks into this code:
1) The driver connects to the PHY when opened, calling phy_connect, and
then clears some bits to declare functionality it doesn't support (my
driver, for instance, does not support gigabit in half-duplex mode).
2) The driver implements a function which reads the speed/duplex
settings, and modifies the controller registers as appropriate (also
bringing the carrier up and down depending on link state). My driver
needs to note whether it's gigabit or not (for GMII vs MII mode), and
the duplex (to set the MAC full or half).
Both of those steps are very straightforward. The PHY layer will
invoke the callback whenever the link state changes, so the controller
will always be up-to-date.
3) The third step is the part that can make things a little messier.
My driver implements a second driver for the MDIO bus, which is
connected through its registers. This bus needs to be registered, and
the driver also needs to register. Then some code needs to be written
to deal with initialization, and takedown. I can send out that patch
anytime, if there's demand.
>
> btw, I recently posted a patch to add GigE support to mii.c which is
> in Jeff's netdev-2.6 queue. Some register definitions were added in
> mii.h that will collide with yours.
Yeah, I ran in to some of those. I can't remember whether they're in
the patch or not, I suspect not. I will have to submit a new patch to
cover those (I just changed my code to use your definitions).
Andy
^ permalink raw reply
* Re: mpc8560ads PCI bus
From: Kumar Gala @ 2005-03-15 5:25 UTC (permalink / raw)
To: Greg Weeks; +Cc: linuxppc-embedded
In-Reply-To: <423600F9.5050705@timesys.com>
Greg good to hear, I was about to comment on the fact that PCI based=20
support had been working on the 8540/8560 ADS systems.
- kumar
On Mar 14, 2005, at 3:24 PM, Greg Weeks wrote:
> Switch bank SW1 switch #4 was on which stops config accesses from=20
> making
> it on the bus. It works fine now.
>
> Greg Weeks
>
> Clemens Koller wrote:
>
> > Hello, Greg,
> >
> > I am working on an mpc8540_ads-like board and recently, I ran into=20=
> data
> > corruption problems with a Silicon Motion SM501 (Rev AA) PCI=20
> graphics
> > card. =46rom my current point of view it seems that Kernel 2.6.11 =
PCI
> > works well. I am about to check the hardware and signal integrity.
> >
> > BTW: I am working with a Promise Ultra-TX133 IDE controller=20
> (PDC20269)
> > which is fine with 66MHz PCICLK.
> >
> > Greets,
> >
> > Clemens
> >
> >
> >> Has anyone else tried to get the PCI bus working on the mpc8560ads
> >> board at 2.6.11? The card enumerates, but the I/O resource regions
> >> aren't getting set up.
> >>
> >> -bash-2.05b# lspci -vv
> >> 00:03.0 Unknown mass storage controller: Silicon Image, Inc.
> >> (formerly CMD Technology Inc) PCI0680 Ultra ATA-133 Host Controller
> >> (rev 02)
> >>=A0=A0=A0=A0=A0=A0=A0 Subsystem: Silicon Image, Inc. (formerly CMD =
Technology Inc)
> >> PCI0680 Ultra ATA-133 Host Controller
> >>=A0=A0=A0=A0=A0=A0=A0 Control: I/O- Mem- BusMaster- SpecCycle- =
MemWINV- VGASnoop-
> >> ParErr- Stepping- SERR- FastB2B-
> >>=A0=A0=A0=A0=A0=A0=A0 Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- =
DEVSEL=3Dmedium
> >> >TAbort- <TAbort- <MAbort- >SERR- <PERR+
> >>=A0=A0=A0=A0=A0=A0=A0 Interrupt: pin A routed to IRQ 100
> >>=A0=A0=A0=A0=A0=A0=A0 Region 0: I/O ports at <unassigned> =
[disabled]
> >>=A0=A0=A0=A0=A0=A0=A0 Region 1: I/O ports at <unassigned> =
[disabled]
> >>=A0=A0=A0=A0=A0=A0=A0 Region 2: I/O ports at <unassigned> =
[disabled]
> >>=A0=A0=A0=A0=A0=A0=A0 Region 3: I/O ports at <unassigned> =
[disabled]
> >>=A0=A0=A0=A0=A0=A0=A0 Region 4: I/O ports at <unassigned> =
[disabled]
> >>=A0=A0=A0=A0=A0=A0=A0 Capabilities: [60] Power Management version 2
> >>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Flags: PMEClk- DSI+ =
D1+ D2+ AuxCurrent=3D0mA
> >> PME(D0-,D1-,D2-,D3hot-,D3cold-)
> >>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Status: D0 =
PME-Enable- DSel=3D0 DScale=3D2 PME-
> >>
> >> Greg Weeks
> >> _______________________________________________
> >> Linuxppc-embedded mailing list
> >> Linuxppc-embedded@ozlabs.org
> >> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >>
> >
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* [PATCH] boot time scheduling w hile atomic fix
From: Takeharu KATO @ 2005-03-15 10:24 UTC (permalink / raw)
To: linuxppc-dev; +Cc: tmm
Hi
I've fixed the problem by changing the implementation of
kernel_thread function.
> Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
> scheduling while atomic: swapper/0x00000002/0
> Call trace:
> [c0007620] dump_stack+0x18/0x28
> [c01de704] schedule+0x678/0x67c
> [c0004500] syscall_exit_work+0x108/0x10c
> [c02a97b4] proc_root_init+0x168/0x174
> [ff847288] 0xff847288
> [c02945e8] start_kernel+0x144/0x170
> [00003a30] 0x3a30
As I mentioned before, it was caused by calling kernel_thread function via
trap call.
So, I've replaced the implementation of kernel_thread with function call like as
other architectures.
I tested this patch on PowerPC440GP (ebony evaluation board).
Please apply this patch.
I show the boot log for your information:
-- boot-log
Linux/PPC load: console=ttyS0,9600 nfsroot=192.168.0.1:/opt/fje/devkit/ppc/440/0
Uncompressing Linux...done.
Now booting the kernel
Linux version 2.6.11 (tkato@XXXX) (gcc version 3.4.0 20040331 (prerelease))5
IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))
Built 1 zonelists
Kernel command line: console=ttyS0,9600 nfsroot=192.168.0.1:/opt/fje/devkit/ppc0
PID hash table entries: 1024 (order: 10, 16384 bytes)
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 126720k available (2064k kernel code, 600k data, 332k init, 0k highmem)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
NET: Registered protocol family 16
PCI: Probing PCI hardware
SCSI subsystem initialized
usbcore: registered new driver usbfs
usbcore: registered new driver hub
i8042.c: i8042 controller self test timeout.
Serial: 8250/16550 driver $Revision: 1.90 $ 6 ports, IRQ sharing enabled
ttyS0 at MMIO 0x0 (irq = 0) is a 16550A
ttyS1 at MMIO 0x0 (irq = 1) is a 16550A
io scheduler noop registered
io scheduler anticipatory registered
[snip]
-- boot-log
Regards,
--
Takeharu KATO
Fujitsu Limited
Email:kato.takeharu at jp.fujitsu.com
Signed-off-by: Takeharu KATO <kato.takeharu@jp.fujitsu.com>
diff -Nupr linux-2.6.11/arch/ppc/kernel/misc.S linux-2.6.11-preempt/arch/ppc/kernel/misc.S
--- linux-2.6.11/arch/ppc/kernel/misc.S 2005-03-11 17:26:14.000000000 +0900
+++ linux-2.6.11-preempt/arch/ppc/kernel/misc.S 2005-03-15 17:57:30.000000000 +0900
@@ -1125,36 +1125,23 @@ _GLOBAL(cvt_df)
stfd 0,-4(r5)
blr
#endif
-
/*
- * Create a kernel thread
- * kernel_thread(fn, arg, flags)
+ * void kernel_thread_helper(void)
+ * This gets run with r13 containing the
+ * function to call, and r14 containing
+ * the "args".
+ * These register is set in ``kernel_thread'' function in
+ * arch/ppc/kernel/process.c.
+ * Note:
+ * Registers used for arguments for this function should NOT be caller-saves.
*/
-_GLOBAL(kernel_thread)
+_GLOBAL(kernel_thread_helper)
stwu r1,-16(r1)
- stw r30,8(r1)
- stw r31,12(r1)
- mr r30,r3 /* function */
- mr r31,r4 /* argument */
- ori r3,r5,CLONE_VM /* flags */
- oris r3,r3,CLONE_UNTRACED>>16
- li r4,0 /* new sp (unused) */
- li r0,__NR_clone
- sc
- cmpwi 0,r3,0 /* parent or child? */
- bne 1f /* return if parent */
- li r0,0 /* make top-level stack frame */
- stwu r0,-16(r1)
- mtlr r30 /* fn addr in lr */
- mr r3,r31 /* load arg and call fn */
+ mtlr r13
+ mr r3,r14
blrl
- li r0,__NR_exit /* exit if function returns */
- li r3,0
- sc
-1: lwz r30,8(r1)
- lwz r31,12(r1)
- addi r1,r1,16
- blr
+ bl do_exit
+ /* Never return here */
/*
* This routine is just here to keep GCC happy - sigh...
diff -Nupr linux-2.6.11/arch/ppc/kernel/process.c linux-2.6.11-preempt/arch/ppc/kernel/process.c
--- linux-2.6.11/arch/ppc/kernel/process.c 2005-03-11 17:23:13.000000000 +0900
+++ linux-2.6.11-preempt/arch/ppc/kernel/process.c 2005-03-15 17:57:31.000000000 +0900
@@ -405,6 +405,31 @@ void prepare_to_copy(struct task_struct
#endif /* CONFIG_SPE */
preempt_enable();
}
+/*
+ * Kernel thread relevant functions
+ */
+extern void kernel_thread_helper(void);
+/*
+ * Create a kernel thread
+ */
+long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ /* We use r13,14 for arguments for kernel_thread_helper.
+ * Because registers used for arguments for this function
+ * should NOT be caller-saves.
+ */
+ regs.gpr[13] = (unsigned long) fn;
+ regs.gpr[14] = (unsigned long) arg;
+
+ regs.nip = (unsigned long) kernel_thread_helper;
+ regs.msr = MSR_KERNEL;
+
+ /* Ok, create the new process.. */
+ return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
+}
/*
* Copy a thread..
^ permalink raw reply
* mtd maps
From: Greg Weeks @ 2005-03-15 12:22 UTC (permalink / raw)
To: linuxppc-embedded
Are mtd maps still in drivers/mtd/maps or has that all moved to the
platform code? I have an mtd map for the mpc8560ads but it's in mtd/maps.
Greg W
^ permalink raw reply
* Interrupts handling?
From: Garcia Jérémie @ 2005-03-15 13:14 UTC (permalink / raw)
To: linuxppc-dev
Hi everybody,
Although I am a newbie in linux powerPC development, I am in charge of a =
related project.
The project is the following: I have to move a vXWorks application to a =
Linux (montavista) environnment with a 405EP processor. Unfotunately, my =
knowledges are very limited in BSP and with all the board specific =
functions (device drivers too...).
In my application, we assign IRQ only at its early beginning and we =
never change them after. Furthermore, this application uses an OS API =
layer in order to make it independant of the OS used. For exemple we =
encapsulate all the OS calls in this layer ; as that we theoretically =
only have to change this file to use another OS. To finish, we use POSIX =
pthreads to get an equivalent of vxWorks tasks.
Giving that, here are my questions:
- is it possible to write a driver in this "file" (OS API Layer) or =
wherever I want?
- do I need to use kernel modules even if I need to register my driver =
only one time?
- is it possible for my application to register itself a driver or is =
it only a "kernel job"?
- I have to map other vxWorks routines as "intEnable", "intDisable" =
which respectively enable/disable specified interrupt bit : may I use =
the linux equivalent "enable_irq" and "disqble_irq" and that wherever =
and whenever I want? (same question for the "request_irq" routine)=20
Tks a lot for your precious help cause over here I am really alone on =
that project and none use Linux!
J=E9r=E9mie
^ permalink raw reply
* Re: Newer laptops & CPU speed
From: Joerg Dorchain @ 2005-03-15 14:03 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, debian-powerpc@lists.debian.org
In-Reply-To: <1110767622.5787.215.camel@gaston>
[-- Attachment #1: Type: text/plain, Size: 1074 bytes --]
On Mon, Mar 14, 2005 at 01:33:42PM +1100, Benjamin Herrenschmidt wrote:
> It seems the new laptops are booting with CPU set to low
> speed. /proc/cpuinfo outputs the wrong fequency (thinks it's high speed)
> but bogomips shows that it's running at about half speed. This patch
> against 2.6.11 (will not apply on 2.6.10) adds proper cpufreq support so
> that the boot speed is recognized (fixing /proc/cpuinfo output) and so
> you can acutally use cpufreq interface & utilities to switch to full
> speed (I recommend powernowd).
>
> This is completely untested as I don't have access to any of those new
> models yet, so I'm waiting for some feedback before submitting upstream.
My ibook G4 boots at low speed. /proc/cpuinfo shows 666MHz and a smiliar
bogomips value. Nevertheless, the cpu frequency scaler works, i.e. set
it to performance to be at high speed after boot up, or, as I currently
do, use the userspace governor and powernowd. All this is without your
patch (Did not try it yet, my ibook lacks internet) on linus' 2.6.11.
Bye,
Joerg
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: I2C RTC recommendations?
From: Babarovic Ivica @ 2005-03-15 14:43 UTC (permalink / raw)
To: egoforth, linuxppc-embedded
In-Reply-To: <4235BD6A.5000004@gmail.com>
Ed Goforth wrote:
> I'm looking to add a RTC to a custom 440gx-based board. The board
> developer has indicated that they would prefer use an I2C device (vs.
> eg. something like the DS1743 that's on the reference board).
I got my board equipped with Epson's RX-8025 SA/NB RTC module.
I managed to get it working with a few hacks to a 8564 RTC driver
from Stefan Eletzhofer This RTC module is also from Epson.
So far everything works fine. I don't really know why board designers
decided for it but I suppose the main concern was price. :D
regards,
Ivica
^ permalink raw reply
* modem control for 8xx serial
From: David Ho @ 2005-03-15 15:19 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
Has anyone implemented modem control in arch/ppc/8xx_io/serial.c. I don't
want to reinvent the wheel if someone's already done it. I'll be glad to
do the dirty work and submit it if anyone is interested.
Thanks, David H.
^ permalink raw reply
* Re: Interrupts handling?
From: James Chapman @ 2005-03-15 16:47 UTC (permalink / raw)
To: Garcia Jérémie; +Cc: linuxppc-dev
In-Reply-To: <D4FDDD1349B5AC46B68FC26AD8AF42D6226B11@exnet.3il.fr>
Garcia Jérémie wrote:
> Hi everybody,
>
> Although I am a newbie in linux powerPC development, I am in charge
> of a related project.
>
> The project is the following: I have to move a vXWorks application
> to a Linux (montavista) environnment with a 405EP
> processor. Unfotunately, my knowledges are very limited in BSP and
> with all the board specific functions (device drivers too...).
>
> In my application, we assign IRQ only at its early beginning and we
> never change them after.
What sort of device does your application need to talk to?
You need to separate your "application" into kernel and userspace parts.
Hooking up interrupt handlers would be done by a device driver.
Depending on what your device is, there might already be a Linux device
driver for it.
> Furthermore, this application uses an OS
> API layer in order to make it independant of the OS used. For
> exemple we encapsulate all the OS calls in this layer ; as that we
> theoretically only have to change this file to use another OS.
Nice theory but it's unlikely to cope with the paradigm shift of moving
from vxworks to Linux. You'll need to change your application to use
Unix system calls to access the device rather than making direct BSP
calls that it does today.
> To
> finish, we use POSIX pthreads to get an equivalent of vxWorks tasks.
The pthread code should be straightforward to port into a Linux
userspace application. However, if it touches the device (messes with
irqs etc) then bigger changes might be needed. I've seen some vxworks
code that combines device driver and application functions in one big
blob. Linux enforces separation.
> Giving that, here are my questions:
>
> - is it possible to write a driver in this "file" (OS API Layer) or
> wherever I want?
I don't really understand the question. Linux device drivers live in the
kernel. They may be statically linked in the kernel or they may be
dynamically loaded on-demand by the kernel. Your userspace pthread
application would be another separately linked application. You can't
call kernel C functions directly from your application like you can call
BSP or device driver functions in RTOS applications.
> - do I need to use kernel modules even if I need to register my
> driver only one time?
Kernel modules are just shared libraries that are linked in at runtime
by the kernel. It doesn't matter whether you implement a Linux driver as
a kernel module or not. Actually, Linux device drivers can often be
built statically or as kernel modules, selectable at kernel compile time.
> - is it possible for my application to register itself a driver or
> is it only a "kernel job"?
If you mean can your application load a driver into the kernel then the
answer is yes. But it's often automatic. It might happen, for example,
when your application opens a device file of your driver.
If you mean can your application be a device driver for the kernel then
the answer is no.
> - I have to map other vxWorks routines as "intEnable", "intDisable"
> which respectively enable/disable specified interrupt bit : may I
> use the linux equivalent "enable_irq" and "disqble_irq" and that
> wherever and whenever I want? (same question for the
> "request_irq" routine)
This is kernel code. I suggest you try to study how Linux device drivers
work. Some books are available on the subject. Google.
Hope I helped.
/james
^ permalink raw reply
* [PATCH 1/3] PPC440EP SoC and Bamboo board support
From: Wade Farnsworth @ 2005-03-15 17:17 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 211 bytes --]
Hello all,
This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
board. Any comments would be appreciated.
Regards,
Wade Farnsworth
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ppc.patch --]
[-- Type: text/x-patch, Size: 82336 bytes --]
diff -uprN linux-2.6.11-bk7/arch/ppc/boot/simple/Makefile linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/Makefile
--- linux-2.6.11-bk7/arch/ppc/boot/simple/Makefile 2005-03-11 16:25:16.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/Makefile 2005-03-14 09:49:18.000000000 -0700
@@ -61,6 +61,12 @@ zimageinitrd-$(CONFIG_IBM_OPENBIOS) := z
end-$(CONFIG_EMBEDDEDBOOT) := embedded
misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o
+ zimage-$(CONFIG_BAMBOO) := zImage-TREE
+zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE
+ end-$(CONFIG_BAMBOO) := bamboo
+ entrypoint-$(CONFIG_BAMBOO) := 0x01000000
+ extra.o-$(CONFIG_BAMBOO) := pibs.o
+
zimage-$(CONFIG_EBONY) := zImage-TREE
zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE
end-$(CONFIG_EBONY) := ebony
diff -uprN linux-2.6.11-bk7/arch/ppc/boot/simple/pibs.c linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/pibs.c
--- linux-2.6.11-bk7/arch/ppc/boot/simple/pibs.c 2005-03-02 00:38:08.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/pibs.c 2005-03-11 16:26:19.000000000 -0700
@@ -91,9 +91,11 @@ load_kernel(unsigned long load_addr, int
mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
-#ifdef CONFIG_440GX
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
+#endif
+#ifdef CONFIG_440GX
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
diff -uprN linux-2.6.11-bk7/arch/ppc/configs/bamboo_defconfig linux-2.6.11-bk7-440ep/arch/ppc/configs/bamboo_defconfig
--- linux-2.6.11-bk7/arch/ppc/configs/bamboo_defconfig 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/configs/bamboo_defconfig 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,910 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.11-rc5
+# Wed Mar 2 16:46:31 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+
+#
+# IBM 4xx options
+#
+# CONFIG_EBONY is not set
+# CONFIG_LUAN is not set
+# CONFIG_OCOTEA is not set
+CONFIG_BAMBOO=y
+CONFIG_440EP=y
+CONFIG_440_FPU=y
+CONFIG_IBM440EP_ERR42=y
+CONFIG_IBM_OCP=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="ip=on"
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+CONFIG_BLK_DEV_CMD64X=y
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_IBM_EMAC_ERRMSG is not set
+CONFIG_IBM_EMAC_RXB=128
+CONFIG_IBM_EMAC_TXB=128
+CONFIG_IBM_EMAC_FGAP=8
+CONFIG_IBM_EMAC_SKBRES=0
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+CONFIG_NATSEMI=y
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=y
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+
+#
+# USB ATM/DSL drivers
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+CONFIG_BDI_SWITCH=y
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/cputable.c linux-2.6.11-bk7-440ep/arch/ppc/kernel/cputable.c
--- linux-2.6.11-bk7/arch/ppc/kernel/cputable.c 2005-03-11 16:25:16.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/cputable.c 2005-03-11 16:26:19.000000000 -0700
@@ -841,6 +841,26 @@ struct cpu_spec cpu_specs[] = {
#endif /* CONFIG_40x */
#ifdef CONFIG_44x
+ { /* 440EP Rev. A */
+ .pvr_mask = 0xf0000fff,
+ .pvr_value = 0x40000850,
+ .cpu_name = "440EP Rev. A",
+ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB,
+ .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ },
+ { /* 440EP Rev. B */
+ .pvr_mask = 0xf0000fff,
+ .pvr_value = 0x400008d3,
+ .cpu_name = "440EP Rev. B",
+ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB,
+ .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ },
{ /* 440GP Rev. B */
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000440,
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/entry.S linux-2.6.11-bk7-440ep/arch/ppc/kernel/entry.S
--- linux-2.6.11-bk7/arch/ppc/kernel/entry.S 2005-03-02 00:38:25.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/entry.S 2005-03-11 16:26:19.000000000 -0700
@@ -216,6 +216,7 @@ syscall_dotrace_cont:
lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
mtlr r10
addi r9,r1,STACK_FRAME_OVERHEAD
+ PPC440EP_ERR42
blrl /* Call handler */
.globl ret_from_syscall
ret_from_syscall:
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/head_44x.S linux-2.6.11-bk7-440ep/arch/ppc/kernel/head_44x.S
--- linux-2.6.11-bk7/arch/ppc/kernel/head_44x.S 2005-03-02 00:37:51.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/head_44x.S 2005-03-11 16:26:19.000000000 -0700
@@ -228,6 +228,16 @@ skpinv: addi r4,r4,1 /* Increment */
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
+#ifdef CONFIG_440_FPU
+ /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
+ mfspr r2,SPRN_CCR0
+ lis r3,0xffef
+ ori r3,r3,0xffff
+ and r2,r2,r3
+ mtspr SPRN_CCR0,r2
+ isync
+#endif /* CONFIG_440_FPU */
+
/*
* This is where the main kernel code starts.
*/
@@ -426,7 +436,16 @@ interrupt_base:
PROGRAM_EXCEPTION
/* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_440_FPU
+ /* FPU code from arch/ppc/kernel/head.S */
+ START_EXCEPTION(FloatingPointUnavailable)
+ NORMAL_EXCEPTION_PROLOG
+ bne load_up_fpu
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_EE_LITE(0x2010, KernelFP)
+#else
EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif /* CONFIG_440_FPU */
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
@@ -669,6 +688,85 @@ finish_tlb_load:
mfspr r10, SPRG0
rfi /* Force context change */
+#ifdef CONFIG_440_FPU
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+load_up_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ sync
+ mtmsr r5 /* enable use of fpu now */
+ isync
+
+ addi r6,0,0
+ addis r3,r6,last_task_used_math@ha
+ lwz r4,last_task_used_math@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want last_task_used_math->thread */
+ SAVE_32FPRS(0, r4)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r4)
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r10,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r10 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+ /* enable use of FP after return */
+ mfspr r5,SPRG3 /* current task's THREAD (phys) */
+ lwz r4,THREAD_FPEXC_MODE(r5)
+ ori r9,r9,MSR_FP /* enable FP for current */
+ or r9,r9,r4
+ lfd fr0,THREAD_FPSCR-4(r5)
+ mtfsf 0xff,fr0
+ REST_32FPRS(0, r5)
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_math@l(r3)
+
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ REST_4GPRS(3, r11)
+ lwz r10,_CCR(r11)
+ REST_GPR(1, r11)
+ mtcrf 0xff,r10
+ lwz r10,_LINK(r11)
+ mtlr r10
+ REST_GPR(10, r11)
+ mtspr SRR1,r9
+ mtspr SRR0,r12
+ REST_GPR(9, r11)
+ REST_GPR(12, r11)
+ lwz r11,GPR11(r11)
+ sync
+ rfi
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+KernelFP:
+ lwz r3,_MSR(r1)
+ ori r3,r3,MSR_FP
+ stw r3,_MSR(r1) /* enable use of FP after return */
+ lis r3,86f@h
+ ori r3,r3,86f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+86: .string "floating point used in kernel (task=%p, pc=%x)\n"
+ .align 4,0
+#endif /* CONFIG_440_FPU */
+
/*
* Global functions
*/
@@ -684,10 +782,37 @@ _GLOBAL(giveup_altivec)
/*
* extern void giveup_fpu(struct task_struct *prev)
*
- * The 44x core does not have an FPU.
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
*/
_GLOBAL(giveup_fpu)
+#ifdef CONFIG_440_FPU
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ mtmsr r5 /* enable use of fpu now */
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32FPRS(0, r3)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r3)
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r3,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r3 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+ li r5,0
+ lis r4,last_task_used_math@ha
+ stw r5,last_task_used_math@l(r4)
+ blr
+#else
blr
+#endif /* CONFIG_440_FPU */
/*
* extern void abort(void)
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/misc.S linux-2.6.11-bk7-440ep/arch/ppc/kernel/misc.S
--- linux-2.6.11-bk7/arch/ppc/kernel/misc.S 2005-03-11 16:25:16.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/misc.S 2005-03-11 16:26:19.000000000 -0700
@@ -1147,6 +1147,7 @@ _GLOBAL(kernel_thread)
stwu r0,-16(r1)
mtlr r30 /* fn addr in lr */
mr r3,r31 /* load arg and call fn */
+ PPC440EP_ERR42
blrl
li r0,__NR_exit /* exit if function returns */
li r3,0
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/Kconfig linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Kconfig
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/Kconfig 2005-03-02 00:37:48.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Kconfig 2005-03-11 16:26:19.000000000 -0700
@@ -83,6 +83,11 @@ config OCOTEA
help
This option enables support for the IBM PPC440GX evaluation board.
+config BAMBOO
+ bool "Bamboo"
+ help
+ This option enables support for the IBM PPC440EP evaluation board.
+
endchoice
config EP405PC
@@ -113,6 +118,11 @@ config 440SP
depends on LUAN
default y
+config 440EP
+ bool
+ depends on BAMBOO
+ default y
+
config 440
bool
depends on 440GP || 440SP
@@ -123,6 +133,16 @@ config 440A
depends on 440GX
default y
+config 440_FPU
+ bool
+ depends on 440EP
+ default y
+
+config IBM440EP_ERR42
+ bool
+ depends on 440EP
+ default y
+
# All 405-based cores up until the 405GPR and 405EP have this errata.
config IBM405_ERR77
bool
@@ -142,7 +162,7 @@ config BOOKE
config IBM_OCP
bool
- depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+ depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || BAMBOO
default y
config XILINX_OCP
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/Makefile linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Makefile
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/Makefile 2005-03-02 00:38:25.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Makefile 2005-03-11 16:26:19.000000000 -0700
@@ -2,6 +2,7 @@
# Makefile for the PowerPC 4xx linux kernel.
obj-$(CONFIG_ASH) += ash.o
+obj-$(CONFIG_BAMBOO) += bamboo.o
obj-$(CONFIG_CPCI405) += cpci405.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_EP405) += ep405.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
obj-$(CONFIG_440GP) += ibm440gp.o
obj-$(CONFIG_440GX) += ibm440gx.o
obj-$(CONFIG_440SP) += ibm440sp.o
+obj-$(CONFIG_440EP) += ibm440ep.o
obj-$(CONFIG_405EP) += ibm405ep.o
obj-$(CONFIG_405GPR) += ibm405gpr.o
obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.c linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.c
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.c 2005-03-14 15:33:16.000000000 -0700
@@ -0,0 +1,451 @@
+/*
+ * arch/ppc/platforms/4xx/bamboo.c
+ *
+ * Bamboo board specific routines
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/initrd.h>
+#include <linux/irq.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/ethtool.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ocp.h>
+#include <asm/pci-bridge.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+#include <asm/bootinfo.h>
+#include <asm/ppc4xx_pic.h>
+#include <asm/ppcboot.h>
+
+#include <syslib/gen550.h>
+#include <syslib/ibm440gx_common.h>
+#include <syslib/ibm440ep_common.h>
+
+/*
+ * This is a horrible kludge, we eventually need to abstract this
+ * generic PHY stuff, so the standard phy mode defines can be
+ * easily used from arch code.
+ */
+#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
+
+bd_t __res;
+
+static struct ibm44x_clocks clocks __initdata;
+
+/*
+ * Bamboo external IRQ triggering/polarity settings
+ */
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
+};
+
+static void __init
+bamboo_calibrate_decr(void)
+{
+ unsigned int freq;
+
+ if (mfspr(SPRN_CCR1) & CCR1_TCS)
+ freq = BAMBOO_TMRCLK;
+ else
+ freq = clocks.cpu;
+
+ ibm44x_calibrate_decr(freq);
+
+}
+
+static int
+bamboo_show_cpuinfo(struct seq_file *m)
+{
+ seq_printf(m, "vendor\t\t: IBM\n");
+ seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
+
+ return 0;
+}
+
+static inline int
+bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
+ { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
+ { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
+ { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
+ };
+
+ const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void __init bamboo_set_emacdata(void)
+{
+ unsigned char * selection1_base;
+ struct ocp_def *def;
+ struct ocp_func_emac_data *emacdata;
+ u8 selection1_val;
+ int mode;
+
+ selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
+ selection1_val = readb(selection1_base);
+ iounmap((void *) selection1_base);
+ if (BAMBOO_SEL_MII(selection1_val))
+ mode = PHY_MODE_MII;
+ else if (BAMBOO_SEL_RMII(selection1_val))
+ mode = PHY_MODE_RMII;
+ else
+ mode = PHY_MODE_SMII;
+
+ /* Set mac_addr and phy mode for each EMAC */
+
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+ emacdata = def->additions;
+ memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+ emacdata->phy_mode = mode;
+
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
+ emacdata = def->additions;
+ memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
+ emacdata->phy_mode = mode;
+}
+
+static int
+bamboo_exclude_device(unsigned char bus, unsigned char devfn)
+{
+ return (bus == 0 && devfn == 0);
+}
+
+static unsigned long
+bamboo_ptm1_memory(unsigned long in_size)
+{
+ if (in_size == PPC44x_MEM_SIZE_8M)
+ return PPC44x_MEM_SIZE_8M;
+
+ if ((in_size > PPC44x_MEM_SIZE_8M) && (in_size <= PPC44x_MEM_SIZE_16M))
+ return PPC44x_MEM_SIZE_16M;
+
+ if ((in_size > PPC44x_MEM_SIZE_16M) && (in_size <= PPC44x_MEM_SIZE_32M))
+ return PPC44x_MEM_SIZE_32M;
+
+ if ((in_size > PPC44x_MEM_SIZE_32M) && (in_size <= PPC44x_MEM_SIZE_64M))
+ return PPC44x_MEM_SIZE_64M;
+
+ if ((in_size > PPC44x_MEM_SIZE_64M) && (in_size <= PPC44x_MEM_SIZE_128M))
+ return PPC44x_MEM_SIZE_128M;
+
+ if ((in_size > PPC44x_MEM_SIZE_128M) && (in_size <= PPC44x_MEM_SIZE_256M))
+ return PPC44x_MEM_SIZE_256M;
+ if ((in_size > PPC44x_MEM_SIZE_256M) && (in_size <= PPC44x_MEM_SIZE_512M))
+ return PPC44x_MEM_SIZE_512M;
+
+ return 0;
+}
+
+#define PCI_READW(offset) \
+ (readw((void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEW(value, offset) \
+ (writew(value, (void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEL(value, offset) \
+ (writel(value, (void *)((u32)pci_reg_base+offset)))
+
+static void __init
+bamboo_setup_pci(void)
+{
+ void *pci_reg_base;
+ unsigned long memory_size;
+ memory_size = ppc_md.find_end_of_memory();
+
+ pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
+
+ /* Enable PCI I/O, Mem, and Busmaster cycles */
+ PCI_WRITEW(PCI_READW(PCI_COMMAND) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCI_COMMAND);
+
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA); /* Disable region first */
+ PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA); /* PLB starting addr: 0x00000000A0000000 */
+ PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA); /* PCI start addr, 0xA0000000 (PCI Address) */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
+ PCI_WRITEL(((0xffffffff -
+ (BAMBOO_PCI_UPPER_MEM -
+ BAMBOO_PCI_MEM_BASE)) | 0x01), BAMBOO_PCIL0_PMM0MA);/* Enable no pre-fetch, enable region */
+ //PCI_WRITEL(0xFC000001, BAMBOO_PCIL0_PMM0MA); /* 64 MB, Enable no pre-fetch, enable region */
+
+ /* Disable region one */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+
+ /* Disable region two */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+
+ /* Now configure the PCI->PLB windows, we only use PTM1
+ *
+ * For Inbound flow, set the window size to all available memory
+ * This is required because if size is smaller,
+ * then Eth/PCI DD would fail as PCI card not able to access
+ * the memory allocated by DD.
+ */
+
+ PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
+ memory_size = bamboo_ptm1_memory(memory_size) | 0x00000001;
+ PCI_WRITEL(memory_size, BAMBOO_PCIL0_PTM1MS); /* Size low + Enabled */
+
+ eieio();
+ iounmap(pci_reg_base);
+}
+
+static void __init
+bamboo_setup_hose(void)
+{
+ unsigned int bar_response, bar;
+ struct pci_controller *hose;
+
+ bamboo_setup_pci();
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
+
+ pci_init_resource(&hose->io_resource,
+ BAMBOO_PCI_LOWER_IO,
+ BAMBOO_PCI_UPPER_IO,
+ IORESOURCE_IO,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[0],
+ BAMBOO_PCI_LOWER_MEM,
+ BAMBOO_PCI_UPPER_MEM,
+ IORESOURCE_MEM,
+ "PCI host bridge");
+
+ ppc_md.pci_exclude_device = bamboo_exclude_device;
+
+ hose->io_space.start = BAMBOO_PCI_LOWER_IO;
+ hose->io_space.end = BAMBOO_PCI_UPPER_IO;
+ hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
+ hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
+ isa_io_base =
+ (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
+ hose->io_base_virt = (void *)isa_io_base;
+
+ setup_indirect_pci(hose,
+ BAMBOO_PCI_CFGA_PLB32,
+ BAMBOO_PCI_CFGD_PLB32);
+ hose->set_cfg_type = 1;
+
+ /* Zero config bars */
+ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+ early_write_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ 0x00000000);
+ early_read_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ &bar_response);
+ }
+
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = bamboo_map_irq;
+}
+
+TODC_ALLOC();
+
+static void __init
+bamboo_early_serial_map(void)
+{
+ struct uart_port port;
+
+ /* Setup ioremapped serial port access */
+ memset(&port, 0, sizeof(port));
+ port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
+ port.irq = 0;
+ port.uartclk = clocks.uart0;
+ port.regshift = 0;
+ port.iotype = SERIAL_IO_MEM;
+ port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.line = 0;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 0 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(0, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
+ port.irq = 1;
+ port.uartclk = clocks.uart1;
+ port.line = 1;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 1 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(1, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
+ port.irq = 3;
+ port.uartclk = clocks.uart2;
+ port.line = 2;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 2 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(2, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
+ port.irq = 4;
+ port.uartclk = clocks.uart3;
+ port.line = 3;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 3 failed\n");
+ }
+}
+
+static void __init
+bamboo_setup_arch(void)
+{
+
+ bamboo_set_emacdata();
+
+ /*
+ * Determine various clocks.
+ * To be completely correct we should get SysClk
+ * from FPGA, because it can be changed by on-board switches
+ * --ebs
+ */
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
+
+ /* Setup TODC access */
+ TODC_INIT(TODC_TYPE_DS1743,
+ 0,
+ 0,
+ ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
+ 8);
+
+ /* init to some ~sane value until calibrate_delay() runs */
+ loops_per_jiffy = 50000000/HZ;
+
+ /* Setup PCI host bridge */
+ bamboo_setup_hose();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+
+ bamboo_early_serial_map();
+
+ /* Identify the system */
+ printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
+}
+
+void __init platform_init(unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, unsigned long r7)
+{
+ parse_bootinfo(find_bootinfo());
+
+ /*
+ * If we were passed in a board information, copy it into the
+ * residual data area.
+ */
+ if (r3)
+ __res = *(bd_t *)(r3 + KERNELBASE);
+
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
+
+ ibm44x_platform_init();
+
+ ppc_md.setup_arch = bamboo_setup_arch;
+ ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
+ ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
+
+ ppc_md.calibrate_decr = bamboo_calibrate_decr;
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+#ifdef CONFIG_KGDB
+ ppc_md.early_serial_map = bamboo_early_serial_map;
+#endif
+}
+
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.h linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.h
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.h 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,141 @@
+/*
+ * arch/ppc/platforms/bamboo.h
+ *
+ * Bamboo board definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_BAMBOO_H__
+#define __ASM_BAMBOO_H__
+
+#include <linux/config.h>
+#include <platforms/4xx/ibm440ep.h>
+
+/* F/W TLB mapping used in bootloader glue to reset EMAC */
+#define PPC44x_EMAC0_MR0 0x0EF600E00
+
+#define PIBS_FLASH_BASE 0xfff00000
+#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
+#define PIBS_MAC_SIZE 0x200
+#define PIBS_MAC_OFFSET 0x100
+
+/* Default clock rate */
+#define BAMBOO_SYSCLK 33333333
+#define BAMBOO_OPBCLK 66666666
+#define BAMBOO_TMRCLK 25000000
+
+/* RTC/NVRAM location */
+#define BAMBOO_RTC_ADDR 0x80000000
+#define BAMBOO_RTC_SIZE 0x2000
+
+/* FPGA Registers */
+#define BAMBOO_FPGA_ADDR 0x80002000
+
+#define BAMBOO_FPGA_CONFIG1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x0)
+
+#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
+#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x8)
+#define BAMBOO_FORCE_100Mbps(x) (x & 0x4)
+#define BAMBOO_AUTONEG(x) (x & 0x2)
+
+#define BAMBOO_FPGA_CLOCKING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x2)
+
+#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
+#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
+#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
+#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
+
+#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
+#define BAMBOO_SEL_MII(x) (x & 0x80)
+#define BAMBOO_SEL_RMII(x) (x & 0x40)
+#define BAMBOO_SEL_SMII(x) (x & 0x20)
+
+#define BAMBOO_FPGA_SELECTION2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x5)
+#define BAMBOO_FPGA_SELECTION3_REG_ADDR (BAMBOO_FPGA_ADDR + 0x6)
+#define BAMBOO_FPGA_RESET_REG_ADDR (BAMBOO_FPGA_ADDR + 0x7)
+
+
+/* Flash */
+#define BAMBOO_SMALL_FLASH_LOW 0x087f00000
+#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000
+#define BAMBOO_SMALL_FLASH_SIZE 0x100000
+#define BAMBOO_LARGE_FLASH_LOW 0x087800000
+#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000
+#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000
+#define BAMBOO_LARGE_FLASH_SIZE 0x400000
+#define BAMBOO_NAND_FLASH_ADDR 0x090000000
+#define BAMBOO_NAND_FLASH_SIZE 0x6400000
+
+/*
+ * Serial port defines
+ */
+
+#define UART0_IO_BASE 0xEF600300
+#define UART1_IO_BASE 0xEF600400
+#define UART2_IO_BASE 0xEF600500
+#define UART3_IO_BASE 0xEF600600
+
+#define BASE_BAUD 33177600/3/16
+#define UART0_INT 0
+#define UART1_INT 1
+#define UART2_INT 3
+#define UART3_INT 4
+
+#define STD_UART_OP(num) \
+ { 0, BASE_BAUD, 0, UART##num##_INT, \
+ (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
+ iomem_base: UART##num##_IO_BASE, \
+ io_type: SERIAL_IO_MEM},
+
+#define SERIAL_PORT_DFNS \
+ STD_UART_OP(0) \
+ STD_UART_OP(1) \
+ STD_UART_OP(2) \
+ STD_UART_OP(3)
+
+/* PCI support */
+#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
+#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
+
+#define BAMBOO_PCI_IO_BASE 0x00000000e8000000
+#define BAMBOO_PCI_IO_SIZE 0x00010000
+#define BAMBOO_PCI_MEM_OFFSET 0x00000000
+#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000A0000000
+
+#define BAMBOO_PCI_LOWER_IO 0x00000000
+#define BAMBOO_PCI_UPPER_IO 0x0000ffff
+#define BAMBOO_PCI_LOWER_MEM 0xa0000000
+#define BAMBOO_PCI_UPPER_MEM 0xafffffff
+#define BAMBOO_PCI_MEM_BASE 0xA0000000
+
+#define BAMBOO_PCIL0_BASE 0x00000000ef400000
+#define BAMBOO_PCIL0_SIZE 0x40
+
+#define BAMBOO_PCIL0_PMM0LA 0x000
+#define BAMBOO_PCIL0_PMM0MA 0x004
+#define BAMBOO_PCIL0_PMM0PCILA 0x008
+#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
+#define BAMBOO_PCIL0_PMM1LA 0x010
+#define BAMBOO_PCIL0_PMM1MA 0x014
+#define BAMBOO_PCIL0_PMM1PCILA 0x018
+#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
+#define BAMBOO_PCIL0_PMM2LA 0x020
+#define BAMBOO_PCIL0_PMM2MA 0x024
+#define BAMBOO_PCIL0_PMM2PCILA 0x028
+#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
+#define BAMBOO_PCIL0_PTM1MS 0x030
+#define BAMBOO_PCIL0_PTM1LA 0x034
+#define BAMBOO_PCIL0_PTM2MS 0x038
+#define BAMBOO_PCIL0_PTM2LA 0x03C
+
+#endif /* __ASM_BAMBOO_H__ */
+#endif /* __KERNEL__ */
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,176 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.c
+ *
+ * PPC440EP I/O descriptions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <platforms/4xx/ibm440ep.h>
+#include <asm/ocp.h>
+
+static struct ocp_func_emac_data ibm440ep_emac0_def = {
+ .rgmii_idx = -1, /* No RGMII */
+ .rgmii_mux = -1, /* No RGMII */
+ .zmii_idx = 0, /* ZMII device index */
+ .zmii_mux = 0, /* ZMII input of this EMAC */
+ .mal_idx = 0, /* MAL device index */
+ .mal_rx_chan = 0, /* MAL rx channel number */
+ .mal_tx_chan = 0, /* MAL tx channel number */
+ .wol_irq = 61, /* WOL interrupt number */
+ .mdio_idx = -1, /* No shared MDIO */
+ .tah_idx = -1, /* No TAH */
+};
+
+static struct ocp_func_emac_data ibm440ep_emac1_def = {
+ .rgmii_idx = -1, /* No RGMII */
+ .rgmii_mux = -1, /* No RGMII */
+ .zmii_idx = 0, /* ZMII device index */
+ .zmii_mux = 1, /* ZMII input of this EMAC */
+ .mal_idx = 0, /* MAL device index */
+ .mal_rx_chan = 1, /* MAL rx channel number */
+ .mal_tx_chan = 2, /* MAL tx channel number */
+ .wol_irq = 63, /* WOL interrupt number */
+ .mdio_idx = -1, /* No shared MDIO */
+ .tah_idx = -1, /* No TAH */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_mal_data ibm440ep_mal0_def = {
+ .num_tx_chans = 4, /* Number of TX channels */
+ .num_rx_chans = 2, /* Number of RX channels */
+ .txeob_irq = 10, /* TX End Of Buffer IRQ */
+ .rxeob_irq = 11, /* RX End Of Buffer IRQ */
+ .txde_irq = 33, /* TX Descriptor Error IRQ */
+ .rxde_irq = 34, /* RX Descriptor Error IRQ */
+ .serr_irq = 32, /* MAL System Error IRQ */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_iic_data ibm440ep_iic0_def = {
+ .fast_mode = 0, /* Use standad mode (100Khz) */
+};
+
+static struct ocp_func_iic_data ibm440ep_iic1_def = {
+ .fast_mode = 0, /* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_OPB,
+ .index = 0,
+ .paddr = 0xEF600000,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 0,
+ .paddr = PPC440EP_UART0_ADDR,
+ .irq = UART0_INT,
+ .pm = IBM_CPM_UART0,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 1,
+ .paddr = PPC440EP_UART1_ADDR,
+ .irq = UART1_INT,
+ .pm = IBM_CPM_UART1,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 2,
+ .paddr = PPC440EP_UART2_ADDR,
+ .irq = UART2_INT,
+ .pm = IBM_CPM_UART2,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 3,
+ .paddr = PPC440EP_UART3_ADDR,
+ .irq = UART3_INT,
+ .pm = IBM_CPM_UART3,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_IIC,
+ .index = 0,
+ .paddr = PPC440EP_IIC0_ADDR,
+ .irq = IIC0_IRQ,
+ .pm = IBM_CPM_IIC0,
+ .additions = &ibm440ep_iic0_def,
+ .show = &ocp_show_iic_data
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_IIC,
+ .index = 1,
+ .paddr = PPC440EP_IIC1_ADDR,
+ .irq = IIC1_IRQ,
+ .pm = IBM_CPM_IIC1,
+ .additions = &ibm440ep_iic1_def,
+ .show = &ocp_show_iic_data
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_GPIO,
+ .index = 0,
+ .paddr = PPC440EP_GPIO0_ADDR,
+ .irq = OCP_IRQ_NA,
+ .pm = IBM_CPM_GPIO0,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_GPIO,
+ .index = 1,
+ .paddr = PPC440EP_GPIO1_ADDR,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_MAL,
+ .paddr = OCP_PADDR_NA,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_mal0_def,
+ .show = &ocp_show_mal_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_EMAC,
+ .index = 0,
+ .paddr = PPC440EP_EMAC0_ADDR,
+ .irq = BL_MAC_ETH0,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_emac0_def,
+ .show = &ocp_show_emac_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_EMAC,
+ .index = 1,
+ .paddr = PPC440EP_EMAC1_ADDR,
+ .irq = BL_MAC_ETH1,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_emac1_def,
+ .show = &ocp_show_emac_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_ZMII,
+ .paddr = PPC440EP_ZMII_ADDR,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_USB,
+ .paddr = PPC440EP_USB1HOST_ADDR,
+ .irq = USB0_IRQ,
+ .pm = IBM_CPM_USB1H,
+ },
+ { .vendor = OCP_VENDOR_INVALID
+ }
+};
+
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,224 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.h
+ *
+ * PPC440EP definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2002 Roland Dreier
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_PLATFORMS_IBM440EP_H
+#define __PPC_PLATFORMS_IBM440EP_H
+
+#include <linux/config.h>
+
+/* GPT */
+#define PPC440EP_GPT_ADDR 0x0EF600000
+#define PPC440EP_GPT_SIZE 0x200
+#define GPT_NUMS 1
+
+/* UART */
+#define PPC440EP_UART0_ADDR 0x0EF600300
+#define PPC440EP_UART1_ADDR 0x0EF600400
+#define PPC440EP_UART2_ADDR 0x0EF600500
+#define PPC440EP_UART3_ADDR 0x0EF600600
+#define PPC440EP_UART_SIZE 0x08
+#define UART_NUMS 4
+
+/* EMAC */
+#define PPC440EP_EMAC0_ADDR 0x0EF600E00
+#define PPC440EP_EMAC1_ADDR 0x0EF600F00
+#define PPC440EP_EMAC_SIZE 0x100
+#define EMAC_NUMS 2
+
+/* EMAC IRQ's */
+#define BL_MAC_WOL 61 /* WOL */
+#define BL_MAC_WOL1 63 /* WOL */
+#define BL_MAL_SERR 32 /* MAL SERR */
+#define BL_MAL_TXDE 33 /* MAL TXDE */
+#define BL_MAL_RXDE 34 /* MAL RXDE */
+#define BL_MAL_TXEOB 10 /* MAL TX EOB */
+#define BL_MAL_RXEOB 11 /* MAL RX EOB */
+#define BL_MAC_ETH0 60 /* MAC */
+#define BL_MAC_ETH1 62 /* MAC */
+
+/* ZMII */
+#define PPC440EP_ZMII_ADDR 0x0EF600D00
+#define PPC440EP_ZMII_SIZE 0x10
+#define ZMII_NUMS 1
+
+/* IIC */
+#define PPC440EP_IIC0_ADDR 0x0EF600700
+#define PPC440EP_IIC1_ADDR 0x0EF600800
+#define PPC440EP_IIC_SIZE 0x20
+#define IIC0_IRQ 2
+#define IIC1_IRQ 7
+#define IIC_NUMS 2
+
+/* SPI */
+#define PPC440EP_SPI_ADDR 0x0EF600900
+#define PPC440EP_SPI_SIZE 0x06
+#define SPI_NUMS 1
+
+/* GPIO */
+#define PPC440EP_GPIO0_ADDR 0x0EF600B00
+#define PPC440EP_GPIO1_ADDR 0x0EF600C00
+#define PPC440EP_GPIO_SIZE 0x80
+#define GPIO_NUMS 2
+
+/* USB1HOST */
+#define PPC440EP_USB1HOST_ADDR 0x0EF601000
+#define PPC440EP_USB1HOST_SIZE 0x80
+#define USB1HOST_IRQ 40
+#define USB1HOST_NUMS 1
+
+/* USB 1.1 Host constants for usb-ocp-ohci.c */
+#define USB0_IRQ USB1HOST_IRQ
+#define USB0_BASE PPC440EP_USB1HOST_ADDR
+#define USB0_SIZE PPC440EP_USB1HOST_SIZE
+#define USB0_EXTENT 4096
+
+/* NDFC Registers */
+#define PPC440EP_NDFC_REG_BASE 0x090000000
+#define PPC440EP_NDFC_REG_SIZE 0x2000
+
+/* Clock and Power Management */
+#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
+#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
+#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
+#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
+#define IBM_CPM_FPU 0x04000000 /* floating point unit */
+#define IBM_CPM_CPU 0x02000000 /* processor core */
+#define IBM_CPM_DMA 0x01000000 /* DMA controller */
+#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
+#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
+#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
+#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
+#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
+#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
+#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
+#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
+#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
+#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
+#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
+#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
+#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
+#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
+#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
+#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
+#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
+#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
+#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
+#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
+#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
+#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
+
+#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
+ | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
+ | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
+ | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
+ | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
+ | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
+/*
+ * Serial port defines
+ */
+#define RS_TABLE_SIZE 4
+
+#include <asm/ibm44x.h>
+#include <syslib/ibm440ep_common.h>
+
+/*
+ * DCRs (the common ones will be defined in ibm44x.h)
+ */
+
+/* Base DCR address values for all peripheral cores in the 440EP */
+
+#define CPR0_DCR_BASE 0x00C /* Clock and Power Reset */
+#define SDR0_DCR_BASE 0x00E /* chip control registers */
+
+/* DMA */
+
+#define MAX_DMA_PLB4_CHANNELS 4
+
+/* Base DCRNs */
+#define DCRN_DMA0_PLB4_BASE 0x300 /* DMA to PL4 Channel 0 */
+#define DCRN_DMA1_PLB4_BASE 0x308 /* DMA to PL4 Channel 1 */
+#define DCRN_DMA2_PLB4_BASE 0x310 /* DMA to PL4 Channel 2 */
+#define DCRN_DMA3_PLB4_BASE 0x318 /* DMA to PL4 Channel 3 */
+#define DCRN_DMASR_PLB4_BASE 0x320 /* DMA to PL4 status Register */
+
+#define DCRN_DMACR0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x0) /* DMA Channel Control 0 */
+#define DCRN_DMACT0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x1) /* DMA Count 0 */
+#define DCRN_DMASAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x2) /* DMA Src Addr High 0 */
+#define DCRN_DMASA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x3) /* DMA Src Addr Low 0 */
+#define DCRN_DMADAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x4) /* DMA Dest Addr High 0 */
+#define DCRN_DMADA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x5) /* DMA Dest Addr Low 0 */
+#define DCRN_ASGH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 0 */
+#define DCRN_ASG0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
+
+#define DCRN_DMACR1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x0) /* DMA Channel Control 1 */
+#define DCRN_DMACT1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x1) /* DMA Count 1 */
+#define DCRN_DMASAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x2) /* DMA Src Addr High 1 */
+#define DCRN_DMASA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x3) /* DMA Src Addr Low 1 */
+#define DCRN_DMADAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x4) /* DMA Dest Addr High 1 */
+#define DCRN_DMADA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x5) /* DMA Dest Addr Low 1 */
+#define DCRN_ASGH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 1 */
+#define DCRN_ASG1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
+
+#define DCRN_DMACR2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x0) /* DMA Channel Control 2 */
+#define DCRN_DMACT2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x1) /* DMA Count 2 */
+#define DCRN_DMASAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x2) /* DMA Src Addr High 2 */
+#define DCRN_DMASA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x3) /* DMA Src Addr Low 2 */
+#define DCRN_DMADAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x4) /* DMA Dest Addr High 2 */
+#define DCRN_DMADA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x5) /* DMA Dest Addr Low 2 */
+#define DCRN_ASGH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 2 */
+#define DCRN_ASG2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
+
+#define DCRN_DMACR3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x0) /* DMA Channel Control 3 */
+#define DCRN_DMACT3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x1) /* DMA Count 3 */
+#define DCRN_DMASAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x2) /* DMA Src Addr High 3 */
+#define DCRN_DMASA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x3) /* DMA Src Addr Low 3 */
+#define DCRN_DMADAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x4) /* DMA Dest Addr High 3 */
+#define DCRN_DMADA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x5) /* DMA Dest Addr Low 3 */
+#define DCRN_ASGH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 3 */
+#define DCRN_ASG3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
+
+#define DCRN_DMASR_PLB4 (DCRN_DMASR_PLB4_BASE + 0x0) /* DMA Status Register */
+#define DCRN_ASGC_PLB4 (DCRN_DMASR_PLB4_BASE + 0x3) /* DMA Scatter/Gather Command */
+#define DCRN_SLP_PLB4 (DCRN_DMASR_PLB4_BASE + 0x5) /* DMA Sleep Register */
+#define DCRN_POL_PLB4 (DCRN_DMASR_PLB4_BASE + 0x6) /* DMA Polarity Register */
+
+#define DMA_CE_ENABLE_PLB4 0x80000000
+#define DMA_CIE_ENABLE_PLB4 0x40000000
+#define DMA_TD_PLB4 0x20000000
+#define DMA_PL_PLB4 0x10000000
+#define DMA_PW_WORD 0x04000000
+#define DMA_DAI_PLB4 0x01000000
+#define DMA_SAI_PLB4 0x00800000
+#define DMA_BUFFER_ENABLED_PLB4 0x00400000
+#define DMA_MTM_HARDWARE_START_PLB4 0x00300000
+#define DMA_TS_IS_OUTPUT_PLB4 0x00000100
+#define DMA_STOP_AT_TC_PLB4 0x00000080
+#define DMA_PRIORITY_HIGH_PLB4 0x00000060
+
+#define DMA_TCIE_ENABLED_PLB4 0x20000000
+#define DMA_ETIE_ENABLED_PLB4 0x10000000
+#define DMA_EIE_ENABLED_PLB4 0x08000000
+#define DMA_BURST_ENABLED_PLB4 0x00800000
+#define DMA_BURST_SIZE_8_PLB4 0x00400000
+
+/* SDR0 */
+#define SDR0_USB 0x0320 /* Selection of USB2.0 and USB1.1 Device */
+
+#endif /* __PPC_PLATFORMS_IBM440EP_H */
+#endif /* __KERNEL__ */
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/Makefile linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile
--- linux-2.6.11-bk7/arch/ppc/syslib/Makefile 2005-03-11 16:25:17.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile 2005-03-14 14:59:52.000000000 -0700
@@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram
obj-$(CONFIG_PPC_OCP) += ocp.o
obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
obj-$(CONFIG_44x) += ibm44x_common.o
+obj-$(CONFIG_440EP) += ibm440gx_common.o ibm440ep_common.o
obj-$(CONFIG_440GP) += ibm440gp_common.o
obj-$(CONFIG_440GX) += ibm440gx_common.o
obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP) += open_pic.o in
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
+obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c 2005-03-14 13:49:37.000000000 -0700
@@ -0,0 +1,334 @@
+/*
+ * arch/ppc/kernel/ibm440ep_common.c
+ *
+ * PPC440EP system library
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <asm/ibm44x.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <syslib/ibm440ep_common.h>
+#include <linux/module.h>
+
+/* DMA functions reserved for DMA to PLB4 (used for USB2.0 Device) */
+
+/*
+ * * Clear DMA Status Register (DMA2P40_SR)
+ * */
+void clear_dma2pl4_status(void)
+{
+ mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
+}
+
+/*
+ * * Get the DMA to PLB4 status Register (DMA2P40_SR)
+ * */
+int get_dma2pl4_status(void)
+{
+ return (mfdcr(DCRN_DMASR_PLB4));
+}
+
+/*
+ * * Get the DMA to PLB4 ADDRESS DEST (DMA2P40_DA)
+ * */
+unsigned long get_dma2pl4_dst_addr(unsigned int dmanr)
+{
+ unsigned long dst_addr;
+
+ switch (dmanr) {
+ case 0:
+ dst_addr = mfdcr(DCRN_DMADA0_PLB4);
+ break;
+
+ case 1:
+ dst_addr = mfdcr(DCRN_DMADA1_PLB4);
+ break;
+
+ case 2:
+ dst_addr = mfdcr(DCRN_DMADA2_PLB4);
+ break;
+
+ case 3:
+ dst_addr = mfdcr(DCRN_DMADA3_PLB4);
+ break;
+
+ default:
+ dst_addr = 0;
+ if (dmanr >= MAX_DMA_PLB4_CHANNELS)
+ printk("get_dma2pl4_dst_addr: bad channel: %d\n", dmanr);
+ }
+ return dst_addr;
+}
+
+/*
+ * Set the source address
+ */
+void set_src_addr_dma2pl4(unsigned int dmanr, phys_addr_t src_addr)
+{
+ switch (dmanr) {
+
+ case 0:
+ mtdcr(DCRN_DMASAH0_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA0_PLB4, (u32)src_addr);
+ break;
+
+ case 1:
+ mtdcr(DCRN_DMASAH1_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA1_PLB4, (u32)src_addr);
+ break;
+
+ case 2:
+ mtdcr(DCRN_DMASAH2_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA2_PLB4, (u32)src_addr);
+ break;
+
+ case 3:
+ mtdcr(DCRN_DMASAH3_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA3_PLB4, (u32)src_addr);
+ break;
+
+ default:
+ if (dmanr >= MAX_DMA_PLB4_CHANNELS)
+ printk("set_src_addr_dma2pl4: bad channel: %d\n", dmanr);
+ }
+}
+
+/*
+ * Set the destimation address
+ */
+void set_dst_addr_dma2pl4(unsigned int dmanr, phys_addr_t dst_addr)
+{
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMADAH0_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA0_PLB4, (u32)dst_addr);
+ break;
+ case 1:
+ mtdcr(DCRN_DMADAH1_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA1_PLB4, (u32)dst_addr);
+ break;
+ case 2:
+ mtdcr(DCRN_DMADAH2_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA2_PLB4, (u32)dst_addr);
+ break;
+ case 3:
+ mtdcr(DCRN_DMADAH3_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA3_PLB4, (u32)dst_addr);
+ break;
+ default:
+ if (dmanr >= MAX_DMA_PLB4_CHANNELS)
+ printk("set_dst_addr_dma2pl4: bad channel: %d\n", dmanr);
+ }
+}
+
+/*
+ * Enable the DMA to PLB4 Peripheral to Memory
+ */
+void enable_dma2pl4_peripheral_to_memory(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count)
+{
+ unsigned int control = 0x00;
+
+ control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
+ control |= DMA_TD_PLB4; /* Transfers are from peripheral-to-memory */
+ control |= DMA_PL_PLB4; /* Device located on the OPB */
+ control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
+ control |= DMA_DAI_PLB4; /* Destination Address Increment */
+ control |= 0x00; /* Do not increment Source Address */
+ control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
+ control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
+ control |= 0x00; /* Peripheral Setup Cycles:000 */
+ control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
+ control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
+ control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
+
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+
+ /*
+ * Clear the CS, TS, RI bits for the channel from DMASR. This
+ * has been observed to happen correctly only after the mode and
+ * ETD/DCE bits in DMACRx are set above. Must do this before
+ * enabling the channel.
+ */
+ mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
+
+ /* peripheral to memory */
+ set_src_addr_dma2pl4(dmanr, srcAddr);
+ set_dst_addr_dma2pl4(dmanr, destAddr);
+
+ count |= DMA_TCIE_ENABLED_PLB4;
+ count |= DMA_ETIE_ENABLED_PLB4;
+ count |= DMA_EIE_ENABLED_PLB4;
+ count |= DMA_BURST_ENABLED_PLB4;
+ count |= DMA_BURST_SIZE_8_PLB4;
+
+ /* Set the number of bytes to transfer */
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACT0_PLB4, count);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACT1_PLB4, count);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACT2_PLB4, count);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACT3_PLB4, count);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+
+ /*
+ * Now enable the channel.
+ */
+ control |= DMA_CE_ENABLE_PLB4;
+
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+}
+
+/*
+ * * Enable the DMA to PLB4 Memory to Peripheral
+ * */
+void enable_dma2pl4_memory_to_peripheral(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count)
+{
+ unsigned int control = 0x00;
+
+ control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
+ control |= 0x00; /* Transfers are from memory_to_peripheral */
+ control |= DMA_PL_PLB4; /* Device located on the OPB */
+ control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
+ control |= 0x00; /* Do not increment Destination Address */
+ control |= DMA_SAI_PLB4; /* Source Address Increment */
+ control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
+ control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
+ control |= 0x00; /* Peripheral Setup Cycles:000 */
+ control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
+ control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
+ control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+ /*
+ * Clear the CS, TS, RI bits for the channel from DMASR. This
+ * has been observed to happen correctly only after the mode and
+ * ETD/DCE bits in DMACRx are set above. Must do this before
+ * enabling the channel.
+ */
+ mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
+
+ /* peripheral to memory */
+ set_src_addr_dma2pl4(dmanr, srcAddr);
+ set_dst_addr_dma2pl4(dmanr, destAddr);
+ count |= DMA_TCIE_ENABLED_PLB4;
+ count |= DMA_ETIE_ENABLED_PLB4;
+ count |= DMA_EIE_ENABLED_PLB4;
+ count |= DMA_BURST_ENABLED_PLB4;
+ count |= DMA_BURST_SIZE_8_PLB4;
+
+ /* Set the number of bytes to transfer */
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACT0_PLB4, count);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACT1_PLB4, count);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACT2_PLB4, count);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACT3_PLB4, count);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+
+ /*
+ * Now enable the channel.
+ */
+ control |= DMA_CE_ENABLE_PLB4;
+
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+}
+
+EXPORT_SYMBOL(get_dma2pl4_status);
+EXPORT_SYMBOL(clear_dma2pl4_status);
+EXPORT_SYMBOL(get_dma2pl4_dst_addr);
+EXPORT_SYMBOL(enable_dma2pl4_peripheral_to_memory);
+EXPORT_SYMBOL(enable_dma2pl4_memory_to_peripheral);
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.h linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.h
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.h 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,54 @@
+/*
+ * arch/ppc/kernel/ibm440ep_common.h
+ *
+ * PPC440EP system library
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#ifdef __KERNEL__
+#ifndef __PPC_SYSLIB_IBM440EP_COMMON_H
+#define __PPC_SYSLIB_IBM440EP_COMMON_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <syslib/ibm44x_common.h>
+#include <asm/mmu.h>
+
+/*
+ * Please, refer to the Figure 15.1 in 440EP user manual
+ *
+ * if internal UART clock is used, ser_clk is ignored
+ */
+void ibm440ep_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk,
+ unsigned int ser_clk) __init;
+
+/*
+ * The DMA API are in ibm440ep_common.c
+ */
+int get_dma2pl4_status(void);
+void clear_dma2pl4_status(void);
+unsigned long get_dma2pl4_dst_addr(unsigned int dmanr);
+void enable_dma2pl4_peripheral_to_memory(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count);
+void enable_dma2pl4_memory_to_peripheral(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __PPC_SYSLIB_IBM440EP_COMMON_H */
+#endif /* __KERNEL__ */
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440gx_common.c linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440gx_common.c
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm440gx_common.c 2005-03-02 00:38:25.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440gx_common.c 2005-03-14 13:52:45.000000000 -0700
@@ -34,6 +34,10 @@ void __init ibm440gx_get_clocks(struct i
u32 plld = CPR_READ(DCRN_CPR_PLLD);
u32 uart0 = SDR_READ(DCRN_SDR_UART0);
u32 uart1 = SDR_READ(DCRN_SDR_UART1);
+#ifdef CONFIG_440EP
+ u32 uart2 = SDR_READ(DCRN_SDR_UART2);
+ u32 uart3 = SDR_READ(DCRN_SDR_UART3);
+#endif
/* Dividers */
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
@@ -96,6 +100,19 @@ bypass:
p->uart1 = ser_clk;
else
p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+
+#ifdef CONFIG_440EP
+ if (uart2 & 0x00800000)
+ p->uart1 = ser_clk;
+ else
+ p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+
+ if (uart3 & 0x00800000)
+ p->uart1 = ser_clk;
+ else
+ p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+#endif
+
}
/* Issue L2C diagnostic command */
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm44x_common.h linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm44x_common.h
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm44x_common.h 2005-03-02 00:37:50.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm44x_common.h 2005-03-14 13:48:19.000000000 -0700
@@ -29,6 +29,11 @@ struct ibm44x_clocks {
unsigned int ebc; /* PerClk */
unsigned int uart0;
unsigned int uart1;
+#ifdef CONFIG_440EP
+ /* The IBM 440EP eval board has four uarts */
+ unsigned int uart2;
+ unsigned int uart3;
+#endif
};
/* common 44x platform init */
diff -uprN linux-2.6.11-bk7/include/asm-ppc/ibm44x.h linux-2.6.11-bk7-440ep/include/asm-ppc/ibm44x.h
--- linux-2.6.11-bk7/include/asm-ppc/ibm44x.h 2005-03-02 00:38:38.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/ibm44x.h 2005-03-11 16:26:19.000000000 -0700
@@ -35,8 +35,10 @@
#define PPC44x_LOW_SLOT 63
/* LS 32-bits of UART0 physical address location for early serial text debug */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define UART0_PHYS_IO_BASE 0xf0000200
+#elif defined(CONFIG_440EP)
+#define UART0_PHYS_IO_BASE 0xe0000000
#else
#define UART0_PHYS_IO_BASE 0x40000200
#endif
@@ -49,11 +51,16 @@
/*
* Standard 4GB "page" definitions
*/
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_PAGE 0x0000000000000000ULL
+#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
+#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
#else
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
@@ -64,7 +71,7 @@
/*
* 36-bit trap ranges
*/
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define PPC44x_IO_LO 0xf0000000UL
#define PPC44x_IO_HI 0xf0000fffUL
#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -75,6 +82,13 @@
#define PPC44x_PCI2CFG_HI 0x2ec00007UL
#define PPC44x_PCIMEM_LO 0x80000000UL
#define PPC44x_PCIMEM_HI 0xdfffffffUL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_LO 0xef500000
+#define PPC44x_IO_HI 0xefffffff
+#define PPC44x_PCI0CFG_LO 0xeec00000
+#define PPC44x_PCI0CFG_HI 0xeecfffff
+#define PPC44x_PCIMEM_LO 0xa0000000
+#define PPC44x_PCIMEM_HI 0xdfffffff
#else
#define PPC44x_IO_LO 0x40000000UL
#define PPC44x_IO_HI 0x40000fffUL
@@ -151,7 +165,21 @@
#define DCRN_SDR_MFR_E3RXFH 0x00000001
#define DCRN_SDR_UART0 0x0120
#define DCRN_SDR_UART1 0x0121
+#endif /* CONFIG_440GX */
+#ifdef CONFIG_440EP
+#define DCRN_SDR_CONFIG_ADDR 0xe
+#define DCRN_SDR_CONFIG_DATA 0xf
+#define DCRN_SDR_PFC0 0x4100
+#define DCRN_SDR_PFC1 0x4101
+#define DCRN_SDR_MFR 0x4300
+#define DCRN_SDR_UART0 0x0120
+#define DCRN_SDR_UART1 0x0121
+#define DCRN_SDR_UART2 0x0122
+#define DCRN_SDR_UART3 0x0123
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
/* SDR read/write helper macros */
#define SDR_READ(offset) ({\
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +197,14 @@
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_MAL_BASE 0x180
+#ifdef CONFIG_440EP
+#define DCRN_DMA2P40_BASE 0x300
+#define DCRN_DMA2P41_BASE 0x308
+#define DCRN_DMA2P42_BASE 0x310
+#define DCRN_DMA2P43_BASE 0x318
+#define DCRN_DMA2P4SR_BASE 0x320
+#endif
+
/* UIC */
#define DCRN_UIC0_BASE 0xc0
#define DCRN_UIC1_BASE 0xd0
diff -uprN linux-2.6.11-bk7/include/asm-ppc/ibm4xx.h linux-2.6.11-bk7-440ep/include/asm-ppc/ibm4xx.h
--- linux-2.6.11-bk7/include/asm-ppc/ibm4xx.h 2005-03-02 00:38:09.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/ibm4xx.h 2005-03-11 16:26:19.000000000 -0700
@@ -109,6 +109,10 @@ void ppc4xx_init(unsigned long r3, unsig
#include <platforms/4xx/ocotea.h>
#endif
+#if defined(CONFIG_BAMBOO)
+#include <platforms/4xx/bamboo.h>
+#endif
+
#ifndef __ASSEMBLY__
#ifdef CONFIG_40x
/*
diff -uprN linux-2.6.11-bk7/include/asm-ppc/ppc_asm.h linux-2.6.11-bk7-440ep/include/asm-ppc/ppc_asm.h
--- linux-2.6.11-bk7/include/asm-ppc/ppc_asm.h 2005-03-02 00:37:48.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/ppc_asm.h 2005-03-11 16:26:19.000000000 -0700
@@ -184,6 +184,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
#define PPC405_ERR77_SYNC
#endif
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
/* The boring bits... */
/* Condition Register Bit Fields */
diff -uprN linux-2.6.11-bk7/include/asm-ppc/reg.h linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h
--- linux-2.6.11-bk7/include/asm-ppc/reg.h 2005-03-11 16:25:22.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h 2005-03-14 10:05:47.000000000 -0700
@@ -449,6 +449,8 @@
#define PVR_STB03XXX 0x40310000
#define PVR_NP405H 0x41410000
#define PVR_NP405L 0x41610000
+#define PVR_440EP_RA 0x42221850
+#define PVR_440EP_RB 0x422218D3
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC1 0x40120481
#define PVR_440GP_RC2 0x40200481
^ permalink raw reply
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
From: Eugene Surovegin @ 2005-03-15 18:41 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
In-Reply-To: <1110907039.24673.12.camel@rhino.az.mvista.com>
On Tue, Mar 15, 2005 at 10:17:19AM -0700, Wade Farnsworth wrote:
> Hello all,
>
> This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
> board. Any comments would be appreciated.
[snip]
> diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c
> --- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c 2005-03-11 16:26:19.000000000 -0700
> @@ -0,0 +1,176 @@
> +/*
> + * arch/ppc/platforms/4xx/ibm440ep.c
> + *
> + * PPC440EP I/O descriptions
> + *
> + * Wade Farnsworth <wfarnsworth@mvista.com>
> + * Copyright 2004 MontaVista Software Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <platforms/4xx/ibm440ep.h>
> +#include <asm/ocp.h>
> +
> +static struct ocp_func_emac_data ibm440ep_emac0_def = {
> + .rgmii_idx = -1, /* No RGMII */
> + .rgmii_mux = -1, /* No RGMII */
> + .zmii_idx = 0, /* ZMII device index */
> + .zmii_mux = 0, /* ZMII input of this EMAC */
> + .mal_idx = 0, /* MAL device index */
> + .mal_rx_chan = 0, /* MAL rx channel number */
> + .mal_tx_chan = 0, /* MAL tx channel number */
> + .wol_irq = 61, /* WOL interrupt number */
> + .mdio_idx = -1, /* No shared MDIO */
> + .tah_idx = -1, /* No TAH */
> +};
> +
> +static struct ocp_func_emac_data ibm440ep_emac1_def = {
> + .rgmii_idx = -1, /* No RGMII */
> + .rgmii_mux = -1, /* No RGMII */
> + .zmii_idx = 0, /* ZMII device index */
> + .zmii_mux = 1, /* ZMII input of this EMAC */
> + .mal_idx = 0, /* MAL device index */
> + .mal_rx_chan = 1, /* MAL rx channel number */
> + .mal_tx_chan = 2, /* MAL tx channel number */
> + .wol_irq = 63, /* WOL interrupt number */
> + .mdio_idx = -1, /* No shared MDIO */
> + .tah_idx = -1, /* No TAH */
> +};
> +OCP_SYSFS_EMAC_DATA()
> +
> +static struct ocp_func_mal_data ibm440ep_mal0_def = {
> + .num_tx_chans = 4, /* Number of TX channels */
> + .num_rx_chans = 2, /* Number of RX channels */
> + .txeob_irq = 10, /* TX End Of Buffer IRQ */
> + .rxeob_irq = 11, /* RX End Of Buffer IRQ */
> + .txde_irq = 33, /* TX Descriptor Error IRQ */
> + .rxde_irq = 34, /* RX Descriptor Error IRQ */
> + .serr_irq = 32, /* MAL System Error IRQ */
> +};
> +OCP_SYSFS_MAL_DATA()
> +
> +static struct ocp_func_iic_data ibm440ep_iic0_def = {
> + .fast_mode = 0, /* Use standad mode (100Khz) */
> +};
> +
> +static struct ocp_func_iic_data ibm440ep_iic1_def = {
> + .fast_mode = 0, /* Use standad mode (100Khz) */
> +};
> +OCP_SYSFS_IIC_DATA()
> +
> +struct ocp_def core_ocp[] = {
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_OPB,
> + .index = 0,
> + .paddr = 0xEF600000,
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 0,
> + .paddr = PPC440EP_UART0_ADDR,
> + .irq = UART0_INT,
> + .pm = IBM_CPM_UART0,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 1,
> + .paddr = PPC440EP_UART1_ADDR,
> + .irq = UART1_INT,
> + .pm = IBM_CPM_UART1,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 2,
> + .paddr = PPC440EP_UART2_ADDR,
> + .irq = UART2_INT,
> + .pm = IBM_CPM_UART2,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 3,
> + .paddr = PPC440EP_UART3_ADDR,
> + .irq = UART3_INT,
> + .pm = IBM_CPM_UART3,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_IIC,
> + .index = 0,
> + .paddr = PPC440EP_IIC0_ADDR,
Do we need PPC440EP_IIC0_ADDR define? I think not, please, don't
introduce useless defines which are only used in one file. Use numbers
directly, it helps readability. Please, look at how this is
handled in other 4xx platform files.
> + .irq = IIC0_IRQ,
Ditto
> + .pm = IBM_CPM_IIC0,
> + .additions = &ibm440ep_iic0_def,
> + .show = &ocp_show_iic_data
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_IIC,
> + .index = 1,
> + .paddr = PPC440EP_IIC1_ADDR,
Ditto.
> + .irq = IIC1_IRQ,
> + .pm = IBM_CPM_IIC1,
> + .additions = &ibm440ep_iic1_def,
> + .show = &ocp_show_iic_data
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_GPIO,
> + .index = 0,
> + .paddr = PPC440EP_GPIO0_ADDR,
Ditto.
> + .irq = OCP_IRQ_NA,
> + .pm = IBM_CPM_GPIO0,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_GPIO,
> + .index = 1,
> + .paddr = PPC440EP_GPIO1_ADDR,
Ditto.
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_MAL,
> + .paddr = OCP_PADDR_NA,
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + .additions = &ibm440ep_mal0_def,
> + .show = &ocp_show_mal_data,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_EMAC,
> + .index = 0,
> + .paddr = PPC440EP_EMAC0_ADDR,
Ditto
> + .irq = BL_MAC_ETH0,
Ditto.
> + .pm = OCP_CPM_NA,
> + .additions = &ibm440ep_emac0_def,
> + .show = &ocp_show_emac_data,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_EMAC,
> + .index = 1,
> + .paddr = PPC440EP_EMAC1_ADDR,
> + .irq = BL_MAC_ETH1,
> + .pm = OCP_CPM_NA,
> + .additions = &ibm440ep_emac1_def,
> + .show = &ocp_show_emac_data,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_ZMII,
> + .paddr = PPC440EP_ZMII_ADDR,
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_USB,
> + .paddr = PPC440EP_USB1HOST_ADDR,
> + .irq = USB0_IRQ,
> + .pm = IBM_CPM_USB1H,
> + },
> + { .vendor = OCP_VENDOR_INVALID
> + }
> +};
> +
> diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h
> --- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h 2005-03-11 16:26:19.000000000 -0700
> @@ -0,0 +1,224 @@
> +/*
> + * arch/ppc/platforms/4xx/ibm440ep.h
> + *
> + * PPC440EP definitions
> + *
> + * Wade Farnsworth <wfarnsworth@mvista.com>
> + *
> + * Copyright 2002 Roland Dreier
> + * Copyright 2004 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +
> +#ifdef __KERNEL__
> +#ifndef __PPC_PLATFORMS_IBM440EP_H
> +#define __PPC_PLATFORMS_IBM440EP_H
> +
> +#include <linux/config.h>
> +
> +/* GPT */
> +#define PPC440EP_GPT_ADDR 0x0EF600000
> +#define PPC440EP_GPT_SIZE 0x200
> +#define GPT_NUMS 1
> +
> +/* UART */
> +#define PPC440EP_UART0_ADDR 0x0EF600300
> +#define PPC440EP_UART1_ADDR 0x0EF600400
> +#define PPC440EP_UART2_ADDR 0x0EF600500
> +#define PPC440EP_UART3_ADDR 0x0EF600600
> +#define PPC440EP_UART_SIZE 0x08
> +#define UART_NUMS 4
> +
> +/* EMAC */
> +#define PPC440EP_EMAC0_ADDR 0x0EF600E00
> +#define PPC440EP_EMAC1_ADDR 0x0EF600F00
> +#define PPC440EP_EMAC_SIZE 0x100
> +#define EMAC_NUMS 2
> +
> +/* EMAC IRQ's */
> +#define BL_MAC_WOL 61 /* WOL */
> +#define BL_MAC_WOL1 63 /* WOL */
> +#define BL_MAL_SERR 32 /* MAL SERR */
> +#define BL_MAL_TXDE 33 /* MAL TXDE */
> +#define BL_MAL_RXDE 34 /* MAL RXDE */
> +#define BL_MAL_TXEOB 10 /* MAL TX EOB */
> +#define BL_MAL_RXEOB 11 /* MAL RX EOB */
> +#define BL_MAC_ETH0 60 /* MAC */
> +#define BL_MAC_ETH1 62 /* MAC */
We don't need these defines.
> +
> +/* ZMII */
> +#define PPC440EP_ZMII_ADDR 0x0EF600D00
> +#define PPC440EP_ZMII_SIZE 0x10
> +#define ZMII_NUMS 1
And these
> +
> +/* IIC */
> +#define PPC440EP_IIC0_ADDR 0x0EF600700
> +#define PPC440EP_IIC1_ADDR 0x0EF600800
> +#define PPC440EP_IIC_SIZE 0x20
> +#define IIC0_IRQ 2
> +#define IIC1_IRQ 7
> +#define IIC_NUMS 2
> +
> +/* SPI */
> +#define PPC440EP_SPI_ADDR 0x0EF600900
> +#define PPC440EP_SPI_SIZE 0x06
> +#define SPI_NUMS 1
> +
> +/* GPIO */
> +#define PPC440EP_GPIO0_ADDR 0x0EF600B00
> +#define PPC440EP_GPIO1_ADDR 0x0EF600C00
> +#define PPC440EP_GPIO_SIZE 0x80
> +#define GPIO_NUMS 2
And these....
> +
> +/* USB1HOST */
> +#define PPC440EP_USB1HOST_ADDR 0x0EF601000
> +#define PPC440EP_USB1HOST_SIZE 0x80
> +#define USB1HOST_IRQ 40
> +#define USB1HOST_NUMS 1
> +
> +/* USB 1.1 Host constants for usb-ocp-ohci.c */
> +#define USB0_IRQ USB1HOST_IRQ
> +#define USB0_BASE PPC440EP_USB1HOST_ADDR
> +#define USB0_SIZE PPC440EP_USB1HOST_SIZE
> +#define USB0_EXTENT 4096
> +
> +/* NDFC Registers */
> +#define PPC440EP_NDFC_REG_BASE 0x090000000
> +#define PPC440EP_NDFC_REG_SIZE 0x2000
> +
> +/* Clock and Power Management */
> +#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
> +#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
> +#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
> +#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
> +#define IBM_CPM_FPU 0x04000000 /* floating point unit */
> +#define IBM_CPM_CPU 0x02000000 /* processor core */
> +#define IBM_CPM_DMA 0x01000000 /* DMA controller */
> +#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
> +#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
> +#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
> +#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
> +#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
> +#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
> +#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
> +#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
> +#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
> +#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
> +#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
> +#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
> +#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
> +#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
> +#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
> +#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
> +#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
> +#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
> +#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
> +#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
> +#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
> +#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
> +#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
> +
> +#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
> + | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
> + | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
> + | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
> + | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
> + | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
> +/*
> + * Serial port defines
> + */
> +#define RS_TABLE_SIZE 4
> +
> +#include <asm/ibm44x.h>
> +#include <syslib/ibm440ep_common.h>
> +
> +/*
> + * DCRs (the common ones will be defined in ibm44x.h)
> + */
> +
> +/* Base DCR address values for all peripheral cores in the 440EP */
> +
> +#define CPR0_DCR_BASE 0x00C /* Clock and Power Reset */
> +#define SDR0_DCR_BASE 0x00E /* chip control registers */
> +
> +/* DMA */
> +
> +#define MAX_DMA_PLB4_CHANNELS 4
> +
> +/* Base DCRNs */
> +#define DCRN_DMA0_PLB4_BASE 0x300 /* DMA to PL4 Channel 0 */
> +#define DCRN_DMA1_PLB4_BASE 0x308 /* DMA to PL4 Channel 1 */
> +#define DCRN_DMA2_PLB4_BASE 0x310 /* DMA to PL4 Channel 2 */
> +#define DCRN_DMA3_PLB4_BASE 0x318 /* DMA to PL4 Channel 3 */
> +#define DCRN_DMASR_PLB4_BASE 0x320 /* DMA to PL4 status Register */
> +
> +#define DCRN_DMACR0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x0) /* DMA Channel Control 0 */
> +#define DCRN_DMACT0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x1) /* DMA Count 0 */
> +#define DCRN_DMASAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x2) /* DMA Src Addr High 0 */
> +#define DCRN_DMASA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x3) /* DMA Src Addr Low 0 */
> +#define DCRN_DMADAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x4) /* DMA Dest Addr High 0 */
> +#define DCRN_DMADA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x5) /* DMA Dest Addr Low 0 */
> +#define DCRN_ASGH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 0 */
> +#define DCRN_ASG0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
> +
> +#define DCRN_DMACR1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x0) /* DMA Channel Control 1 */
> +#define DCRN_DMACT1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x1) /* DMA Count 1 */
> +#define DCRN_DMASAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x2) /* DMA Src Addr High 1 */
> +#define DCRN_DMASA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x3) /* DMA Src Addr Low 1 */
> +#define DCRN_DMADAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x4) /* DMA Dest Addr High 1 */
> +#define DCRN_DMADA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x5) /* DMA Dest Addr Low 1 */
> +#define DCRN_ASGH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 1 */
> +#define DCRN_ASG1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
> +
> +#define DCRN_DMACR2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x0) /* DMA Channel Control 2 */
> +#define DCRN_DMACT2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x1) /* DMA Count 2 */
> +#define DCRN_DMASAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x2) /* DMA Src Addr High 2 */
> +#define DCRN_DMASA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x3) /* DMA Src Addr Low 2 */
> +#define DCRN_DMADAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x4) /* DMA Dest Addr High 2 */
> +#define DCRN_DMADA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x5) /* DMA Dest Addr Low 2 */
> +#define DCRN_ASGH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 2 */
> +#define DCRN_ASG2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
> +
> +#define DCRN_DMACR3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x0) /* DMA Channel Control 3 */
> +#define DCRN_DMACT3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x1) /* DMA Count 3 */
> +#define DCRN_DMASAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x2) /* DMA Src Addr High 3 */
> +#define DCRN_DMASA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x3) /* DMA Src Addr Low 3 */
> +#define DCRN_DMADAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x4) /* DMA Dest Addr High 3 */
> +#define DCRN_DMADA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x5) /* DMA Dest Addr Low 3 */
> +#define DCRN_ASGH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 3 */
> +#define DCRN_ASG3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
> +
> +#define DCRN_DMASR_PLB4 (DCRN_DMASR_PLB4_BASE + 0x0) /* DMA Status Register */
> +#define DCRN_ASGC_PLB4 (DCRN_DMASR_PLB4_BASE + 0x3) /* DMA Scatter/Gather Command */
> +#define DCRN_SLP_PLB4 (DCRN_DMASR_PLB4_BASE + 0x5) /* DMA Sleep Register */
> +#define DCRN_POL_PLB4 (DCRN_DMASR_PLB4_BASE + 0x6) /* DMA Polarity Register */
> +
> +#define DMA_CE_ENABLE_PLB4 0x80000000
> +#define DMA_CIE_ENABLE_PLB4 0x40000000
> +#define DMA_TD_PLB4 0x20000000
> +#define DMA_PL_PLB4 0x10000000
> +#define DMA_PW_WORD 0x04000000
> +#define DMA_DAI_PLB4 0x01000000
> +#define DMA_SAI_PLB4 0x00800000
> +#define DMA_BUFFER_ENABLED_PLB4 0x00400000
> +#define DMA_MTM_HARDWARE_START_PLB4 0x00300000
> +#define DMA_TS_IS_OUTPUT_PLB4 0x00000100
> +#define DMA_STOP_AT_TC_PLB4 0x00000080
> +#define DMA_PRIORITY_HIGH_PLB4 0x00000060
> +
> +#define DMA_TCIE_ENABLED_PLB4 0x20000000
> +#define DMA_ETIE_ENABLED_PLB4 0x10000000
> +#define DMA_EIE_ENABLED_PLB4 0x08000000
> +#define DMA_BURST_ENABLED_PLB4 0x00800000
> +#define DMA_BURST_SIZE_8_PLB4 0x00400000
> +
> +/* SDR0 */
> +#define SDR0_USB 0x0320 /* Selection of USB2.0 and USB1.1 Device */
> +
> +#endif /* __PPC_PLATFORMS_IBM440EP_H */
> +#endif /* __KERNEL__ */
> diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/Makefile linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile
> --- linux-2.6.11-bk7/arch/ppc/syslib/Makefile 2005-03-11 16:25:17.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile 2005-03-14 14:59:52.000000000 -0700
> @@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram
> obj-$(CONFIG_PPC_OCP) += ocp.o
> obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
> obj-$(CONFIG_44x) += ibm44x_common.o
> +obj-$(CONFIG_440EP) += ibm440gx_common.o ibm440ep_common.o
> obj-$(CONFIG_440GP) += ibm440gp_common.o
> obj-$(CONFIG_440GX) += ibm440gx_common.o
> obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
> @@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP) += open_pic.o in
> obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
> obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
> todc_time.o
> +obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
> obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
> obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
> obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
> diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c
> --- linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c 2005-03-14 13:49:37.000000000 -0700
> @@ -0,0 +1,334 @@
> +/*
> + * arch/ppc/kernel/ibm440ep_common.c
> + *
> + * PPC440EP system library
> + *
> + * Wade Farnsworth <wfarnsworth@mvista.com>
> + * Copyright 2004 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +#include <linux/config.h>
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <asm/ibm44x.h>
> +#include <asm/mmu.h>
> +#include <asm/processor.h>
> +#include <syslib/ibm440ep_common.h>
> +#include <linux/module.h>
> +
> +/* DMA functions reserved for DMA to PLB4 (used for USB2.0 Device) */
> +
> +/*
> + * * Clear DMA Status Register (DMA2P40_SR)
> + * */
> +void clear_dma2pl4_status(void)
> +{
> + mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
> +}
> +
> +/*
> + * * Get the DMA to PLB4 status Register (DMA2P40_SR)
> + * */
> +int get_dma2pl4_status(void)
> +{
> + return (mfdcr(DCRN_DMASR_PLB4));
> +}
> +
> +/*
> + * * Get the DMA to PLB4 ADDRESS DEST (DMA2P40_DA)
> + * */
> +unsigned long get_dma2pl4_dst_addr(unsigned int dmanr)
> +{
> + unsigned long dst_addr;
> +
> + switch (dmanr) {
> + case 0:
> + dst_addr = mfdcr(DCRN_DMADA0_PLB4);
> + break;
> +
> + case 1:
> + dst_addr = mfdcr(DCRN_DMADA1_PLB4);
> + break;
> +
> + case 2:
> + dst_addr = mfdcr(DCRN_DMADA2_PLB4);
> + break;
> +
> + case 3:
> + dst_addr = mfdcr(DCRN_DMADA3_PLB4);
> + break;
PLEASE, there is already "inderect" DCR stuff in the tree. You don't
need all these ugly switch statements.
> +
> + default:
> + dst_addr = 0;
> + if (dmanr >= MAX_DMA_PLB4_CHANNELS)
> + printk("get_dma2pl4_dst_addr: bad channel: %d\n", dmanr);
> + }
> + return dst_addr;
> +}
> +
> +/*
> + * Set the source address
> + */
> +void set_src_addr_dma2pl4(unsigned int dmanr, phys_addr_t src_addr)
> +{
> + switch (dmanr) {
> +
> + case 0:
> + mtdcr(DCRN_DMASAH0_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA0_PLB4, (u32)src_addr);
> + break;
> +
> + case 1:
> + mtdcr(DCRN_DMASAH1_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA1_PLB4, (u32)src_addr);
> + break;
> +
> + case 2:
> + mtdcr(DCRN_DMASAH2_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA2_PLB4, (u32)src_addr);
> + break;
> +
> + case 3:
> + mtdcr(DCRN_DMASAH3_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA3_PLB4, (u32)src_addr);
> + break;
Ditto.
> +
> + default:
> + if (dmanr >= MAX_DMA_PLB4_CHANNELS)
> + printk("set_src_addr_dma2pl4: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +/*
> + * Set the destimation address
> + */
> +void set_dst_addr_dma2pl4(unsigned int dmanr, phys_addr_t dst_addr)
> +{
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMADAH0_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA0_PLB4, (u32)dst_addr);
> + break;
> + case 1:
> + mtdcr(DCRN_DMADAH1_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA1_PLB4, (u32)dst_addr);
> + break;
> + case 2:
> + mtdcr(DCRN_DMADAH2_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA2_PLB4, (u32)dst_addr);
> + break;
> + case 3:
> + mtdcr(DCRN_DMADAH3_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA3_PLB4, (u32)dst_addr);
> + break;
Ditto.
> + default:
> + if (dmanr >= MAX_DMA_PLB4_CHANNELS)
> + printk("set_dst_addr_dma2pl4: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +/*
> + * Enable the DMA to PLB4 Peripheral to Memory
> + */
> +void enable_dma2pl4_peripheral_to_memory(unsigned int dmanr,
> + phys_addr_t srcAddr,
> + phys_addr_t destAddr,
> + unsigned int count)
> +{
> + unsigned int control = 0x00;
> +
> + control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
> + control |= DMA_TD_PLB4; /* Transfers are from peripheral-to-memory */
> + control |= DMA_PL_PLB4; /* Device located on the OPB */
> + control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
> + control |= DMA_DAI_PLB4; /* Destination Address Increment */
> + control |= 0x00; /* Do not increment Source Address */
> + control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
> + control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
> + control |= 0x00; /* Peripheral Setup Cycles:000 */
> + control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
> + control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
> + control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
> +
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +
> + /*
> + * Clear the CS, TS, RI bits for the channel from DMASR. This
> + * has been observed to happen correctly only after the mode and
> + * ETD/DCE bits in DMACRx are set above. Must do this before
> + * enabling the channel.
> + */
> + mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
> +
> + /* peripheral to memory */
> + set_src_addr_dma2pl4(dmanr, srcAddr);
> + set_dst_addr_dma2pl4(dmanr, destAddr);
> +
> + count |= DMA_TCIE_ENABLED_PLB4;
> + count |= DMA_ETIE_ENABLED_PLB4;
> + count |= DMA_EIE_ENABLED_PLB4;
> + count |= DMA_BURST_ENABLED_PLB4;
> + count |= DMA_BURST_SIZE_8_PLB4;
> +
> + /* Set the number of bytes to transfer */
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACT0_PLB4, count);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACT1_PLB4, count);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACT2_PLB4, count);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACT3_PLB4, count);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +
> + /*
> + * Now enable the channel.
> + */
> + control |= DMA_CE_ENABLE_PLB4;
> +
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +/*
> + * * Enable the DMA to PLB4 Memory to Peripheral
> + * */
> +void enable_dma2pl4_memory_to_peripheral(unsigned int dmanr,
> + phys_addr_t srcAddr,
> + phys_addr_t destAddr,
> + unsigned int count)
> +{
> + unsigned int control = 0x00;
> +
> + control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
> + control |= 0x00; /* Transfers are from memory_to_peripheral */
> + control |= DMA_PL_PLB4; /* Device located on the OPB */
> + control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
> + control |= 0x00; /* Do not increment Destination Address */
> + control |= DMA_SAI_PLB4; /* Source Address Increment */
> + control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
> + control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
> + control |= 0x00; /* Peripheral Setup Cycles:000 */
> + control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
> + control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
> + control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> + /*
> + * Clear the CS, TS, RI bits for the channel from DMASR. This
> + * has been observed to happen correctly only after the mode and
> + * ETD/DCE bits in DMACRx are set above. Must do this before
> + * enabling the channel.
> + */
> + mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
> +
> + /* peripheral to memory */
> + set_src_addr_dma2pl4(dmanr, srcAddr);
> + set_dst_addr_dma2pl4(dmanr, destAddr);
> + count |= DMA_TCIE_ENABLED_PLB4;
> + count |= DMA_ETIE_ENABLED_PLB4;
> + count |= DMA_EIE_ENABLED_PLB4;
> + count |= DMA_BURST_ENABLED_PLB4;
> + count |= DMA_BURST_SIZE_8_PLB4;
> +
> + /* Set the number of bytes to transfer */
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACT0_PLB4, count);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACT1_PLB4, count);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACT2_PLB4, count);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACT3_PLB4, count);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +
> + /*
> + * Now enable the channel.
> + */
> + control |= DMA_CE_ENABLE_PLB4;
> +
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +EXPORT_SYMBOL(get_dma2pl4_status);
> +EXPORT_SYMBOL(clear_dma2pl4_status);
> +EXPORT_SYMBOL(get_dma2pl4_dst_addr);
> +EXPORT_SYMBOL(enable_dma2pl4_peripheral_to_memory);
> +EXPORT_SYMBOL(enable_dma2pl4_memory_to_peripheral);
[snip]
> diff -uprN linux-2.6.11-bk7/include/asm-ppc/reg.h linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h
> --- linux-2.6.11-bk7/include/asm-ppc/reg.h 2005-03-11 16:25:22.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h 2005-03-14 10:05:47.000000000 -0700
> @@ -449,6 +449,8 @@
> #define PVR_STB03XXX 0x40310000
> #define PVR_NP405H 0x41410000
> #define PVR_NP405L 0x41610000
> +#define PVR_440EP_RA 0x42221850
> +#define PVR_440EP_RB 0x422218D3
I don't think it's needed. There are plans to get rid of all not-used
PVR defines.
> #define PVR_440GP_RB 0x40120440
> #define PVR_440GP_RC1 0x40120481
> #define PVR_440GP_RC2 0x40200481
--
Eugene
^ permalink raw reply
* Re: mtd maps
From: Mark A. Greer @ 2005-03-15 18:44 UTC (permalink / raw)
To: Greg Weeks; +Cc: linuxppc-embedded
In-Reply-To: <4236D36D.3090809@timesys.com>
Greg Weeks wrote:
> Are mtd maps still in drivers/mtd/maps or has that all moved to the
> platform code? I have an mtd map for the mpc8560ads but it's in mtd/maps.
The mtd code has changed so that platform code can get at the routines
to set up the maps from there. arch/ppc/platforms/katana.c has its mtd
maps there and I recently posted a patch that moves it for the chestnut
as well.
I think its a good idea to move them to the platform code since the mtd
maps are platform specific anyway. Plus its one less place to add/edit
a file. But that's just my $0.02...
Mark
^ permalink raw reply
* Re: [PATCH 2/3] PPC440EP: ibm_emac phy mode bug fix
From: Wade Farnsworth @ 2005-03-15 18:47 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1110907039.24673.12.camel@rhino.az.mvista.com>
[-- Attachment #1: Type: text/plain, Size: 377 bytes --]
This patch fixes a bug in drivers/net/ibm_emac/ibm_emac_core.c where if
the MDI0 bit is set in the ZMII_FER register, then the phy mode is not
detected properly, and SMII is selected by default. This only occurs on
platforms where the phy_mode field of struct ocp_func_emac_data is not
used.
Regards,
Wade Farnsworth
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ibm_emac-bugfix.patch --]
[-- Type: text/plain, Size: 560 bytes --]
--- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_core.c 2005-03-11 16:25:19.000000000 -0700
+++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_core.c 2005-03-11 16:26:19.000000000 -0700
@@ -315,7 +315,7 @@ static int emac_init_zmii(struct ocp_dev
zmii->base->fer &= ~ZMII_FER_MASK(input);
zmii->base->fer |= zmii_enable[input][mode];
} else {
- switch ((zmii->base->fer & ZMII_FER_MASK(input)) << (4 * input)) {
+ switch (((zmii->base->fer & ZMII_FER_MASK(input)) << (4 * input)) & ~ZMII_MDI0) {
case ZMII_MII0:
mode = MII;
break;
^ permalink raw reply
* Re: [PATCH 3/3] PPC440EP IBM EMAC support
From: Wade Farnsworth @ 2005-03-15 18:58 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1110912458.24527.27.camel@rhino.az.mvista.com>
[-- Attachment #1: Type: text/plain, Size: 155 bytes --]
This patch adds support to the IBM EMAC ethernet driver for the 440EP.
Regards,
Wade Farnsworth
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ibm_emac.patch --]
[-- Type: text/plain, Size: 2903 bytes --]
--- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-02 00:38:13.000000000 -0700
+++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-11 16:32:01.000000000 -0700
@@ -27,6 +27,12 @@
#include "ibm_emac_phy.h"
+#ifdef CONFIG_BAMBOO
+#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
+#else
+#define BAMBOO_REV0 0
+#endif
+
static int reset_one_mii_phy(struct mii_phy *phy, int phy_id)
{
u16 val;
@@ -109,6 +115,54 @@ static int genmii_setup_aneg(struct mii_
return 0;
}
+static int ac104_setup_aneg(struct mii_phy *phy, u32 advertise)
+{
+ /* Rev. 0 of the IBM 440EP Eval Board has improperly biased RJ-45
+ * sockets, causing 100baseTx to be disabled. Removing inductors L17
+ * and L18 enables 100baseTx, but disables 10baseT. Therefore, only
+ * one speed will be allowed.
+ *
+ * Rev. 1 boards and any other boards using the AC104 can use the
+ * generic function.
+ */
+ u16 ctl, adv, bmcr;
+
+ if (!BAMBOO_REV0)
+ return genmii_setup_aneg(phy, advertise);
+
+
+ phy->autoneg = 1;
+ phy->speed = SPEED_10;
+ phy->duplex = DUPLEX_HALF;
+ phy->pause = 0;
+ phy->advertising = advertise;
+
+ bmcr = phy_read(phy, MII_BMCR);
+
+ /* Setup standard advertise */
+ adv = phy_read(phy, MII_ADVERTISE);
+ adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
+ if (bmcr & BMCR_SPEED100) {
+ if (advertise & ADVERTISED_100baseT_Half)
+ adv |= ADVERTISE_100HALF;
+ if (advertise & ADVERTISED_100baseT_Full)
+ adv |= ADVERTISE_100FULL;
+ } else {
+ if (advertise & ADVERTISED_10baseT_Half)
+ adv |= ADVERTISE_10HALF;
+ if (advertise & ADVERTISED_10baseT_Full)
+ adv |= ADVERTISE_10FULL;
+ }
+ phy_write(phy, MII_ADVERTISE, adv);
+
+ /* Start/Restart aneg */
+ ctl = phy_read(phy, MII_BMCR);
+ ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
+ phy_write(phy, MII_BMCR, ctl);
+
+ return 0;
+}
+
static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
{
u16 ctl;
@@ -226,6 +280,14 @@ static struct mii_phy_ops cis8201_phy_op
read_link:cis8201_read_link
};
+/* AC104 phy ops */
+static struct mii_phy_ops ac104_phy_ops = {
+ setup_aneg:ac104_setup_aneg,
+ setup_forced:genmii_setup_forced,
+ poll_link:genmii_poll_link,
+ read_link:genmii_read_link
+};
+
/* Generic implementation for most 10/100 PHYs */
static struct mii_phy_ops generic_phy_ops = {
setup_aneg:genmii_setup_aneg,
@@ -243,6 +305,15 @@ static struct mii_phy_def cis8201_phy_de
ops:&cis8201_phy_ops
};
+static struct mii_phy_def ac104_phy_def = {
+ phy_id:0x00225540,
+ phy_id_mask:0x00fffff0,
+ name:"AC104 Ethernet",
+ features:MII_BASIC_FEATURES,
+ magic_aneg:0,
+ ops:&ac104_phy_ops
+};
+
static struct mii_phy_def genmii_phy_def = {
phy_id:0x00000000,
phy_id_mask:0x00000000,
@@ -254,6 +325,7 @@ static struct mii_phy_def genmii_phy_def
static struct mii_phy_def *mii_phy_table[] = {
&cis8201_phy_def,
+ &ac104_phy_def,
&genmii_phy_def,
NULL
};
^ permalink raw reply
* [patch] mpc8560ads mtd map
From: Greg Weeks @ 2005-03-15 19:05 UTC (permalink / raw)
To: linuxppc-embedded
Add an MTD map for the flash on the mpc8560ads board.
Signed-off-by: Greg Weeks <greg.weeks@timesys.com>
--- /dev/null
+++ ppc-mpc8560ads/drivers/mtd/maps/mpc85xxads.c
@@ -0,0 +1,104 @@
+/*
+ * $Id$
+ *
+ * Mapping for Motorola MPC85xxADS flash
+ *
+ * Greg Weeks <greg.weeks@timesys.com>
+ *
+ * Copyright 2004 Timesys Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <asm/io.h>
+#include <platforms/85xx/mpc85xx_ads_common.h>
+
+static struct mtd_info *flash;
+
+static struct map_info mpc85xxads_map = {
+ .name = "mpc85xxads-flash",
+ .size = MPC85XXADS_FLASH_SIZE,
+ .bankwidth = 4,
+};
+
+static struct mtd_partition mpc85xxads_partitions[] = {
+ {
+ .name = "Linux JFFS2 Filesystem",
+ .offset = 0x0,
+ .size = 0x00800000,
+ },
+ {
+ .name = "Linux Kernel",
+ .offset = 0x00800000,
+ .size = 0x00200000,
+ },
+ {
+ .name = "Linux INITRD",
+ .offset = 0x00a00000,
+ .size = 0x00580000,
+ },
+ {
+ .name = "Bootloader",
+ .offset = 0x00f80000,
+ .size = 0x00080000,
+ }
+};
+
+int __init mpc85xxads_map_init(void)
+{
+ unsigned long mpc85xxads_flash_base = MPC85XXADS_FLASH_BASE;
+
+ mpc85xxads_map.phys = mpc85xxads_flash_base;
+ mpc85xxads_map.virt = (unsigned
long)ioremap(mpc85xxads_flash_base, mpc85xxads_map.size);
+
+ if (!mpc85xxads_map.virt) {
+ printk("Failed to ioremap flash\n");
+ return -EIO;
+ }
+
+ simple_map_init(&mpc85xxads_map);
+
+ flash = do_map_probe("cfi_probe", &mpc85xxads_map);
+ if (flash) {
+ flash->owner = THIS_MODULE;
+ add_mtd_partitions(flash, mpc85xxads_partitions,
+ ARRAY_SIZE(mpc85xxads_partitions));
+ } else {
+ iounmap((void *)mpc85xxads_map.virt);
+ printk("map probe failed for flash\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static void __exit mpc85xxads_map_exit(void)
+{
+ if (flash) {
+ del_mtd_partitions(flash);
+ map_destroy(flash);
+ }
+
+ if (mpc85xxads_map.virt) {
+ iounmap((void *)mpc85xxads_map.virt);
+ mpc85xxads_map.virt = 0;
+ }
+}
+
+module_init(mpc85xxads_map_init);
+module_exit(mpc85xxads_map_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Greg Weeks <greg.weeks@timesys.com>");
+MODULE_DESCRIPTION("MTD map and partitions for Motorola MPC85xxADS");
--- ppc-mpc8560ads/arch/ppc/platforms/85xx/mpc85xx_ads_common.h-orig
+++ ppc-mpc8560ads/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
@@ -47,4 +47,7 @@
#define MPC85XX_PCI1_IO_SIZE 0x01000000
+#define MPC85XXADS_FLASH_BASE 0xff000000
+#define MPC85XXADS_FLASH_SIZE 0x01000000
+
#endif /* __MACH_MPC85XX_ADS_H__ */
--- ppc-mpc8560ads/drivers/mtd/maps/Kconfig-orig
+++ ppc-mpc8560ads/drivers/mtd/maps/Kconfig
@@ -667,5 +667,12 @@
help
This enables access to the flash chip on the Sharp SL Series
of PDAs.
+config MTD_MPC85XXADS
+ tristate "Flash device mapped on the MPC85XXADS board"
+ depends on MTD_CFI && MTD_CFI_INTELEXT && MTD_PARTITIONS &&
MPC8560_ADS
+ help
+ This enables access to the Flash on the MPC85xxADS boards.
+ If you have such a board, say 'Y'.
+
endmenu
--- ppc-mpc8560ads/drivers/mtd/maps/Makefile-orig
+++ ppc-mpc8560ads/drivers/mtd/maps/Makefile
@@ -72,3 +72,4 @@
obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o
obj-$(CONFIG_MTD_DMV182) += dmv182.o
obj-$(CONFIG_MTD_SHARP_SL) += sharpsl-flash.o
+obj-$(CONFIG_MTD_MPC85XXADS) += mpc85xxads.o
^ permalink raw reply
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
From: Wade Farnsworth @ 2005-03-15 19:08 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
In-Reply-To: <20050315184153.GB28823@gate.ebshome.net>
On Tue, 2005-03-15 at 11:41, Eugene Surovegin wrote:
[snip]
>
> > diff -uprN linux-2.6.11-bk7/include/asm-ppc/reg.h linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h
> > --- linux-2.6.11-bk7/include/asm-ppc/reg.h 2005-03-11 16:25:22.000000000 -0700
> > +++ linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h 2005-03-14 10:05:47.000000000 -0700
> > @@ -449,6 +449,8 @@
> > #define PVR_STB03XXX 0x40310000
> > #define PVR_NP405H 0x41410000
> > #define PVR_NP405L 0x41610000
> > +#define PVR_440EP_RA 0x42221850
> > +#define PVR_440EP_RB 0x422218D3
>
>
> I don't think it's needed. There are plans to get rid of all not-used
> PVR defines.
The PVR for the Rev A is needed for a workaround in the IBM EMAC code
(see patch 3/3). If there is a better way to do this, or if it would be
better to put the PVR define somewhere else, please let me know.
Thanks for your comments.
Regards,
Wade Farnsworth
^ permalink raw reply
* Re: [patch] mpc8560ads mtd map
From: Mark A. Greer @ 2005-03-15 19:09 UTC (permalink / raw)
To: Greg Weeks; +Cc: linuxppc-embedded
In-Reply-To: <4237320D.9040200@timesys.com>
Greg Weeks wrote:
>
> Add an MTD map for the flash on the mpc8560ads board.
>
> Signed-off-by: Greg Weeks <greg.weeks@timesys.com>
<snip>
Most of the code in this patch can be eliminated if you set up the table
in your platform file and use the proper CONFIG_MTD_xxx options.
Mark
^ permalink raw reply
* Re: modem control for 8xx serial
From: Wolfgang Denk @ 2005-03-15 19:17 UTC (permalink / raw)
To: David Ho; +Cc: linuxppc-embedded
In-Reply-To: <OF53FB4D54.F4DBA8F0-ON85256FC5.0053C4E5-85256FC5.00542475@nanometrics.ca>
In message <OF53FB4D54.F4DBA8F0-ON85256FC5.0053C4E5-85256FC5.00542475@nanometrics.ca> you wrote:
>
> Has anyone implemented modem control in arch/ppc/8xx_io/serial.c. I don't
Sure. See the Linux trees on our CVS server.
And read the FAQ section in the DULG, too.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
As in certain cults it is possible to kill a process if you know its
true name. -- Ken Thompson and Dennis M. Ritchie
^ permalink raw reply
* Re: RFC: PHY Abstraction Layer II
From: James Chapman @ 2005-03-15 19:18 UTC (permalink / raw)
To: Andy Fleming; +Cc: netdev, David S. Miller, linuxppc-embedded
In-Reply-To: <ba5d844255b5ba76b2685f9397faf689@freescale.com>
Hi Andy,
I finally found some time to review your phy abstraction code.
I haven't reviewed the low level MII functions; I focused mostly on
its API to the net driver and whether it has the necessary hooks to
handle the various hardware that I know.
General comment: nice, clean code. No serious style or Linux kernel
core API issues that I can see.
Specific comments follow.
- It isn't obvious what has to be done in net drivers to hook up this
code. Consider writing a Documentation/networking/phy.txt to
describe typical net driver code changes needed.
- If a net driver is modified to use your new code, should it use any
functions from mii.c at all? I guess I'm unclear about the
relationship with mii.c.
- netif_carrier_on()/off() calls are done by mii.c on link state
changes. Consider doing the same inside your phy code.
- Some hardware does not use a separate irq for phy but instead
indicates phy events via the ethernet chip's irq.
There are registered phy_driver callbacks to handle things like
read/clear/ack interrupt status. But if my ethernet device's phy
interrupt is effectively one or more bits in the ethernet chip's
status register (where there is no separate phy interrupt), how
would this hook into your phy code? For example, in the interrupt
handler of mv643xx_eth, we check status bits that indicate link
state change from the same register that indicates rx/tx packet
events.
Also, NAPI drivers will disable irqs and poll for tx/rx while there
is work to do. If they have a combined tx/rx/phy interrupt then does
this pose other issues for hooking up the new phy code?
- What determines whether the phy driver uses interrupts or polling?
- The callback registered in phy_connect() is called when phy link
changes are detected. It is passed a struct device*. How about
letting the net driver register its struct net_device* which would
be passed back in the callback? It is likely that the callback will
need access to net driver data anyway. Some net drivers will need to
reconfigure their ethernet chip for duplex/speed setting changes,
for example. Passing in the struct net_device* also lets the phy
code call netif_xxx() functions such as netif_carrier_on()/off()
mentioned earlier as well as the netif_msg_xxx message control
macros.
- The callback function is only called by the phy timer poll as
far as I can tell. Shouldn't it also be called in the phy interrupt
handler when link state changes?
- Have all phy printk messages controlled by the netif_msg_ macros.
- Many drivers use mii.c to implement ethtool functions. I don't see
equivalents in your new code.
- Does include/linux/phy.h represent a public API for use by net
drivers or is it also the internal API used by various C files in
your phy code? It seems to contain some data/defs that are
private to the implementation. Separate some members of struct
phy_device into public and private parts and move the private bits
into separate files away from include/linux?
- phy_sanitize_settings() / phy_force_reduction()
I don't understand why this is done. Are you trying to handle
link negotiation in software for phy chips that can't autoneg?
Other minor notes:-
- Rename register_mdiobus() --> mdiobus_register()?
- I personally try to avoid listing parameter names in function header
comment blocks; they seldom contain useful info and they're a
maintenance overhead. If it would be useful for docbook-generated
documentation then ok, but your comment blocks don't follow that
format anyway.
I hope this was useful.
/james
Andy Fleming wrote:
>
> On Mar 10, 2005, at 17:01, James Chapman wrote:
>
>> Hi Andy,
>>
>> Can you elaborate on why this phy abstraction is needed?
>>
>> In your original post, you mentioned that you were going to post a
>> patch to show how your code would be hooked up in an existing net
>> driver. Did I miss it? It would help in understanding the pros and cons
>> of using genphy over using plain old mii.c.
>
>
> Hi James,
>
> I haven't posted it yet, since it's a large patch (it deletes a lot of
> code from my driver), but I can give a basic overview of how my driver
> hooks into this code:
>
> 1) The driver connects to the PHY when opened, calling phy_connect, and
> then clears some bits to declare functionality it doesn't support (my
> driver, for instance, does not support gigabit in half-duplex mode).
>
> 2) The driver implements a function which reads the speed/duplex
> settings, and modifies the controller registers as appropriate (also
> bringing the carrier up and down depending on link state). My driver
> needs to note whether it's gigabit or not (for GMII vs MII mode), and
> the duplex (to set the MAC full or half).
>
> Both of those steps are very straightforward. The PHY layer will invoke
> the callback whenever the link state changes, so the controller will
> always be up-to-date.
>
> 3) The third step is the part that can make things a little messier. My
> driver implements a second driver for the MDIO bus, which is connected
> through its registers. This bus needs to be registered, and the driver
> also needs to register. Then some code needs to be written to deal with
> initialization, and takedown. I can send out that patch anytime, if
> there's demand.
>
>>
>> btw, I recently posted a patch to add GigE support to mii.c which is
>> in Jeff's netdev-2.6 queue. Some register definitions were added in
>> mii.h that will collide with yours.
>
>
> Yeah, I ran in to some of those. I can't remember whether they're in
> the patch or not, I suspect not. I will have to submit a new patch to
> cover those (I just changed my code to use your definitions).
>
> Andy
^ permalink raw reply
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