* Re: [PATCH 2.6.12] mtd: Remove MTD map file for Chestnut platform.
From: Jörn Engel @ 2005-03-17 16:35 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linux-mtd, dwmw2, Embedded PPC Linux list
In-Reply-To: <42323A97.5070105@mvista.com>
On Fri, 11 March 2005 17:40:55 -0700, Mark A. Greer wrote:
>
> Remove Chestnut mtd map file.
>
> The chestnut now sets up its MTD map from its platform-specific file so
> the map file drivers/mtd/maps/chestnut.c is no longer needed. This
> patch removes the file & the Kconfig/Makefile hooks.
>
> Please apply.
Applied to mtd cvs. It will make its way to Linus eventually...
Thanks!
Jörn
--
Sometimes, asking the right question is already the answer.
-- Unknown
^ permalink raw reply
* Re: looking for a model for building CRAMFS(?)-based system
From: Wolfgang Denk @ 2005-03-17 16:32 UTC (permalink / raw)
To: Robert P. J. Day; +Cc: linuxppc-embedded
In-Reply-To: <Pine.LNX.4.61.0503171011220.20335@localhost.localdomain>
Dear Robert,
in message <Pine.LNX.4.61.0503171011220.20335@localhost.localdomain> you wrote:
>
> now this is the sticky part. imagine this system out in the field,
> where you need to make an update to something in the initrd in the
> root filesystem.
This is the szenario where an overly filesystem enters the stage.
See http://www.denx.de/e/news.php#MINI_FO
Note that the overlay filesystem was developed specifically for this
purpose; it has been in production use in some telecom products for
over a year now.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Only in our dreams we are free. The rest of the time we need wages.
- Terry Pratchett, _Wyrd Sisters_
^ permalink raw reply
* Re: [PATCH] ppc32: 3/2 HDPU platform fix PCI bus 1 enumeration
From: Brian Waite @ 2005-03-17 16:21 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20050317162509.GB5762@gate.ebshome.net>
[-- Attachment #1: Type: text/plain, Size: 1010 bytes --]
Lets try this again....
Signed-off-by: Brian Waite <waite@skycomputers.com>
Add the proper bus enumeration code that was missing for bus 1.
===== arch/ppc/platforms/hdpu.c 1.2 vs 1.3 =====
--- 1.2/arch/ppc/platforms/hdpu.c Thu Mar 17 10:42:34 2005
+++ 1.3/arch/ppc/platforms/hdpu.c Thu Mar 17 11:07:38 2005
@@ -260,6 +260,17 @@
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = hdpu_map_irq;
+ mv64x60_set_bus(&bh, 0, 0);
+ bh.hose_a->first_busno = 0;
+ bh.hose_a->last_busno = 0xff;
+ bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
+
+ bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
+ mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
+ bh.hose_b->last_busno = 0xff;
+ bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
+ bh.hose_b->first_busno);
+
ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH] ppc32: 3/2 HDPU platform fix PCI bus 1 enumeration
From: Eugene Surovegin @ 2005-03-17 16:25 UTC (permalink / raw)
To: Brian Waite; +Cc: linuxppc-embedded
In-Reply-To: <200503171111.39210.waite@skycomputers.com>
On Thu, Mar 17, 2005 at 11:11:34AM -0500, Brian Waite wrote:
> Signed-off-by: Brian Waite <waite@skycomputers.com>
> Add the proper bus enumeration code that was missing for bus 1.
>
> ===== linux-2.5/arch/ppc/platforms/hdpu.c 1.2 vs edited =====
> 262a263,273
> > mv64x60_set_bus(&bh, 0, 0);
> > bh.hose_a->first_busno = 0;
> > bh.hose_a->last_busno = 0xff;
> > bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
> >
> > bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
> > mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
> > bh.hose_b->last_busno = 0xff;
> > bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
> > bh.hose_b->first_busno);
> >
You probably didn't want to send _context_ diff :).
--
Eugene
^ permalink raw reply
* Re: [PATCH] ppc32: 3/2 HDPU platform fix PCI bus 1 enumeration
From: Brian Waite @ 2005-03-17 16:11 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <200503170953.02626.waite@skycomputers.com>
[-- Attachment #1: Type: text/plain, Size: 595 bytes --]
Signed-off-by: Brian Waite <waite@skycomputers.com>
Add the proper bus enumeration code that was missing for bus 1.
===== linux-2.5/arch/ppc/platforms/hdpu.c 1.2 vs edited =====
262a263,273
> mv64x60_set_bus(&bh, 0, 0);
> bh.hose_a->first_busno = 0;
> bh.hose_a->last_busno = 0xff;
> bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
>
> bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
> mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
> bh.hose_b->last_busno = 0xff;
> bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
> bh.hose_b->first_busno);
>
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* RE: looking for a model for building CRAMFS(?)-based system
From: Fillod Stephane @ 2005-03-17 16:17 UTC (permalink / raw)
To: Robert P. J. Day; +Cc: linuxppc-embedded
Robert P. J. Day wrote:
> now this is the sticky part. imagine this system out in the field,
> where you need to make an update to something in the initrd in the
> root filesystem.
You could get away with mirrored partitions, having version N and N-1
in flash, so a rollback is possible. But static partitions suck,
they are either too big (space wasted), either too small (!!).
Here's an idea I'd enjoy having feedback from: why not dedicating
the whole flash to a jffs2 space, allowing a kind of "dynamic"=20
partitioning with the composing filesystems in image files accessed
trough
loop devices? For example, the base system (libc, busybox, startup=20
scripts, ..) would be packed as a cramfs/squashfs file, put in the jffs2
storage. This image file would be mounted as root fs in 2 steps through=20
a loop device, thanks to a small patch against linux/init/do_mounts.c.=20
I've named this idea "Initial loopback (initlo) support", patch's
available.
Choosing the rootfs image is done through kernel command line.=20
For example, let's say /dev/mtdblock0 is the jffs2 storage, and the real
rootfs is a cramfs image file "rev1/rootfs.img" (from base of
mtdblock0).
The command line would be:
root=3D/dev/mtdblock0 lofile=3Drev1/rootfs.img
After bootup, the rootfs.img is the rootfs /, and the mtdblock0 space
is pivoted to /initlo, hence still accessible.
It's easy to have whatever number of rootfs versions, switching from=20
one another, and updating the kernel command line only when install
succeeded (=3Dno power fail,..).
During normal operation, the jffs2 storage is kept read-only for safety.
Only during install it is remounted read-write.
Applications can be packaged the same way (image file). jffs2 will be
happy
to store also configuration files/data and at least 2 kernel versions
(for=20
safe update). Great monitors like U-Boot are able to load the kernel
image
(and other firmwares) from jffs2. The jffs2 loader is portable.
Note: these filesystems in a filesystem look inefficient (read slow
startup),
but who cares, you're already relying on compression. Please note that
once
loaded in pagecache, the system runs at full speed. cramfs/squashfs are
at
advantage here over initrd, because only needed files make it into the
pagecache.
Comments welcome
--=20
Stephane
^ permalink raw reply
* Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board
From: S. van Beek @ 2005-03-17 15:57 UTC (permalink / raw)
To: Peter Ryser, S. van Beek; +Cc: Linuxppc-embedded
In-Reply-To: <4239A41E.7040200@xilinx.com>
> How did you add the Flash (EMC) peripheral? Did you use the Base System
> Builder to generate your hardware?
Yes, we started a new project using the base system builder with the same
options as the previous (working) project and flash, so the address range
should be ok. I'll check tomorrow, right now its time to go home ;)
Regards,
Sander
----- Original Message -----
From: "Peter Ryser" <Peter.Ryser@xilinx.com>
To: "S. van Beek" <nlv11891@prle>
Cc: <Linuxppc-embedded@ozlabs.org>
Sent: Thursday 17 March 2005 16:37
Subject: Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672
board
> How did you add the Flash (EMC) peripheral? Did you use the Base System
> Builder to generate your hardware?
>
> If you configure the hardware manually and use the OPB EMC make sure
> that you add the address range to the PLB2OPB bridge.
>
> - Peter
>
>
> S. van Beek wrote:
>
> > Hello there,
> >
> > This is our first post on this list, hi all!
> > We're two Dutch students working with a Virtex-II pro ff672 board from
> > Memec with the Communications 2 module. We've compiled a simple kernel
> > wich comes with MontaVista Linux 3.1 (2.4.20) with ethernet and a
> > serial port. It mounts its root filesystem over NFS and everything
> > seems to work nicely. The next step we wanted to make was
> > adding support for the Flash on the com board. We added the IP to the
> > hardware and loaded the new bitstream in the FPGA. Next thing, we
> > enabled support for MTD devices in the kernel. After that, the kernel
> > did not seem to boot anymore. It stopped at the message 'Now booting
> > the kernel'. So we read some documentation about debugging. We
> > recompiled this kernel with the -g -ggdb options and removed the -O
> > (optimalization) flag. Then we did not even see the ppc boot loader
> > messages anymore when trying to boot. So we tried to compile the first
> > kernel (with only serial and ethernet support) -wich worked fine
> > before- with debugging and it gave us the same result.. no output at
all.
> > Can anyone give us some hints on what we can try more to find out what
> > is going wrong?
> >
> > Regards,
> > Sander van Beek
> > Daniel van Os
> >
> >------------------------------------------------------------------------
> >
> >_______________________________________________
> >Linuxppc-embedded mailing list
> >Linuxppc-embedded@ozlabs.org
> >https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
>
>
>
^ permalink raw reply
* Re: looking for a model for building CRAMFS(?)-based system
From: Patrick Huesmann @ 2005-03-17 15:42 UTC (permalink / raw)
To: Robert P. J. Day; +Cc: linuxppc-embedded
In-Reply-To: <Pine.LNX.4.61.0503171011220.20335@localhost.localdomain>
Hi,
On Thu, 17 Mar 2005 10:14:41 -0500 (EST), Robert P. J. Day
<rpjday@mindspring.com> wrote:
> On Thu, 17 Mar 2005, Patrick Huesmann wrote:
> > When updating the initrd, the only thing necessary is a
> > eraseall /dev/mtdX
> > cat initrd.gz > /dev/mtdX
>
> now this is the sticky part. imagine this system out in the field,
> where you need to make an update to something in the initrd in the
> root filesystem.
If you know in advance what small parts you will want to change
(perhaps your main application, /var/www or whatever), you can use an
additional small partition, that holds only these files, mount it
somewhere in your rootfs, and you won't have to upload the whole
initrd when updating.
> one technique would be to, of couse, download an entirely new
> initrd.gz and reflash (hoping no one pulls the plug as you're doing
> it), as you describe above.
Power failure is not the only scenario when field updates go wrong.
We once had a stressed-out customer who uploaded the "readme" file to
the zImage partition. (Of course, you can prevent that with sanity
checks),
When something like this happens, it's always good to have a fallback
option, like a small bootloader that is NEVER updated, and can still
be used to flash the rest of the system over slow RS232 or whatever.
Regards,
Patrick
^ permalink raw reply
* Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board
From: Peter Ryser @ 2005-03-17 15:37 UTC (permalink / raw)
To: S. van Beek; +Cc: Linuxppc-embedded
In-Reply-To: <002001c52aef$d29dbb70$9c9c9182@ddns.htc.nl.philips.com>
How did you add the Flash (EMC) peripheral? Did you use the Base System
Builder to generate your hardware?
If you configure the hardware manually and use the OPB EMC make sure
that you add the address range to the PLB2OPB bridge.
- Peter
S. van Beek wrote:
> Hello there,
>
> This is our first post on this list, hi all!
> We're two Dutch students working with a Virtex-II pro ff672 board from
> Memec with the Communications 2 module. We've compiled a simple kernel
> wich comes with MontaVista Linux 3.1 (2.4.20) with ethernet and a
> serial port. It mounts its root filesystem over NFS and everything
> seems to work nicely. The next step we wanted to make was
> adding support for the Flash on the com board. We added the IP to the
> hardware and loaded the new bitstream in the FPGA. Next thing, we
> enabled support for MTD devices in the kernel. After that, the kernel
> did not seem to boot anymore. It stopped at the message 'Now booting
> the kernel'. So we read some documentation about debugging. We
> recompiled this kernel with the -g -ggdb options and removed the -O
> (optimalization) flag. Then we did not even see the ppc boot loader
> messages anymore when trying to boot. So we tried to compile the first
> kernel (with only serial and ethernet support) -wich worked fine
> before- with debugging and it gave us the same result.. no output at all.
> Can anyone give us some hints on what we can try more to find out what
> is going wrong?
>
> Regards,
> Sander van Beek
> Daniel van Os
>
>------------------------------------------------------------------------
>
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* [PATCH] ppc32: 0/2 add support for Sky Computers HDPU Compute blade
From: Brian Waite @ 2005-03-17 14:53 UTC (permalink / raw)
To: linuxppc-embedded, Mark A. Greer; +Cc: Andrew Morton
Add support for Sky Computers HDPU Compute blade
Signed-off-by: Brian Waite <waite@skycomputers.com>
The Sky Computers HDPU compute blade is an embedded compute platform for the
Sky Computers SMARTpac 600/1200 series. A blade consists of
ppc7445/ppc7447A, Marvell Discovery II, 100 BaseT ethernet, a single
PCI/PCI-X slot, and a PCI-X on-board Infiniband device.
This patch contains the base platform support required for booting Linux.
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/Kconfig
linux-2.5-hdpu/arch/ppc/Kconfig
--- linux-2.5/arch/ppc/Kconfig 2005-03-16 14:40:35 -05:00
+++ linux-2.5-hdpu/arch/ppc/Kconfig 2005-03-16 14:01:21 -05:00
@@ -538,6 +538,11 @@
config SPRUCE
bool "IBM-Spruce"
+config HDPU
+ bool "Sky-HDPU"
+ help
+ Select HDPU if configuring a Sky Computers Compute Blade.
+
config EV64260
bool "Marvell-EV64260BP"
help
@@ -748,7 +759,7 @@
config MV64360
bool
- depends on KATANA || RADSTONE_PPC7D
+ depends on KATANA || RADSTONE_PPC7D || HDPU
default y
config MV64360
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/configs/hdpu_defconfig
linux-2.5-hdpu/arch/ppc/configs/hdpu_defconfig
--- linux-2.5/arch/ppc/configs/hdpu_defconfig 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/arch/ppc/configs/hdpu_defconfig 2005-03-16 14:01:22 -05:00
@@ -0,0 +1,890 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.11
+# Wed Mar 16 12:43:19 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_LOCK_KERNEL=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_HOTPLUG=y
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_CPUSETS is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+
+#
+# Processor
+#
+CONFIG_6xx=y
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_ALTIVEC=y
+# CONFIG_TAU is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_PM is not set
+CONFIG_PPC_STD_MMU=y
+# CONFIG_NOT_COHERENT_CACHE is not set
+
+#
+# Platform options
+#
+# CONFIG_PPC_MULTIPLATFORM is not set
+# CONFIG_APUS is not set
+# CONFIG_KATANA is not set
+# CONFIG_WILLOW is not set
+# CONFIG_CPCI690 is not set
+# CONFIG_PCORE is not set
+# CONFIG_POWERPMC250 is not set
+# CONFIG_CHESTNUT is not set
+# CONFIG_SPRUCE is not set
+CONFIG_HDPU=y
+# CONFIG_EV64260 is not set
+# CONFIG_LOPEC is not set
+# CONFIG_MCPN765 is not set
+# CONFIG_MVME5100 is not set
+# CONFIG_PPLUS is not set
+# CONFIG_PRPMC750 is not set
+# CONFIG_PRPMC800 is not set
+# CONFIG_SANDPOINT is not set
+# CONFIG_RADSTONE_PPC7D is not set
+# CONFIG_ADIR is not set
+# CONFIG_K2 is not set
+# CONFIG_PAL4 is not set
+# CONFIG_GEMINI is not set
+# CONFIG_EST8260 is not set
+# CONFIG_SBC82xx is not set
+# CONFIG_SBS8260 is not set
+# CONFIG_RPX8260 is not set
+# CONFIG_TQM8260 is not set
+# CONFIG_ADS8272 is not set
+# CONFIG_PQ2FADS is not set
+# CONFIG_LITE5200 is not set
+# CONFIG_MPC834x_SYS is not set
+CONFIG_MV64360=y
+CONFIG_MV64X60=y
+
+#
+# Set bridge options
+#
+CONFIG_MV64X60_BASE=0xf1000000
+CONFIG_MV64X60_NEW_BASE=0xf1000000
+# CONFIG_SMP is not set
+# CONFIG_IRQ_ALL_CPUS is not set
+# CONFIG_NR_CPUS is not set
+CONFIG_PREEMPT=y
+CONFIG_HIGHMEM=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="root=/dev/nfs ip=auto"
+
+#
+# Bus options
+#
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+# CONFIG_HIGHMEM_START_BOOL is not set
+CONFIG_HIGHMEM_START=0xfe000000
+# CONFIG_LOWMEM_SIZE_BOOL is not set
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START_BOOL=y
+CONFIG_KERNEL_START=0x80000000
+# CONFIG_TASK_SIZE_BOOL is not set
+CONFIG_TASK_SIZE=0x80000000
+# CONFIG_BOOT_LOAD_BOOL is not set
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xfc000000
+CONFIG_MTD_PHYSMAP_LEN=0x04000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+CONFIG_SCSI_AIC7XXX=y
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
+CONFIG_AIC7XXX_RESET_DELAY_MS=15000
+# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
+CONFIG_AIC7XXX_DEBUG_MASK=0
+# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_IP_TCPDIAG is not set
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+# CONFIG_MV643XX_ETH_1 is not set
+# CONFIG_MV643XX_ETH_2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_MPSC=y
+CONFIG_SERIAL_MPSC_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_FS_NOR_ECC is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_DIRECTIO=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_TCP=y
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=15
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/platforms/Makefile
linux-2.5-hdpu/arch/ppc/platforms/Makefile
--- linux-2.5/arch/ppc/platforms/Makefile 2005-03-16 14:14:48 -05:00
+++ linux-2.5-hdpu/arch/ppc/platforms/Makefile 2005-03-10 14:34:49 -05:00
@@ -30,6 +30,7 @@
obj-$(CONFIG_K2) += k2.o
obj-$(CONFIG_LOPEC) += lopec.o
obj-$(CONFIG_KATANA) += katana.o
+obj-$(CONFIG_HDPU) += hdpu.o
obj-$(CONFIG_MCPN765) += mcpn765.o
obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o
obj-$(CONFIG_MVME5100) += mvme5100.o
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/platforms/hdpu.c
linux-2.5-hdpu/arch/ppc/platforms/hdpu.c
--- linux-2.5/arch/ppc/platforms/hdpu.c 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/arch/ppc/platforms/hdpu.c 2005-03-16 14:01:24 -05:00
@@ -0,0 +1,994 @@
+
+/*
+ * arch/ppc/platforms/hdpu_setup.c
+ *
+ * Board setup routines for the Sky Computers HDPU Compute Blade.
+ *
+ * Written by Brian Waite <waite@skycomputers.com>
+ *
+ * Based on code done by - Mark A. Greer <mgreer@mvista.com>
+ * Rabeeh Khoury - rabeeh@galileo.co.il
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/ide.h>
+#include <linux/seq_file.h>
+
+#include <linux/initrd.h>
+#include <linux/root_dev.h>
+#include <linux/smp.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/todc.h>
+#include <asm/mv64x60.h>
+#include <asm/ppcboot.h>
+#include <platforms/hdpu.h>
+#include <linux/mv643xx.h>
+#include <linux/device.h>
+#include <linux/mtd/physmap.h>
+
+#define BOARD_VENDOR "Sky Computers"
+#define BOARD_MACHINE "HDPU-CB-A"
+
+bd_t ppcboot_bd;
+int ppcboot_bd_valid = 0;
+
+static mv64x60_handle_t bh;
+
+extern char cmd_line[];
+
+unsigned long hdpu_find_end_of_memory(void);
+void hdpu_mpsc_progress(char *s, unsigned short hex);
+void hdpu_heartbeat(void);
+
+static void parse_bootinfo(unsigned long r3,
+ unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7);
+static void hdpu_set_l1pe(void);
+static void hdpu_cpustate_set(unsigned char new_state);
+#ifdef CONFIG_SMP
+static spinlock_t timebase_lock = SPIN_LOCK_UNLOCKED;
+static unsigned int timebase_upper = 0, timebase_lower = 0;
+extern int smp_tb_synchronized;
+
+void __devinit hdpu_tben_give(void);
+void __devinit hdpu_tben_take(void);
+#endif
+
+static int __init
+hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
+
+ if (hose->index == 0) {
+ static char pci_irq_table[][4] = {
+ {HDPU_PCI_0_IRQ, 0, 0, 0},
+ {HDPU_PCI_0_IRQ, 0, 0, 0},
+ };
+
+ const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+ } else {
+ static char pci_irq_table[][4] = {
+ {HDPU_PCI_1_IRQ, 0, 0, 0},
+ };
+
+ const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+ }
+}
+
+static void __init hdpu_intr_setup(void)
+{
+ mv64x60_write(&bh, MV64x60_GPP_IO_CNTL,
+ (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
+ (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
+ (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
+ (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
+ (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
+
+ /* XXXX Erranum FEr PCI-#8 */
+ mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9));
+ mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9));
+
+ /*
+ * Dismiss and then enable interrupt on GPP interrupt cause
+ * for CPU #0
+ */
+ mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13)));
+ mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
+
+ /*
+ * Dismiss and then enable interrupt on CPU #0 high cause reg
+ * BIT25 summarizes GPP interrupts 8-15
+ */
+ mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25));
+}
+
+static void __init hdpu_setup_peripherals(void)
+{
+ unsigned int val;
+
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
+ HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
+
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
+ HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
+
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
+ HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
+
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
+ HDPU_INTERNAL_SRAM_BASE,
+ HDPU_INTERNAL_SRAM_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
+
+ bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
+ mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0);
+
+ mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3));
+ mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
+ mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
+ ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
+
+ /* Enable pipelining */
+ mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
+ /* Enable Snoop Pipelineing */
+ mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
+
+ /*
+ * Change DRAM read buffer assignment.
+ * Assign read buffer 0 dedicated only for CPU,
+ * and the rest read buffer 1.
+ */
+ val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG);
+ val = val & 0x03ffffff;
+ val = val | 0xf8000000;
+ mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val);
+
+ /*
+ * Configure internal SRAM -
+ * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
+ * Parity enabled.
+ * Parity error propagation
+ * Arbitration not parked for CPU only
+ * Other bits are reserved.
+ */
+#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
+ mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
+#else
+ mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
+#endif
+
+ hdpu_intr_setup();
+}
+
+static void __init hdpu_setup_bridge(void)
+{
+ struct mv64x60_setup_info si;
+ int i;
+
+ memset(&si, 0, sizeof(si));
+
+ si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
+ si.pci_0.enable_bus = 1;
+ si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
+ si.pci_0.pci_io.pci_base_hi = 0;
+ si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
+ si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
+ si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
+ si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
+ si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
+ si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
+ si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_0.pci_cmd_bits = 0;
+ si.pci_0.latency_timer = 0x80;
+
+ si.pci_1.enable_bus = 1;
+ si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
+ si.pci_1.pci_io.pci_base_hi = 0;
+ si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
+ si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
+ si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
+ si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
+ si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
+ si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
+ si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
+ si.pci_1.pci_cmd_bits = 0;
+ si.pci_1.latency_timer = 0x80;
+
+ for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
+
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_NONE |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+
+ si.pci_0.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_NONE |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+
+#else
+ si.cpu_prot_options[i] = 0;
+ si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */
+ si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */
+ si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */
+
+ si.pci_0.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_WB |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+
+ si.pci_1.acc_cntl_options[i] =
+ MV64360_PCI_ACC_CNTL_SNOOP_WB |
+ MV64360_PCI_ACC_CNTL_SWAP_NONE |
+ MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
+ MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+#endif
+ }
+
+ hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
+
+ /* Lookup PCI host bridges */
+ mv64x60_init(&bh, &si);
+ pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = hdpu_map_irq;
+
+ ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
+
+ hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
+ /*
+ * Enabling of PCI internal-vs-external arbitration
+ * is a platform- and errata-dependent decision.
+ */
+ return;
+}
+
+#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
+static void __init hdpu_early_serial_map(void)
+{
+#ifdef CONFIG_KGDB
+ static char first_time = 1;
+
+#if defined(CONFIG_KGDB_TTYS0)
+#define KGDB_PORT 0
+#elif defined(CONFIG_KGDB_TTYS1)
+#define KGDB_PORT 1
+#else
+#error "Invalid kgdb_tty port"
+#endif
+
+ if (first_time) {
+ gt_early_mpsc_init(KGDB_PORT,
+ B9600 | CS8 | CREAD | HUPCL | CLOCAL);
+ first_time = 0;
+ }
+
+ return;
+#endif
+}
+#endif
+
+static void hdpu_init2(void)
+{
+ return;
+}
+
+#if defined(CONFIG_MV643XX_ETH)
+static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
+{
+
+ struct mv643xx_eth_platform_data *eth_pd;
+ eth_pd = pd->dev.platform_data;
+
+ eth_pd->port_serial_control =
+ mv64x60_read(&bh, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd->id) & ~1);
+
+ eth_pd->force_phy_addr = 1;
+ eth_pd->phy_addr = pd->id;
+ eth_pd->tx_queue_size = 400;
+ eth_pd->rx_queue_size = 800;
+}
+#endif
+
+static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd)
+{
+
+ struct mpsc_pdata *pdata;
+
+ pdata = (struct mpsc_pdata *)pd->dev.platform_data;
+
+ pdata->max_idle = 40;
+ if (ppcboot_bd_valid)
+ pdata->default_baud = ppcboot_bd.bi_baudrate;
+ else
+ pdata->default_baud = HDPU_DEFAULT_BAUD;
+ pdata->brg_clk_src = HDPU_MPSC_CLK_SRC;
+ pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ;
+}
+
+static int __init hdpu_platform_notify(struct device *dev)
+{
+ static struct {
+ char *bus_id;
+ void ((*rtn) (struct platform_device * pdev));
+ } dev_map[] = {
+ {
+ MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata},
+#if defined(CONFIG_MV643XX_ETH)
+ {
+ MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata},
+#endif
+ };
+ struct platform_device *pdev;
+ int i;
+
+ if (dev && dev->bus_id)
+ for (i = 0; i < ARRAY_SIZE(dev_map); i++)
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id,
+ BUS_ID_SIZE)) {
+
+ pdev = container_of(dev,
+ struct platform_device,
+ dev);
+ dev_map[i].rtn(pdev);
+ }
+
+ return 0;
+}
+
+static void __init hdpu_setup_arch(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress("hdpu_setup_arch: enter", 0);
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_SDA2;
+#endif
+
+ ppc_md.heartbeat = hdpu_heartbeat;
+
+ ppc_md.heartbeat_reset = HZ;
+ ppc_md.heartbeat_count = 1;
+
+ if (ppc_md.progress)
+ ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0);
+
+ /* Enable L1 Parity Bits */
+ hdpu_set_l1pe();
+
+ /* Enable L2 and L3 caches (if 745x) */
+ _set_L2CR(0x80080000);
+
+ if (ppc_md.progress)
+ ppc_md.progress("hdpu_setup_arch: enter", 0);
+
+ hdpu_setup_bridge();
+
+ hdpu_setup_peripherals();
+
+#ifdef CONFIG_SERIAL_MPSC_CONSOLE
+ hdpu_early_serial_map();
+#endif
+
+ printk("SKY HDPU Compute Blade \n");
+
+ if (ppc_md.progress)
+ ppc_md.progress("hdpu_setup_arch: exit", 0);
+
+ hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
+ return;
+}
+static void __init hdpu_init_irq(void)
+{
+ mv64360_init_irq();
+}
+
+static void __init hdpu_set_l1pe()
+{
+ unsigned long ictrl;
+ asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
+ ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
+ asm volatile ("mtspr 1011, %0"::"r" (ictrl));
+}
+
+/*
+ * Set BAT 1 to map 0xf1000000 to end of physical memory space.
+ */
+static __inline__ void hdpu_set_bat(void)
+{
+ mb();
+ mtspr(SPRN_DBAT1U, 0xf10001fe);
+ mtspr(SPRN_DBAT1L, 0xf100002a);
+ mb();
+
+ return;
+}
+
+unsigned long __init hdpu_find_end_of_memory(void)
+{
+ return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
+ MV64x60_TYPE_MV64360);
+}
+
+static void hdpu_reset_board(void)
+{
+ volatile int infinite = 1;
+
+ hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
+
+ local_irq_disable();
+
+ /* Clear all the LEDs */
+ mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) |
+ (1 << 5) | (1 << 6)));
+
+ /* disable and invalidate the L2 cache */
+ _set_L2CR(0);
+ _set_L2CR(0x200000);
+
+ /* flush and disable L1 I/D cache */
+ __asm__ __volatile__
+ ("\n"
+ "mfspr 3,1008\n"
+ "ori 5,5,0xcc00\n"
+ "ori 4,3,0xc00\n"
+ "andc 5,3,5\n"
+ "sync\n"
+ "mtspr 1008,4\n"
+ "isync\n" "sync\n" "mtspr 1008,5\n" "isync\n" "sync\n");
+
+ /* Hit the reset bit */
+ mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3));
+
+ while (infinite)
+ infinite = infinite;
+
+ return;
+}
+
+static void hdpu_restart(char *cmd)
+{
+ volatile ulong i = 10000000;
+
+ hdpu_reset_board();
+
+ while (i-- > 0) ;
+ panic("restart failed\n");
+}
+
+static void hdpu_halt(void)
+{
+ local_irq_disable();
+
+ hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
+
+ /* Clear all the LEDs */
+ mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) |
+ (1 << 6)));
+ while (1) ;
+ /* NOTREACHED */
+}
+
+static void hdpu_power_off(void)
+{
+ hdpu_halt();
+ /* NOTREACHED */
+}
+
+static int hdpu_show_cpuinfo(struct seq_file *m)
+{
+ uint pvid;
+
+ pvid = mfspr(SPRN_PVR);
+ seq_printf(m, "vendor\t\t: Sky Computers\n");
+ seq_printf(m, "machine\t\t: HDPU Compute Blade\n");
+ seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
+ pvid, (pvid & (1 << 15) ? "IBM" : "Motorola"));
+
+ return 0;
+}
+
+static void __init hdpu_calibrate_decr(void)
+{
+ ulong freq;
+
+ if (ppcboot_bd_valid)
+ freq = ppcboot_bd.bi_busfreq / 4;
+ else
+ freq = 133000000;
+
+ printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
+ freq / 1000000, freq % 1000000);
+
+ tb_ticks_per_jiffy = freq / HZ;
+ tb_to_us = mulhwu_scale_factor(freq, 1000000);
+
+ return;
+}
+
+static void parse_bootinfo(unsigned long r3,
+ unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ bd_t *bd = NULL;
+ char *cmdline_start = NULL;
+ int cmdline_len = 0;
+
+ if (r3) {
+ if ((r3 & 0xf0000000) == 0)
+ r3 += KERNELBASE;
+ if ((r3 & 0xf0000000) == KERNELBASE) {
+ bd = (void *)r3;
+
+ memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd));
+ ppcboot_bd_valid = 1;
+ }
+ }
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (r4 && r5 && r5 > r4) {
+ if ((r4 & 0xf0000000) == 0)
+ r4 += KERNELBASE;
+ if ((r5 & 0xf0000000) == 0)
+ r5 += KERNELBASE;
+ if ((r4 & 0xf0000000) == KERNELBASE) {
+ initrd_start = r4;
+ initrd_end = r5;
+ initrd_below_start_ok = 1;
+ }
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+ if (r6 && r7 && r7 > r6) {
+ if ((r6 & 0xf0000000) == 0)
+ r6 += KERNELBASE;
+ if ((r7 & 0xf0000000) == 0)
+ r7 += KERNELBASE;
+ if ((r6 & 0xf0000000) == KERNELBASE) {
+ cmdline_start = (void *)r6;
+ cmdline_len = (r7 - r6);
+ strncpy(cmd_line, cmdline_start, cmdline_len);
+ }
+ }
+}
+
+#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
+static int hdpu_ide_check_region(ide_ioreg_t from, unsigned int extent)
+{
+ return check_region(from, extent);
+}
+
+static void
+hdpu_ide_request_region(ide_ioreg_t from, unsigned int extent, const char
*name)
+{
+ request_region(from, extent, name);
+ return;
+}
+
+static void hdpu_ide_release_region(ide_ioreg_t from, unsigned int extent)
+{
+ release_region(from, extent);
+ return;
+}
+
+static void __init
+hdpu_ide_pci_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
+ ide_ioreg_t ctrl_port, int *irq)
+{
+ struct pci_dev *dev;
+
+ pci_for_each_dev(dev) {
+ if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
+ ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
+ hw->irq = dev->irq;
+
+ if (irq != NULL) {
+ *irq = dev->irq;
+ }
+ }
+ }
+
+ return;
+}
+#endif
+
+void hdpu_heartbeat(void)
+{
+ if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
+ mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5));
+ else
+ mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5));
+
+ ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
+
+}
+
+static void __init hdpu_map_io(void)
+{
+ io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO);
+}
+
+#ifdef CONFIG_SMP
+char hdpu_smp0[] = "SMP Cpu #0";
+char hdpu_smp1[] = "SMP Cpu #1";
+
+static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ volatile unsigned int doorbell;
+
+ doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL);
+
+ /* Ack the doorbell interrupts */
+ mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
+
+ if (doorbell & 1) {
+ smp_message_recv(0, regs);
+ }
+ if (doorbell & 2) {
+ smp_message_recv(1, regs);
+ }
+ if (doorbell & 4) {
+ smp_message_recv(2, regs);
+ }
+ if (doorbell & 8) {
+ smp_message_recv(3, regs);
+ }
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ volatile unsigned int doorbell;
+
+ doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL);
+
+ /* Ack the doorbell interrupts */
+ mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
+
+ if (doorbell & 1) {
+ smp_message_recv(0, regs);
+ }
+ if (doorbell & 2) {
+ smp_message_recv(1, regs);
+ }
+ if (doorbell & 4) {
+ smp_message_recv(2, regs);
+ }
+ if (doorbell & 8) {
+ smp_message_recv(3, regs);
+ }
+ return IRQ_HANDLED;
+}
+
+static void smp_hdpu_CPU_two(void)
+{
+ __asm__ __volatile__
+ ("\n"
+ "lis 3,0x0000\n"
+ "ori 3,3,0x00c0\n"
+ "mtspr 26, 3\n" "li 4,0\n" "mtspr 27,4\n" "rfi");
+
+}
+
+static int smp_hdpu_probe(void)
+{
+ int *cpu_count_reg;
+ int num_cpus = 0;
+
+ cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE);
+ if (cpu_count_reg) {
+ num_cpus = (*cpu_count_reg >> 20) & 0x3;
+ iounmap(cpu_count_reg);
+ }
+
+ /* Validate the bits in the CPLD. If we could not map the reg, return 2.
+ * If the register reported 0 or 3, return 2.
+ * Older CPLD revisions set these bits to all ones (val = 3).
+ */
+ if ((num_cpus < 1) || (num_cpus > 2)) {
+ printk
+ ("Unable to determine the number of processors %d . deafulting to 2.
\n",
+ num_cpus);
+ num_cpus = 2;
+ }
+ return num_cpus;
+}
+
+static void
+smp_hdpu_message_pass(int target, int msg, unsigned long data, int wait)
+{
+ if (msg > 0x3) {
+ printk("SMP %d: smp_message_pass: unknown msg %d\n",
+ smp_processor_id(), msg);
+ return;
+ }
+ switch (target) {
+ case MSG_ALL:
+ mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
+ mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
+ break;
+ case MSG_ALL_BUT_SELF:
+ if (smp_processor_id())
+ mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
+ else
+ mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
+ break;
+ default:
+ if (target == 0)
+ mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
+ else
+ mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
+ break;
+ }
+}
+
+static void smp_hdpu_kick_cpu(int nr)
+{
+ volatile unsigned int *bootaddr;
+
+ if (ppc_md.progress)
+ ppc_md.progress("smp_hdpu_kick_cpu", 0);
+
+ hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
+
+ /* Disable BootCS. Must also reduce the windows size to zero. */
+ bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0);
+
+ bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE);
+ if (!bootaddr) {
+ if (ppc_md.progress)
+ ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
+ return;
+ }
+
+ memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20);
+
+ /* map SRAM to 0xfff00000 */
+ bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
+
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
+ 0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
+
+ /* Enable CPU1 arbitration */
+ mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9));
+
+ /*
+ * Wait 100mSecond until other CPU has reached __secondary_start.
+ * When it reaches, it is permittable to rever the SRAM mapping etc...
+ */
+ mdelay(100);
+ *(unsigned long *)KERNELBASE = nr;
+ asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
+
+ iounmap(bootaddr);
+
+ /* Set up window for internal sram (256KByte insize) */
+ bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
+ HDPU_INTERNAL_SRAM_BASE,
+ HDPU_INTERNAL_SRAM_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
+ /*
+ * Set up windows for embedded FLASH (using boot CS window).
+ */
+
+ bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
+ mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
+ HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
+}
+
+static void smp_hdpu_setup_cpu(int cpu_nr)
+{
+ if (cpu_nr == 0) {
+ if (ppc_md.progress)
+ ppc_md.progress("smp_hdpu_setup_cpu 0", 0);
+ mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
+ mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
+ request_irq(60, hdpu_smp_cpu0_int_handler,
+ SA_INTERRUPT, hdpu_smp0, 0);
+ }
+
+ if (cpu_nr == 1) {
+ if (ppc_md.progress)
+ ppc_md.progress("smp_hdpu_setup_cpu 1", 0);
+
+ hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
+ CPUSTATE_KERNEL_CPU1_OK);
+
+ /* Enable L1 Parity Bits */
+ hdpu_set_l1pe();
+
+ /* Enable L2 cache */
+ _set_L2CR(0);
+ _set_L2CR(0x80080000);
+
+ mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
+ mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
+ request_irq(28, hdpu_smp_cpu1_int_handler,
+ SA_INTERRUPT, hdpu_smp1, 0);
+ }
+
+}
+
+void __devinit hdpu_tben_give()
+{
+ volatile unsigned long *val = 0;
+
+ /* By writing 0 to the TBEN_BASE, the timebases is frozen */
+ val = ioremap(HDPU_TBEN_BASE, 4);
+ *val = 0;
+ mb();
+
+ spin_lock(&timebase_lock);
+ timebase_upper = get_tbu();
+ timebase_lower = get_tbl();
+ spin_unlock(&timebase_lock);
+
+ while (timebase_upper || timebase_lower)
+ barrier();
+
+ /* By writing 1 to the TBEN_BASE, the timebases is thawed */
+ *val = 1;
+ mb();
+
+ iounmap(val);
+
+}
+
+void __devinit hdpu_tben_take()
+{
+ while (!(timebase_upper || timebase_lower))
+ barrier();
+
+ spin_lock(&timebase_lock);
+ set_tb(timebase_upper, timebase_lower);
+ timebase_upper = 0;
+ timebase_lower = 0;
+ spin_unlock(&timebase_lock);
+}
+
+static struct smp_ops_t hdpu_smp_ops = {
+ .message_pass = smp_hdpu_message_pass,
+ .probe = smp_hdpu_probe,
+ .kick_cpu = smp_hdpu_kick_cpu,
+ .setup_cpu = smp_hdpu_setup_cpu,
+ .give_timebase = hdpu_tben_give,
+ .take_timebase = hdpu_tben_take,
+};
+#endif /* CONFIG_SMP */
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ parse_bootinfo(r3, r4, r5, r6, r7);
+
+ isa_mem_base = 0;
+
+ ppc_md.setup_arch = hdpu_setup_arch;
+ ppc_md.init = hdpu_init2;
+ ppc_md.show_cpuinfo = hdpu_show_cpuinfo;
+ ppc_md.init_IRQ = hdpu_init_irq;
+ ppc_md.get_irq = mv64360_get_irq;
+ ppc_md.restart = hdpu_restart;
+ ppc_md.power_off = hdpu_power_off;
+ ppc_md.halt = hdpu_halt;
+ ppc_md.find_end_of_memory = hdpu_find_end_of_memory;
+ ppc_md.calibrate_decr = hdpu_calibrate_decr;
+ ppc_md.setup_io_mappings = hdpu_map_io;
+
+ bh.p_base = CONFIG_MV64X60_NEW_BASE;
+ bh.v_base = (unsigned long *)bh.p_base;
+
+ hdpu_set_bat();
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG)
+ ppc_md.progress = hdpu_mpsc_progress; /* embedded UART */
+ mv64x60_progress_init(bh.p_base);
+#endif /* CONFIG_SERIAL_TEXT_DEBUG */
+
+#ifdef CONFIG_SMP
+ ppc_md.smp_ops = &hdpu_smp_ops;
+#endif /* CONFIG_SMP */
+
+#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
+ platform_notify = hdpu_platform_notify;
+#endif
+ return;
+}
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
+/* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
+void hdpu_mpsc_progress(char *s, unsigned short hex)
+{
+ while (mv64x60_read(&bh, MV64360_WHO_AM_I) !=
+ mv64x60_read(&bh, MV64360_SEMAPHORE_0)) {
+ }
+ mv64x60_mpsc_progress(s, hex);
+ mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff);
+}
+#endif
+
+static void hdpu_cpustate_set(unsigned char new_state)
+{
+ unsigned int state = (new_state << 21);
+ mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
+ mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
+}
+
+#ifdef CONFIG_MTD_PHYSMAP
+static struct mtd_partition hdpu_partitions[] = {
+ {
+ .name = "Root FS",
+ .size = 0x03400000,
+ .offset = 0,
+ .mask_flags = 0,
+ },{
+ .name = "User FS",
+ .size = 0x00800000,
+ .offset = 0x03400000,
+ .mask_flags = 0,
+ },{
+ .name = "Kernel Image",
+ .size = 0x002C0000,
+ .offset = 0x03C00000,
+ .mask_flags = 0,
+ },{
+ .name = "bootEnv",
+ .size = 0x00040000,
+ .offset = 0x03EC0000,
+ .mask_flags = 0,
+ },{
+ .name = "bootROM",
+ .size = 0x00100000,
+ .offset = 0x03F00000,
+ .mask_flags = 0,
+ }
+};
+
+static int __init hdpu_setup_mtd(void)
+{
+
+ physmap_set_partitions(hdpu_partitions, 5);
+ return 0;
+}
+
+arch_initcall(hdpu_setup_mtd);
+#endif
+
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/platforms/hdpu.h
linux-2.5-hdpu/arch/ppc/platforms/hdpu.h
--- linux-2.5/arch/ppc/platforms/hdpu.h 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/arch/ppc/platforms/hdpu.h 2005-03-16 14:01:24 -05:00
@@ -0,0 +1,82 @@
+/*
+ * arch/ppc/platforms/hdpu.h
+ *
+ * Definitions for Sky Computers HDPU board.
+ *
+ * Brian Waite <waite@skycomputers.com>
+ *
+ * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
+ * Based on code done by Mark A. Greer <mgreer@mvista.com>
+ * Based on code done by Tim Montgomery <timm@artesyncp.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
+ * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
+ * We'll only use one PCI MEM window on each PCI bus.
+ *
+ * This is the CPU physical memory map (windows must be at least 64K and
start
+ * on a boundary that is a multiple of the window size):
+ *
+ * 0x80000000-0x8fffffff - PCI 0 MEM
+ * 0xa0000000-0xafffffff - PCI 1 MEM
+ * 0xc0000000-0xc0ffffff - PCI 0 I/O
+ * 0xc1000000-0xc1ffffff - PCI 1 I/O
+
+ * 0xf1000000-0xf100ffff - MV64360 Registers
+ * 0xf1010000-0xfb9fffff - HOLE
+ * 0xfbfa0000-0xfbfaffff - TBEN
+ * 0xfbf00000-0xfbfbffff - NEXUS
+ * 0xfbfc0000-0xfbffffff - Internal SRAM
+ * 0xfc000000-0xffffffff - Boot window
+ */
+
+#ifndef __PPC_PLATFORMS_HDPU_H
+#define __PPC_PLATFORMS_HDPU_H
+
+/* CPU Physical Memory Map setup. */
+#define HDPU_BRIDGE_REG_BASE 0xf1000000
+
+#define HDPU_TBEN_BASE 0xfbfa0000
+#define HDPU_TBEN_SIZE 0x00010000
+#define HDPU_NEXUS_ID_BASE 0xfbfb0000
+#define HDPU_NEXUS_ID_SIZE 0x00010000
+#define HDPU_INTERNAL_SRAM_BASE 0xfbfc0000
+#define HDPU_INTERNAL_SRAM_SIZE 0x00040000
+#define HDPU_EMB_FLASH_BASE 0xfc000000
+#define HDPU_EMB_FLASH_SIZE 0x04000000
+
+/* PCI Mappings */
+
+#define HDPU_PCI0_MEM_START_PROC_ADDR 0x80000000
+#define HDPU_PCI0_MEM_START_PCI_HI_ADDR 0x00000000
+#define HDPU_PCI0_MEM_START_PCI_LO_ADDR HDPU_PCI0_MEM_START_PROC_ADDR
+#define HDPU_PCI0_MEM_SIZE 0x10000000
+
+#define HDPU_PCI1_MEM_START_PROC_ADDR 0xc0000000
+#define HDPU_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
+#define HDPU_PCI1_MEM_START_PCI_LO_ADDR HDPU_PCI1_MEM_START_PROC_ADDR
+#define HDPU_PCI1_MEM_SIZE 0x20000000
+
+#define HDPU_PCI0_IO_START_PROC_ADDR 0xc0000000
+#define HDPU_PCI0_IO_START_PCI_ADDR 0x00000000
+#define HDPU_PCI0_IO_SIZE 0x01000000
+
+#define HDPU_PCI1_IO_START_PROC_ADDR 0xc1000000
+#define HDPU_PCI1_IO_START_PCI_ADDR 0x01000000
+#define HDPU_PCI1_IO_SIZE 0x01000000
+
+#define HDPU_DEFAULT_BAUD 115200
+#define HDPU_MPSC_CLK_SRC 8 /* TCLK */
+#define HDPU_MPSC_CLK_FREQ 133000000 /* 133 Mhz */
+
+#define HDPU_PCI_0_IRQ (8+64)
+#define HDPU_PCI_1_IRQ (13+64)
+
+#endif /* __PPC_PLATFORMS_HDPU_H */
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/syslib/Makefile
linux-2.5-hdpu/arch/ppc/syslib/Makefile
--- linux-2.5/arch/ppc/syslib/Makefile 2005-03-16 14:14:50 -05:00
+++ linux-2.5-hdpu/arch/ppc/syslib/Makefile 2005-03-16 14:01:25 -05:00
@@ -53,6 +53,7 @@
obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \
pci_auto.o
obj-$(CONFIG_LOPEC) += i8259.o pci_auto.o todc_time.o
+obj-$(CONFIG_HDPU) += pci_auto.o
obj-$(CONFIG_LUAN) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_KATANA) += pci_auto.o
obj-$(CONFIG_MCPN765) += todc_time.o indirect_pci.o pci_auto.o \
^ permalink raw reply
* [PATCH] ppc32:1/2 add support for Sky Computers HDPU Compute blade enhanced features
From: Brian Waite @ 2005-03-17 14:53 UTC (permalink / raw)
To: linuxppc-embedded, Mark A. Greer; +Cc: Andrew Morton
Add support for Sky Computers HDPU Compute blade enhanced features
Signed-off-by: Brian Waite <waite@skycomputers.com>
The Sky Computers HDPU compute blade is an embedded compute platform for the
Sky Computers SMARTpac 600/1200 series. The blade consists of
ppc7445/ppc7447A UP or SMP, Marvell Discovery II, 100 BaseT ethernet, a
single
PCI/PCI-X slot, and a PCI-X on-board Infiniband device.
This patch contains drivers for enhanced features of the HDPU compute blade.
Namely, 2 drivers for registers used by the Health monitoring co-processor.
The cpustate
register is a write only register used to convey critical states to the health
monitor and the
nexus registers provides a read-only interface from the health monitoring
system to provide
location based information.
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/Kconfig
linux-2.5-hdpu/arch/ppc/Kconfig
--- linux-2.5/arch/ppc/Kconfig 2005-03-16 14:52:37 -05:00
+++ linux-2.5-hdpu/arch/ppc/Kconfig 2005-03-16 14:01:21 -05:00
@@ -543,6 +543,12 @@
help
Select HDPU if configuring a Sky Computers Compute Blade.
+config HDPU_FEATURES
+ depends HDPU
+ tristate "HDPU-Features"
+ help
+ Select to enable HDPU enhanced features.
+
config EV64260
bool "Marvell-EV64260BP"
help
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/include/linux/hdpu_features.h
linux-2.5-hdpu/include/linux/hdpu_features.h
--- linux-2.5/include/linux/hdpu_features.h 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/include/linux/hdpu_features.h 2005-03-16 14:03:18 -05:00
@@ -0,0 +1,26 @@
+#include <linux/spinlock.h>
+
+struct cpustate_t {
+ spinlock_t lock;
+ int excl;
+ int open_count;
+ unsigned char cached_val;
+ int inited;
+ unsigned long *set_addr;
+ unsigned long *clr_addr;
+};
+
+
+#define HDPU_CPUSTATE_NAME "hdpu cpustate"
+#define HDPU_NEXUS_NAME "hdpu nexus"
+
+#define CPUSTATE_KERNEL_MAJOR 0x10
+
+#define CPUSTATE_KERNEL_INIT_DRV 0 /* CPU State Driver Initialized */
+#define CPUSTATE_KERNEL_INIT_PCI 1 /* 64360 PCI Busses Init */
+#define CPUSTATE_KERNEL_INIT_REG 2 /* 64360 Bridge Init */
+#define CPUSTATE_KERNEL_CPU1_KICK 3 /* Boot cpu 1 */
+#define CPUSTATE_KERNEL_CPU1_OK 4 /* Cpu 1 has checked in */
+#define CPUSTATE_KERNEL_OK 5 /* Terminal state */
+#define CPUSTATE_KERNEL_RESET 14 /* Board reset via SW*/
+#define CPUSTATE_KERNEL_HALT 15 /* Board halted via SW*/
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/arch/ppc/platforms/hdpu.c
linux-2.5-hdpu/arch/ppc/platforms/hdpu.c
--- linux-2.5/arch/ppc/platforms/hdpu.c 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/arch/ppc/platforms/hdpu.c 2005-03-16 14:03:18 -05:00
36a37
> #include <linux/hdpu_features.h>
57a59
> static void hdpu_cpustate_set(unsigned char new_state);
252a255,256
> hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
>
260a265
> hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
330a336,344
> #if defined(CONFIG_HDPU_FEATURES)
> static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
> {
> struct platform_device *pds[1];
> pds[0] = pd;
> mv64x60_pd_fixup(&bh, pds, 1);
> }
> #endif
>
342a357,360
> #if defined(CONFIG_HDPU_FEATURES)
> {
> HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata},
> #endif
405a424
> hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
443a463,464
> hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
>
487a509,510
> hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
>
755a779,780
> hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
>
819a845,847
> hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
> CPUSTATE_KERNEL_CPU1_OK);
>
933a962,968
> static void hdpu_cpustate_set(unsigned char new_state)
> {
> unsigned int state = (new_state << 21);
> mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
> mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
> }
>
973a1009,1051
> #ifdef CONFIG_HDPU_FEATURES
>
> static struct resource hdpu_cpustate_resources[] = {
> [0] = {
> .name = "addr base",
> .start = MV64x60_GPP_VALUE_SET,
> .end = MV64x60_GPP_VALUE_CLR + 1,
> .flags = IORESOURCE_MEM,
> },
> };
>
> static struct resource hdpu_nexus_resources[] = {
> [0] = {
> .name = "nexus register",
> .start = HDPU_NEXUS_ID_BASE,
> .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE,
> .flags = IORESOURCE_MEM,
> },
> };
>
> static struct platform_device hdpu_cpustate_device = {
> .name = HDPU_CPUSTATE_NAME,
> .id = 0,
> .num_resources = ARRAY_SIZE(hdpu_cpustate_resources),
> .resource = hdpu_cpustate_resources,
> };
>
> static struct platform_device hdpu_nexus_device = {
> .name = HDPU_NEXUS_NAME,
> .id = 0,
> .num_resources = ARRAY_SIZE(hdpu_nexus_resources),
> .resource = hdpu_nexus_resources,
> };
>
> static int __init hdpu_add_pds(void)
> {
> platform_device_register(&hdpu_cpustate_device);
> platform_device_register(&hdpu_nexus_device);
> return 0;
> }
>
> arch_initcall(hdpu_add_pds);
> #endif
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/drivers/misc/Makefile
linux-2.5-hdpu/drivers/misc/Makefile
--- linux-2.5/drivers/misc/Makefile 2005-03-16 14:15:39 -05:00
+++ linux-2.5-hdpu/drivers/misc/Makefile 2005-03-16 14:02:09 -05:00
@@ -4,3 +4,4 @@
obj- := misc.o # Dummy rule to force built-in.o to be made
obj-$(CONFIG_IBM_ASM) += ibmasm/
+obj-$(CONFIG_HDPU_FEATURES) += hdpuftrs/
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/drivers/misc/hdpuftrs/Makefile
linux-2.5-hdpu/drivers/misc/hdpuftrs/Makefile
--- linux-2.5/drivers/misc/hdpuftrs/Makefile 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/drivers/misc/hdpuftrs/Makefile 2005-03-16 14:02:09 -05:00
@@ -0,0 +1 @@
+obj-$(CONFIG_HDPU_FEATURES) := hdpu_cpustate.o hdpu_nexus.o
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/drivers/misc/hdpuftrs/hdpu_cpustate.c
linux-2.5-hdpu/drivers/misc/hdpuftrs/hdpu_cpustate.c
--- linux-2.5/drivers/misc/hdpuftrs/hdpu_cpustate.c 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/drivers/misc/hdpuftrs/hdpu_cpustate.c 2005-03-16 14:02:09
-05:00
@@ -0,0 +1,234 @@
+/*
+ * Sky CPU State Driver
+ *
+ * Copyright (C) 2002 Brian Waite
+ *
+ * This driver allows use of the CPU state bits
+ * It exports the /dev/sky_cpustate and also
+ * /proc/sky_cpustate pseudo-file for status information.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/miscdevice.h>
+#include <linux/pci.h>
+#include <linux/proc_fs.h>
+#include <linux/device.h>
+#include <asm/uaccess.h>
+#include <linux/hdpu_features.h>
+
+#define SKY_CPUSTATE_VERSION "1.1"
+
+static int hdpu_cpustate_probe(struct device *ddev);
+static int hdpu_cpustate_remove(struct device *ddev);
+
+struct cpustate_t cpustate;
+
+static int cpustate_get_ref(int excl)
+{
+
+ int retval = -EBUSY;
+
+ spin_lock(&cpustate.lock);
+
+ if (cpustate.excl)
+ goto out_busy;
+
+ if (excl) {
+ if (cpustate.open_count)
+ goto out_busy;
+ cpustate.excl = 1;
+ }
+
+ cpustate.open_count++;
+ retval = 0;
+
+ out_busy:
+ spin_unlock(&cpustate.lock);
+ return retval;
+}
+
+static int cpustate_free_ref(void)
+{
+
+ spin_lock(&cpustate.lock);
+
+ cpustate.excl = 0;
+ cpustate.open_count--;
+
+ spin_unlock(&cpustate.lock);
+ return 0;
+}
+
+unsigned char cpustate_get_state(void)
+{
+
+ return cpustate.cached_val;
+}
+
+void cpustate_set_state(unsigned char new_state)
+{
+ unsigned int state = (new_state << 21);
+
+#ifdef DEBUG_CPUSTATE
+ printk("CPUSTATE -> 0x%x\n", new_state);
+#endif
+ spin_lock(&cpustate.lock);
+ cpustate.cached_val = new_state;
+ writel((0xff << 21), cpustate.clr_addr);
+ writel(state, cpustate.set_addr);
+ spin_unlock(&cpustate.lock);
+}
+
+/*
+ * Now all the various file operations that we export.
+ */
+
+static ssize_t cpustate_read(struct file *file, char *buf,
+ size_t count, loff_t * ppos)
+{
+ unsigned char data;
+
+ if (count < 0)
+ return -EFAULT;
+ if (count == 0)
+ return 0;
+
+ data = cpustate_get_state();
+ if (copy_to_user(buf, &data, sizeof(unsigned char)))
+ return -EFAULT;
+ return sizeof(unsigned char);
+}
+
+static ssize_t cpustate_write(struct file *file, const char *buf,
+ size_t count, loff_t * ppos)
+{
+ unsigned char data;
+
+ if (count < 0)
+ return -EFAULT;
+
+ if (count == 0)
+ return 0;
+
+ if (copy_from_user((unsigned char *)&data, buf, sizeof(unsigned char)))
+ return -EFAULT;
+
+ cpustate_set_state(data);
+ return sizeof(unsigned char);
+}
+
+static int cpustate_open(struct inode *inode, struct file *file)
+{
+ return cpustate_get_ref((file->f_flags & O_EXCL));
+}
+
+static int cpustate_release(struct inode *inode, struct file *file)
+{
+ return cpustate_free_ref();
+}
+
+/*
+ * Info exported via "/proc/sky_cpustate".
+ */
+static int cpustate_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ char *p = page;
+ int len = 0;
+
+ p += sprintf(p, "CPU State: %04x\n", cpustate_get_state());
+ len = p - page;
+
+ if (len <= off + count)
+ *eof = 1;
+ *start = page + off;
+ len -= off;
+ if (len > count)
+ len = count;
+ if (len < 0)
+ len = 0;
+ return len;
+}
+
+static struct device_driver hdpu_cpustate_driver = {
+ .name = HDPU_CPUSTATE_NAME,
+ .bus = &platform_bus_type,
+ .probe = hdpu_cpustate_probe,
+ .remove = hdpu_cpustate_remove,
+};
+
+/*
+ * The various file operations we support.
+ */
+static struct file_operations cpustate_fops = {
+ owner:THIS_MODULE,
+ open:cpustate_open,
+ release:cpustate_release,
+ read:cpustate_read,
+ write:cpustate_write,
+ fasync:NULL,
+ poll:NULL,
+ ioctl:NULL,
+ llseek:no_llseek,
+
+};
+
+static struct miscdevice cpustate_dev = {
+ MISC_DYNAMIC_MINOR,
+ "sky_cpustate",
+ &cpustate_fops
+};
+
+static int hdpu_cpustate_probe(struct device *ddev)
+{
+ struct platform_device *pdev = to_platform_device(ddev);
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ cpustate.set_addr = (unsigned long *)res->start;
+ cpustate.clr_addr = (unsigned long *)res->end - 1;
+
+ misc_register(&cpustate_dev);
+ create_proc_read_entry("sky_cpustate", 0, 0, cpustate_read_proc, NULL);
+
+ printk(KERN_INFO "Sky CPU State Driver v" SKY_CPUSTATE_VERSION "\n");
+ return 0;
+}
+static int hdpu_cpustate_remove(struct device *ddev)
+{
+
+ cpustate.set_addr = 0;
+ cpustate.clr_addr = 0;
+
+ remove_proc_entry("sky_cpustate", NULL);
+ misc_deregister(&cpustate_dev);
+ return 0;
+
+}
+
+static int __init cpustate_init(void)
+{
+ int rc;
+ rc = driver_register(&hdpu_cpustate_driver);
+ return rc;
+}
+
+static void __exit cpustate_exit(void)
+{
+ driver_unregister(&hdpu_cpustate_driver);
+}
+
+module_init(cpustate_init);
+module_exit(cpustate_exit);
+
+MODULE_AUTHOR("Brian Waite");
+MODULE_LICENSE("GPL");
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper
--exclude=ChangeSet linux-2.5/drivers/misc/hdpuftrs/hdpu_nexus.c
linux-2.5-hdpu/drivers/misc/hdpuftrs/hdpu_nexus.c
--- linux-2.5/drivers/misc/hdpuftrs/hdpu_nexus.c 1969-12-31 19:00:00 -05:00
+++ linux-2.5-hdpu/drivers/misc/hdpuftrs/hdpu_nexus.c 2005-03-16 14:02:09
-05:00
@@ -0,0 +1,111 @@
+/*
+ * Sky Nexus Register Driver
+ *
+ * Copyright (C) 2002 Brian Waite
+ *
+ * This driver allows reading the Nexus register
+ * It exports the /proc/sky_chassis_id and also
+ * /proc/sky_slot_id pseudo-file for status information.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/proc_fs.h>
+#include <linux/hdpu_features.h>
+#include <linux/pci.h>
+
+#include <linux/device.h>
+
+static int hdpu_nexus_probe(struct device *ddev);
+static int hdpu_nexus_remove(struct device *ddev);
+
+static struct proc_dir_entry *hdpu_slot_id;
+static struct proc_dir_entry *hdpu_chassis_id;
+static int slot_id = -1;
+static int chassis_id = -1;
+
+static struct device_driver hdpu_nexus_driver = {
+ .name = HDPU_NEXUS_NAME,
+ .bus = &platform_bus_type,
+ .probe = hdpu_nexus_probe,
+ .remove = hdpu_nexus_remove,
+};
+
+int hdpu_slot_id_read(char *buffer, char **buffer_location, off_t offset,
+ int buffer_length, int *zero, void *ptr)
+{
+
+ if (offset > 0)
+ return 0;
+ return sprintf(buffer, "%d\n", slot_id);
+}
+
+int hdpu_chassis_id_read(char *buffer, char **buffer_location, off_t offset,
+ int buffer_length, int *zero, void *ptr)
+{
+
+ if (offset > 0)
+ return 0;
+ return sprintf(buffer, "%d\n", chassis_id);
+}
+
+static int hdpu_nexus_probe(struct device *ddev)
+{
+ struct platform_device *pdev = to_platform_device(ddev);
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ int *nexus_id_addr;
+ nexus_id_addr =
+ ioremap(res->start, (unsigned long)(res->end - res->start));
+ if (nexus_id_addr) {
+ slot_id = (*nexus_id_addr >> 8) & 0x1f;
+ chassis_id = *nexus_id_addr & 0xff;
+ iounmap(nexus_id_addr);
+ } else
+ printk("Could not map slot id\n");
+ hdpu_slot_id = create_proc_entry("sky_slot_id", 0666, &proc_root);
+ hdpu_slot_id->read_proc = hdpu_slot_id_read;
+ hdpu_slot_id->nlink = 1;
+
+ hdpu_chassis_id = create_proc_entry("sky_chassis_id", 0666, &proc_root);
+ hdpu_chassis_id->read_proc = hdpu_chassis_id_read;
+ hdpu_chassis_id->nlink = 1;
+ return 0;
+}
+
+static int hdpu_nexus_remove(struct device *ddev)
+{
+ slot_id = -1;
+ chassis_id = -1;
+ remove_proc_entry("sky_slot_id", &proc_root);
+ remove_proc_entry("sky_chassis_id", &proc_root);
+ hdpu_slot_id = 0;
+ hdpu_chassis_id = 0;
+ return 0;
+}
+
+static int __init nexus_init(void)
+{
+ int rc;
+ rc = driver_register(&hdpu_nexus_driver);
+ return rc;
+}
+
+static void __exit nexus_exit(void)
+{
+ driver_unregister(&hdpu_nexus_driver);
+}
+
+module_init(nexus_init);
+module_exit(nexus_exit);
+
+MODULE_AUTHOR("Brian Waite");
+MODULE_LICENSE("GPL");
^ permalink raw reply
* Re: looking for a model for building CRAMFS(?)-based system
From: Robert P. J. Day @ 2005-03-17 15:14 UTC (permalink / raw)
To: Patrick Huesmann; +Cc: linuxppc-embedded
In-Reply-To: <93579fec05031706597355371c@mail.gmail.com>
On Thu, 17 Mar 2005, Patrick Huesmann wrote:
> I'm using separate MTD partitions for bootloader, device parameters,
> zImage, initrd and persistent storage.
>
> When updating the initrd, the only thing necessary is a
> eraseall /dev/mtdX
> cat initrd.gz > /dev/mtdX
now this is the sticky part. imagine this system out in the field,
where you need to make an update to something in the initrd in the
root filesystem.
one technique would be to, of couse, download an entirely new
initrd.gz and reflash (hoping no one pulls the plug as you're doing
it), as you describe above.
what about sacrificing space and having an uncompressed root
filesystem in flash? and, if that's possible, would one mount it
read-only from flash (speed?), or just copy it into RAM and mount that
every time?
if all this is covered somewhere, a URL would be fine, thanks.
rday
^ permalink raw reply
* Re: looking for a model for building CRAMFS(?)-based system
From: Patrick Huesmann @ 2005-03-17 14:59 UTC (permalink / raw)
To: Robert P. J. Day; +Cc: linuxppc-embedded
In-Reply-To: <Pine.LNX.4.61.0503161125560.5095@localhost.localdomain>
Hi,
On Wed, 16 Mar 2005 11:33:39 -0500 (EST), Robert P. J. Day
<rpjday@mindspring.com> wrote:
> currently, the system i've built for our 850 board incorporates
>
> - boot loader (sadly, not u-boot, but i'm working on it)
> - standard zImage.initrd.bin kernel+initrd image
> ... mountable JFFS2 filesystem with persistent stuff ...
>
> obviously, with this layout, it's kind of a nuisance to update
> anything individually in the initrd portion of the system, so i'd like
> to at least experiment with a layout that has separate
>
> - boot loader (ideally, u-boot)
> - kernel image
> - updateable (normally mounted read-only?) root filesystem
> ... rest of stuff the same ...
I'm using separate MTD partitions for bootloader, device parameters,
zImage, initrd and persistent storage.
When updating the initrd, the only thing necessary is a
eraseall /dev/mtdX
cat initrd.gz > /dev/mtdX
When booting the kernel, you need something like this in the commandline:
root=/dev/mtdblockX prompt_ramdisk=0 load_ramdisk=1 ramdisk_size=8192
This is bootloader independent, of course.
HTH,
Patrick
^ permalink raw reply
* Re: looking for a model for building CRAMFS(?)-based system
From: Pantelis Antoniou @ 2005-03-17 14:12 UTC (permalink / raw)
To: Robert P. J. Day; +Cc: Embedded PPC Linux list
In-Reply-To: <Pine.LNX.4.61.0503161125560.5095@localhost.localdomain>
Robert P. J. Day wrote:
> i'm hoping someone has an example of the following that they're
> willing to share.
>
> currently, the system i've built for our 850 board incorporates
>
> - boot loader (sadly, not u-boot, but i'm working on it)
> - standard zImage.initrd.bin kernel+initrd image
> ... mountable JFFS2 filesystem with persistent stuff ...
>
> obviously, with this layout, it's kind of a nuisance to update
> anything individually in the initrd portion of the system, so i'd like
> to at least experiment with a layout that has separate
>
> - boot loader (ideally, u-boot)
> - kernel image
> - updateable (normally mounted read-only?) root filesystem
> ... rest of stuff the same ...
>
> i'm going to start over at DENX with their docs since that seems to
> be the canonical place to get the scoop on this but, in the meantime,
> if anyone has built something like this and is willing to share, say,
> their makefile so i can see how it goes together, i'd be thrilled.
>
> if your example happens to *require* u-boot, well, perhaps so much
> the better since that will give me the incentive to switch. :-)
We use a scheme on NAND with redundant cramfs rootfs partitions
that also contain the proper kernel image(s).
It is u-boot specific since it depends on u-boot loading the
cramfs kernel image.
For persistent storage we use a small JFFS2 partition.
>
> thanks.
>
> rday
Regards
Pantelis
^ permalink raw reply
* Re: [PATCH] Make sleep/wakeup work with USB on powerbooks
From: Colin Leroy @ 2005-03-17 14:20 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Paul Mackerras, Linux-USB
In-Reply-To: <1111044955.7192.210.camel@gaston>
On 17 Mar 2005 at 18h03, Benjamin Herrenschmidt wrote:
Hi,
> > Would it be the "proper" patch I was looking for in the thread named
> > "[PATCH] Re-power USB ports on wakeup" ?
> >
> > Or does it fix different issues ? Mine fixed, with a hack I think,
> > the fact that USB ports kept being powered down after one wakeup
> > out of two. I never got any machine check, however.
>
> Test please, your patch shouldn't be necessary.
Just did so, it's not enough. My patch seems necessary so that usb
ports are powered at each wakeup (the second one, that doesn't touch
anything at sleep and sets power unconditionnaly at wakeup, works fine).
With Paul's patch, (dis)connecting USB devices during sleep isn't a
problem anymore.
--
Colin
^ permalink raw reply
* Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board
From: S. van Beek @ 2005-03-17 13:24 UTC (permalink / raw)
To: Linuxppc-embedded
In-Reply-To: <4239836A.5010200@ru.mvista.com>
Hi,
Yes this is the case too on this board, they are multiplexed. But we don't
have a SystemAce adapter and the SystemAce IP is also not included in our
design.
----- Original Message -----
From: "Andrei Konovalov" <akonovalov@ru.mvista.com>
To: "S. van Beek" <nlv11891@prle>
Cc: <Linuxppc-embedded@ozlabs.org>
Sent: Thursday 17 March 2005 14:17
Subject: Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672
board
> > We added the IP to the hardware and loaded the new bitstream in the
FPGA.
>
> - isn't this the root of the problem? Any hardware conflict?
>
> Not sure about the ff672 board and the Comm2 module, but in case of fg456
board and P160 COMM module
> rev 2 SystemACE and the parallel flash sit on the same data bus. And in
the design generated by default
> the chip selects are always enabled for both. Maybe you have something
similar.
> Just a pure guess.
>
> Thanks,
> Andrei
>
> S. van Beek wrote:
> > Hello there,
> >
> > This is our first post on this list, hi all! We're two Dutch students
working with a Virtex-II pro ff672 board from Memec
> > with the Communications 2 module. We've compiled a simple kernel wich
comes with MontaVista Linux 3.1 (2.4.20) with ethernet
> > and a serial port. It mounts its root filesystem over NFS and everything
seems to work nicely. The next step we wanted to
> > make was adding support for the Flash on the com board. We added the IP
to the hardware and loaded the new bitstream in the
> > FPGA. Next thing, we enabled support for MTD devices in the kernel.
After that, the kernel did not seem to boot anymore. It
> > stopped at the message 'Now booting the kernel'. So we read some
documentation about debugging. We recompiled this kernel
> > with the -g -ggdb options and removed the -O (optimalization) flag. Then
we did not even see the ppc boot loader messages
> > anymore when trying to boot. So we tried to compile the first kernel
(with only serial and ethernet support) -wich worked
> > fine before- with debugging and it gave us the same result.. no output
at all. Can anyone give us some hints on what we can
> > try more to find out what is going wrong?
> >
> > Regards, Sander van Beek Daniel van Os
> >
> >
> > ------------------------------------------------------------------------
> >
> > _______________________________________________ Linuxppc-embedded
mailing list Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
>
>
^ permalink raw reply
* Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board
From: Andrei Konovalov @ 2005-03-17 13:17 UTC (permalink / raw)
To: S. van Beek; +Cc: Linuxppc-embedded
In-Reply-To: <002001c52aef$d29dbb70$9c9c9182@ddns.htc.nl.philips.com>
> We added the IP to the hardware and loaded the new bitstream in the FPGA.
- isn't this the root of the problem? Any hardware conflict?
Not sure about the ff672 board and the Comm2 module, but in case of fg456 board and P160 COMM module
rev 2 SystemACE and the parallel flash sit on the same data bus. And in the design generated by default
the chip selects are always enabled for both. Maybe you have something similar.
Just a pure guess.
Thanks,
Andrei
S. van Beek wrote:
> Hello there,
>
> This is our first post on this list, hi all! We're two Dutch students working with a Virtex-II pro ff672 board from Memec
> with the Communications 2 module. We've compiled a simple kernel wich comes with MontaVista Linux 3.1 (2.4.20) with ethernet
> and a serial port. It mounts its root filesystem over NFS and everything seems to work nicely. The next step we wanted to
> make was adding support for the Flash on the com board. We added the IP to the hardware and loaded the new bitstream in the
> FPGA. Next thing, we enabled support for MTD devices in the kernel. After that, the kernel did not seem to boot anymore. It
> stopped at the message 'Now booting the kernel'. So we read some documentation about debugging. We recompiled this kernel
> with the -g -ggdb options and removed the -O (optimalization) flag. Then we did not even see the ppc boot loader messages
> anymore when trying to boot. So we tried to compile the first kernel (with only serial and ethernet support) -wich worked
> fine before- with debugging and it gave us the same result.. no output at all. Can anyone give us some hints on what we can
> try more to find out what is going wrong?
>
> Regards, Sander van Beek Daniel van Os
>
>
> ------------------------------------------------------------------------
>
> _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board
From: Jaap-Jan Boor @ 2005-03-17 12:57 UTC (permalink / raw)
To: S. van Beek; +Cc: Linuxppc-embedded
In-Reply-To: <002001c52aef$d29dbb70$9c9c9182@ddns.htc.nl.philips.com>
is there something printed before 'Now booting the kernel'?
If so, do the memory ranges not overlap or something?
Jaap-Jan
On 17-mrt-05, at 13:49, S. van Beek wrote:
> Hello there,
> =A0
> This is our first post on this list, hi all!
> We're two Dutch students working with a Virtex-II pro ff672 board from=20=
> Memec with the Communications 2 module. We've compiled a simple kernel=20=
> wich comes with MontaVista Linux=A03.1 (2.4.20) with ethernet and a=20
> serial port. It mounts its root filesystem over NFS and everything=20
> seems to work nicely. The next step we wanted to make was=20
> adding=A0support for the Flash=A0on the com board. We added the IP to =
the=20
> hardware and loaded the new bitstream in the FPGA. Next thing, we=20
> enabled support for MTD devices in the kernel. After that, the kernel=20=
> did not seem to boot anymore. It stopped at the message 'Now booting=20=
> the kernel'. So we read some documentation about debugging. We=20
> recompiled this kernel with the -g -ggdb options and removed the -O=20
> (optimalization) flag. Then we did not even see the ppc boot loader=20
> messages anymore when trying to boot. So we tried to compile the first=20=
> kernel (with only serial and ethernet support) -wich worked fine=20
> before-=A0with debugging and it gave us the same result.. no output at=20=
> all.
> Can anyone give us some hints on what we can try more to find out=20
> what is going wrong?
> =A0
> Regards,
> Sander van Beek
> Daniel van Os
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
J.G.J. Boor Anton Philipsweg 1
Software Engineer 1223 KZ Hilversum
AimSys bv tel. +31 35 689 1941
Postbus 2194, 1200 CD Hilversum mailto:jjboor@aimsys.nl
^ permalink raw reply
* RE: FW: LED driver
From: Hans Schillstrom @ 2005-03-17 12:53 UTC (permalink / raw)
To: srinivas.surabhi; +Cc: linuxppc-embedded
In-Reply-To: <EF9B29C78F41FA488927FCBC7750AF0E011DA97B@hyd-mdp-msg.wipro.com>
[-- Attachment #1: Type: text/plain, Size: 3180 bytes --]
Hi,
Thats right, but the original is for 2.4.2x.
I'll attach the original status_led.c from Denx for you
/Hans
Wolfgang: Sorry about the missing copyright
On Thu, 2005-03-17 at 13:47, srinivas.surabhi@wipro.com wrote:
> Thanks a lot for your help. But in my sources I could not find
> immap_cpm2.h file. There is immap_8260.h file, I don't know it is
> similar to that of immap_cpum2.h.
>
> Can you send the immap_cpum2.h file please?
>
> I am working on kernel 2.4.20
>
> -Thanks once again..
> SS
>
> -----Original Message-----
> From: Hans Schillstrom [mailto:hans.schillstrom@pwav.com]
> Sent: Thursday, March 17, 2005 3:17 PM
> To: Srinivas Surabhi (WT01 - TELECOM SOLUTIONS)
> Cc: linuxppc-embedded@ozlabs.org
> Subject: Re: FW: LED driver
>
> Hi,
> I have made a driver for our mpc8270 board
> It is based upon Denx led_driver and made for 2.6 kernel
> (See atached file)
>
> To control the leds you have to perfom some ioctl's
> first create your devices
> mknod led0 c 151 0 ...
>
> Example howto use it:
>
> void led_off( int file )
> {
> if (ioctl(file,STATUSLED_SET,0) < 0)
> perror("led off: ");
> }
> void led_blink( int file )
> {
> if (ioctl(file,STATUSLED_SET,1) < 0)
> perror("led blink: ");
> }
> void led_on( int file )
> {
> if (ioctl(file,STATUSLED_SET,2) < 0)
> perror("led on: ");
> }
> void led_per( int file, int period )
> {
> if (ioctl(file,STATUSLED_PERIOD,period) < 0)
> perror("led on: ");
> }
>
> ...
>
> int led0 = open("/dev/led0",O_RDWR)
> ...
> led_blink(led0); /* turn on green LED */
> ..
> /Hans
>
>
> On Thu, 2005-03-17 at 06:15, srinivas.surabhi@wipro.com wrote:
> >
> > -----Original Message-----
> > From: Srinivas Surabhi (WT01 - TELECOM SOLUTIONS)
> > Sent: Thursday, March 17, 2005 7:53 AM
> > To: linuxppc-embedded@ozlabs.org
> > Subject: LED driver
> >
> > Hi,
> >
> > I am working on the MPC8270 board having connected GPIO 3 lines
> > connected to 3 LEDs. So can any one help me in finding out the best
> > solution of controlling the LEDs from MVlinux (kernel and user space)
> or
> > any pointers who has done it before.
> >
> > Thanks & Rgds
> > SS
> >
> >
> >
> >
> > Confidentiality Notice
> >
> > The information contained in this electronic message and any
> attachments to this message are intended
> > for the exclusive use of the addressee(s) and may contain confidential
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[-- Attachment #2: status_led.c --]
[-- Type: text/x-c, Size: 15945 bytes --]
/***********************************************************************
*
* (C) Copyright 1999, 2000, 2001
* DENX Software Engineering
* Wolfgang Denk, wd@denx.de
* All rights reserved.
*
***********************************************************************/
/*
* Standard in kernel modules
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/devfs_fs_kernel.h>
#include <linux/version.h>
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/spinlock.h>
#include <asm/types.h>
#include <asm/uaccess.h>
#include <asm/8xx_immap.h>
#include <asm/mpc8xx.h>
#include <asm/status_led.h>
#undef DEBUG
#ifdef DEBUG
# define debugk(fmt,args...) printk(fmt ,##args)
#else
# define debugk(fmt,args...)
#endif
/*
* Deal with CONFIG_MODVERSIONS
*/
#if CONFIG_MODVERSIONS==1
/* # define MODVERSIONS */
# include <linux/modversions.h>
#endif
/*
* For character devices
*/
#include <linux/fs.h> /* character device definitions */
#include <linux/wrapper.h> /* wrapper for compatibility with future versions */
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
static DECLARE_WAIT_QUEUE_HEAD(statusled_wait);
static char last_io_state;
static volatile char changed_io_state;
static spinlock_t statusled_lock;
static struct timer_list io_timer;
static void status_io_poll (unsigned long period);
static int status_io_test (void);
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
#define LED_MAJOR 151 /* Reserverd for "Front panel LEDs" */
#define DRIVER_VERSION "$Revision: 1.0 $"
static void statusled_blink (unsigned long minor);
/*
* Device Declarations
*/
typedef struct {
unsigned long mask;
int state;
int period;
int flags;
struct timer_list timer;
} led_dev_t;
#define SL_FLAG_OPEN 1
led_dev_t led_dev[] = {
{ STATUS_LED_BIT,
STATUS_LED_STATE,
STATUS_LED_PERIOD,
0,
{ function: statusled_blink, data: 0UL /* minor 0 */ },
},
#if defined(STATUS_LED_BIT1)
{ STATUS_LED_BIT1,
STATUS_LED_STATE1,
STATUS_LED_PERIOD1,
0,
{ function: statusled_blink, data: 1UL /* minor 1 */ },
},
#endif /* STATUS_LED_BIT1 */
#if defined(STATUS_LED_BIT2)
{ STATUS_LED_BIT2,
STATUS_LED_STATE2,
STATUS_LED_PERIOD2,
0,
{ function: statusled_blink, data: 2UL /* minor 2 */ },
},
#endif /* STATUS_LED_BIT2 */
};
#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t))
/*
* On the IVM* we handle 2 additional devices with this driver:
* MAX_LED_DEV+0 => "Interlock Switch" and "Device Reset Monitor":
* Both are input pins, which are polled periodically,
* and the user can wait with select() for a status change.
* MAX_LED_DEV+1 => "Device Reset Enable", an output device we can set or reset.
*/
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
# define MAX_IO_DEV 2
static int io_dev_flags[MAX_IO_DEV] = { 0, }; /* additional I/O devices */
#else
# define MAX_IO_DEV 0
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
static volatile immap_t *immr = NULL;
/*
* The name for our device, as it will appear in /proc/devices
*/
#define DEVICE_NAME "status_led"
/*
* Prototypes
*/
static int statusled_init (void) __init;
static int statusled_open(struct inode *, struct file *);
static int statusled_release(struct inode *, struct file *);
# if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
static ssize_t statusled_read(struct file *, char *, size_t, loff_t *);
static unsigned int statusled_poll (struct file *, poll_table *);
# endif /* CONFIG_IVMS8, CONFIG_IVML24 */
int init_module(void);
void cleanup_module(void);
static ssize_t statusled_ioctl(struct inode *, struct file *,
unsigned int, unsigned long);
static struct file_operations statusled_fops = {
owner: THIS_MODULE,
open: statusled_open,
release: statusled_release,
ioctl: statusled_ioctl,
# if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
read: statusled_read,
poll: statusled_poll,
# endif /* CONFIG_IVMS8, CONFIG_IVML24 */
};
static int Major;
/*
* Initialize the driver - Register the character device
*/
static int __init statusled_init (void)
{
int i;
if (!immr) { /* init CPM ptr */
unsigned long val;
asm( "mfspr %0,638": "=r"(val) : );
val &= 0xFFFF0000;
immr = (volatile immap_t *)val;
}
/*
* Register the character device
*/
if ((i = register_chrdev(LED_MAJOR, DEVICE_NAME, &statusled_fops)) < 0) {
immr = NULL;
printk("Unable to get major %d for status LED driver: rc=%d\n",
LED_MAJOR, i);
return (i);
}
Major = LED_MAJOR;
printk (KERN_INFO
"Status LED driver " DRIVER_VERSION " initialized\n");
for (i=0; i<MAX_LED_DEV; ++i) {
immr->STATUS_LED_PAR &= ~(led_dev[i].mask);
#ifdef STATUS_LED_ODR
immr->STATUS_LED_ODR &= ~(led_dev[i].mask);
#endif
if (led_dev[i].state == STATUS_LED_ON) {
#if (STATUS_LED_ACTIVE == 0) /* start with LED on */
immr->STATUS_LED_DAT &= ~(led_dev[i].mask);
#else
immr->STATUS_LED_DAT |= led_dev[i].mask ;
#endif
} else {
#if (STATUS_LED_ACTIVE == 0) /* start with LED off */
immr->STATUS_LED_DAT |= led_dev[i].mask ;
#else
immr->STATUS_LED_DAT &= ~(led_dev[i].mask);
#endif
}
immr->STATUS_LED_DIR |= led_dev[i].mask;
statusled_blink(i);
}
#if defined(CONFIG_IVML24)
/*
* Configure interlock switch port for input
*/
immr->im_cpm.cp_pbpar &= ~(STATUS_ILOCK_SWITCH);
immr->im_cpm.cp_pbodr &= ~(STATUS_ILOCK_SWITCH);
immr->im_cpm.cp_pbdir &= ~(STATUS_ILOCK_SWITCH);
#endif /* CONFIG_IVML24 */
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
/*
* Configure device reset monitor port for input
*/
immr->im_ioport.iop_pcpar &= ~(STATUS_RESET_MON);
immr->im_ioport.iop_pcso &= ~(STATUS_RESET_MON);
immr->im_ioport.iop_pcdir &= ~(STATUS_RESET_MON);
/*
* Configure device reset enable port for output
* Initialize with low (0) level
*/
immr->im_ioport.iop_pcpar &= ~(STATUS_RESET_ENA);
immr->im_ioport.iop_pcso &= ~(STATUS_RESET_ENA);
immr->im_ioport.iop_pcdat &= ~(STATUS_RESET_ENA); /* set 0 */
immr->im_ioport.iop_pcdir |= STATUS_RESET_ENA ; /* output */
/*
* We use the same function (originally for the ILOCK device only)
* to poll both the ILOCK and RESET_MON ports
*/
io_timer.function = status_io_poll;
io_timer.data = STATUS_ILOCK_PERIOD;
last_io_state = (char)status_io_test();
changed_io_state = 0;
init_timer(&io_timer);
io_timer.expires = jiffies + io_timer.data;
add_timer(&io_timer);
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
return (0);
}
/*
* called whenever a process attempts to open the device
*/
static int statusled_open (struct inode *inode, struct file *file)
{
int minor = MINOR(inode->i_rdev);
debugk ("statusled_open(%p,%p): minor %d\n", inode, file, minor);
/*
* Allow for MAX_LED_DEV status LEDs
* On IVMS8 and IVML24: allow for additional I/O devices
*/
if (minor >= MAX_LED_DEV + MAX_IO_DEV)
return (-ENXIO);
if (!immr)
return (-ENODEV);
/*
* exclusive open only
*/
if (minor < MAX_LED_DEV) {
if (led_dev[minor].flags & SL_FLAG_OPEN)
return -EBUSY;
led_dev[minor].flags |= SL_FLAG_OPEN;
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
} else {
int m = minor - MAX_LED_DEV;
if (io_dev_flags[m] & SL_FLAG_OPEN)
return -EBUSY;
io_dev_flags[m] |= SL_FLAG_OPEN;
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
}
/*
* Make sure that the module isn't removed while
* the file is open by incrementing the usage count
*/
MOD_INC_USE_COUNT;
debugk ("LED_OPEN: minor %d dir=0x%x par=0x%x odr=0x%x dat=0x%x\n",
minor,
immr->STATUS_LED_DIR, immr->STATUS_LED_PAR,
immr->STATUS_LED_ODR, immr->STATUS_LED_DAT);
return 0;
}
/*
* Called when a process closes the device.
* Doesn't have a return value in version 2.0.x because it can't fail,
* but in version 2.2.x it is allowed to fail
*/
static int statusled_release (struct inode *inode, struct file *file)
{
int minor = MINOR(inode->i_rdev);
debugk ("statusled_release(%p,%p)\n", inode, file);
if (!immr)
return (-ENODEV);
/* We're now ready for our next caller */
if (minor < MAX_LED_DEV) {
led_dev[minor].flags &= ~SL_FLAG_OPEN;
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
} else {
int m = minor - MAX_LED_DEV;
io_dev_flags[m] &= ~SL_FLAG_OPEN;
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
}
MOD_DEC_USE_COUNT;
debugk ("LED_CLOSE: dir=0x%x par=0x%x odr=0x%x dat=0x%x\n",
immr->STATUS_LED_DIR, immr->STATUS_LED_PAR,
immr->STATUS_LED_ODR, immr->STATUS_LED_DAT);
return 0;
}
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
/*
* read entry point:
* Only supported for interlock switch (return ENXIO for LED devices).
* For the ilock switch, block until the next status change happens;
* then return exactly one byte containing the current state
* (0x00 switch open, 0x01 switch closed).
*/
static ssize_t statusled_read (struct file *file,
char *buf, size_t count, loff_t *ppos)
{
DECLARE_WAITQUEUE(wait, current);
int minor = MINOR(file->f_dentry->d_inode->i_rdev);
int rc = 0;
char c;
if (minor != MAX_LED_DEV)
return (-ENXIO);
add_wait_queue(&statusled_wait, &wait);
current->state = TASK_INTERRUPTIBLE;
for (;;) {
if (changed_io_state)
break;
if (file->f_flags & O_NONBLOCK) {
rc = -EAGAIN;
goto OUT;
}
if (signal_pending(current)) {
rc = -ERESTARTSYS;
goto OUT;
}
schedule ();
}
spin_lock (&statusled_lock);
c = (char)status_io_test ();
changed_io_state = 0;
spin_unlock (&statusled_lock);
/* Copy out */
if ((rc = verify_area(VERIFY_WRITE, buf, 1)) != 0) {
goto OUT;
}
rc = 1; copy_to_user((void *)buf, (void*)(&c), rc);
OUT:
current->state = TASK_RUNNING;
remove_wait_queue(&statusled_wait, &wait);
return (rc);
}
static unsigned int statusled_poll (struct file *file, poll_table *wait)
{
poll_wait(file, &statusled_wait, wait);
if (changed_io_state)
return POLLIN | POLLRDNORM;
return 0;
}
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
/*
* ioctl entry point:
*/
static ssize_t statusled_ioctl (
struct inode *inode,
struct file *file,
unsigned int cmd,
unsigned long arg)
{
int minor = MINOR(inode->i_rdev);
int n;
if (!immr)
return (-ENODEV);
debugk ("IOCTL: minor=%d, cmd=%s, arg=%ld\n",
minor,
(cmd == STATUSLED_GET ) ? "STATUSLED_GET" :
(cmd == STATUSLED_SET ) ? "STATUSLED_SET" :
(cmd == STATUSLED_PERIOD) ? "STATUSLED_PERIOD" :
"<unknown>",
arg);
if (minor < MAX_LED_DEV) {
switch (cmd) {
case STATUSLED_GET:
switch (led_dev[minor].state) {
case STATUS_LED_OFF: n = 0;
break;
case STATUS_LED_ON: n = -1;
break;
default: n = led_dev[minor].period;
break;
}
return (copy_to_user((int *)arg, &n, sizeof (int)));
case STATUSLED_SET:
switch (arg) {
case STATUS_LED_OFF:
debugk ("IOCTL: was %d, set %ld=OFF\n",
led_dev[minor].state, arg);
if (led_dev[minor].state == STATUS_LED_BLINKING)
del_timer(&led_dev[minor].timer);
led_dev[minor].state = arg;
#if (STATUS_LED_ACTIVE == 0)
immr->STATUS_LED_DAT |= led_dev[minor].mask ;
#else
immr->STATUS_LED_DAT &= ~(led_dev[minor].mask);
#endif
return (0);
case STATUS_LED_ON:
debugk ("IOCTL: was %d, set %ld=ON\n",
led_dev[minor].state, arg);
if (led_dev[minor].state == STATUS_LED_BLINKING)
del_timer(&led_dev[minor].timer);
led_dev[minor].state = arg;
#if (STATUS_LED_ACTIVE == 0)
immr->STATUS_LED_DAT &= ~(led_dev[minor].mask);
#else
immr->STATUS_LED_DAT |= led_dev[minor].mask ;
#endif
return (0);
case STATUS_LED_BLINKING:
debugk ("IOCTL: was %d, set %ld=BLINKING\n",
led_dev[minor].state, arg);
if (led_dev[minor].state == STATUS_LED_BLINKING)
return (0);
led_dev[minor].state = arg; /* must come first! */
/* start blinking */
statusled_blink (minor);
return (0);
}
return (-EINVAL);
case STATUSLED_PERIOD:
led_dev[minor].period = arg;
debugk ("IOCTL: set PERIOD=%d\n", arg);
return (0);
}
}
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
else {
int m = minor - MAX_LED_DEV;
switch (m) {
case 0: /* Interlock switch and device reset monitor */
if (cmd == STATUS_SWITCH_GET) {
n = status_io_test ();
return (copy_to_user((int *)arg, &n, sizeof (int)));
}
break;
case 1: /* Device reset enable output */
if (cmd == STATUS_RESET_GET) {
if (immr->im_ioport.iop_pcdat & STATUS_RESET_ENA) {
n = 1;
} else {
n = 0;
}
return (copy_to_user((int *)arg, &n, sizeof (int)));
}
if (cmd == STATUS_RESET_SET) {
if (arg == 0) {
immr->im_ioport.iop_pcdat &= ~STATUS_RESET_ENA;
} else {
immr->im_ioport.iop_pcdat |= STATUS_RESET_ENA;
}
return (0);
}
break;
default:
break;
}
}
#endif
return (-EINVAL);
}
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
/*
* Test status of interlock switch
*/
static int status_io_test (void)
{
int n = 0;
#if defined(CONFIG_IVMS8)
spin_lock (&statusled_lock);
if ((immr->im_siu_conf.sc_sipend & STATUS_ILOCK_SWITCH) != 0)
n |= STATUS_ILOCK_BIT;
immr->im_siu_conf.sc_sipend = STATUS_ILOCK_SWITCH;
spin_unlock (&statusled_lock);
#elif defined(CONFIG_IVML24)
if ((immr->im_cpm.cp_pbdat & STATUS_ILOCK_SWITCH) != 0)
n |= STATUS_ILOCK_BIT;
#endif
if ((immr->im_ioport.iop_pcdat & STATUS_RESET_MON) != 0)
n |= STATUS_RESET_MON_BIT;
return (n);
}
static void status_io_poll (unsigned long period)
{
char c;
spin_lock (&statusled_lock);
c = (char)status_io_test ();
if (c != last_io_state) {
last_io_state = c;
changed_io_state = 1;
}
spin_unlock (&statusled_lock);
if (changed_io_state)
wake_up_interruptible(&statusled_wait);
init_timer(&io_timer);
io_timer.expires = jiffies + io_timer.data;
add_timer(&io_timer);
}
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
/*
* Timer controlled blink entry point.
*
* We delete the timer when the status is changed to non-blinking
* or when the module is unloaded.
*/
static void statusled_blink (unsigned long minor)
{
unsigned long flags;
if (!immr)
return;
if (led_dev[minor].state != STATUS_LED_BLINKING) {
/* don't change any more */
return;
}
immr->STATUS_LED_DAT ^= led_dev[minor].mask;
save_flags(flags);
cli();
init_timer(&led_dev[minor].timer);
led_dev[minor].timer.expires = jiffies + led_dev[minor].period;
add_timer(&led_dev[minor].timer);
restore_flags(flags);
}
/******************************
**** Module Declarations *****
**************************** */
module_init (statusled_init);
#ifdef MODULE
/*
* Cleanup - unregister the driver
*/
void statusled_cleanup (void)
{
int minor, ret;
/*
* Cleanup timer
*/
for (minor=0; minor<MAX_LED_DEV; ++minor) {
if (led_dev[minor].state == STATUS_LED_BLINKING)
del_timer(&led_dev[minor].timer);
#if (STATUS_LED_ACTIVE == 0)
immr->STATUS_LED_DAT |= led_dev[minor].mask ;
#else
immr->STATUS_LED_DAT &= ~(led_dev[minor].mask);
#endif
led_dev[minor].state = STATUS_LED_OFF;
}
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
del_timer(&io_timer);
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
/*
* Unregister the device
*/
ret = unregister_chrdev (Major, DEVICE_NAME);
/*
* If there's an error, report it
*/
if (ret < 0) {
printk ("unregister_chrdev: error %d\n", ret);
}
}
module_exit (statusled_cleanup);
#endif /* MODULE */
[-- Attachment #3: status_led.h --]
[-- Type: text/x-h, Size: 9598 bytes --]
/*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This code implements one or more status LEDs which can be switched
* on or off or set to blink at a specified frequency.
*
* For instance you can use a status LED to signal the operational
* status of a target which usually boots over the network; while
* running in PPCBoot, the status LED is blinking. As soon as a valid
* BOOTP reply message has been received, the LED is turned off. The
* Linux kernel, once it is running, will start blinking the LED
* again, with another frequency.
*
* For IVM* systems, this driver is also used to read and write some
* special I/O ports:
*
* - The "Interlock Switch" and the "Device Reset Monitor" are input
* ports (one bit each), which are used to signal status changes to
* the applications. It is a requirement to be able to wait for
* such a status change using select(). Unfortunately, the hardware
* is different for IVMS8 and IVML24, and not all input pins used
* can generate interrupts. So we have to poll the ports
* periodically - sic!
* - "Device Reset Enable" is an output port (1 bit) which can be set
* and reset from the application. OK, finally we have something
* really simple.
*/
#ifndef _PPC_STATUS_LED_H
#define _PPC_STATUS_LED_H
#include <linux/config.h>
#include <asm/ioctl.h>
/* ioctl's */
#define STATUSLED_GET _IOR('L', 1, unsigned long)
#define STATUSLED_SET _IOW('L', 2, unsigned long)
#define STATUSLED_PERIOD _IOW('L', 3, unsigned long)
#define STATUS_SWITCH_GET _IOR('L', 4, unsigned long)
#define STATUS_RESET_GET _IOR('L', 5, unsigned long)
#define STATUS_RESET_SET _IOW('L', 6, unsigned long)
#define STATUS_LED_OFF 0
#define STATUS_LED_BLINKING 1
#define STATUS_LED_ON 2
#ifdef __KERNEL__
/***** TQM8xxL ********************************************************/
#if (defined(CONFIG_TQM8xxL) && !defined(CONFIG_ETX094))
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (2 * HZ)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** ETX_094 ********************************************************/
#elif defined(CONFIG_ETX094)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (2 * HZ)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** IVMS8 **********************************************************/
#elif defined(CONFIG_IVMS8)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
# define STATUS_LED_PERIOD (1 * HZ)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
# define STATUS_LED_PERIOD1 (1 * HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
/* IDE LED usable for other purposes, too */
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
# define STATUS_LED_PERIOD2 (1 * HZ)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_YELLOW 0
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
# define STATUS_ILOCK_BIT 0x01
# define STATUS_RESET_MON_BIT 0x02
# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */
# define STATUS_ILOCK_PERIOD (HZ / 10) /* about every 100 ms */
# define STATUS_RESET_MON 0x0008 /* Reset Mon. on PC.12 */
/* polled with ILOCK */
# define STATUS_RESET_ENA 0x0004 /* Reset enable PC.13 */
/***** IVML24 *********************************************************/
#elif defined(CONFIG_IVML24)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000010
# define STATUS_LED_PERIOD (1 * HZ)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x00000020
# define STATUS_LED_PERIOD1 (1 * HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
/* IDE LED usable for other purposes, too */
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
# define STATUS_LED_PERIOD2 (1 * HZ)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_YELLOW 0
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
# define STATUS_ILOCK_BIT 0x01
# define STATUS_RESET_MON_BIT 0x02
# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */
# define STATUS_ILOCK_PERIOD (HZ / 10) /* about every 100 ms */
# define STATUS_RESET_MON 0x0008 /* Reset Mon. on PC.12 */
/* polled with ILOCK */
# define STATUS_RESET_ENA 0x0004 /* Reset enable PC.13 */
/***** PCU E and CCM ************************************************/
#elif defined(CONFIG_PCU_E) || defined(CONFIG_CCM)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# undef STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */
# define STATUS_LED_PERIOD (2 * HZ)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x00020000 /* red LED is on PB.14 */
# define STATUS_LED_PERIOD1 (1 * HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
# define STATUS_LED_GREEN STATUS_LED_BOOT
# define STATUS_LED_RED 1
/***** LANTEC *********************************************************/
#elif defined(CONFIG_LANTEC)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x0800
# define STATUS_LED_PERIOD (HZ / 4)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** ICU862 ********************************************************/
#elif defined(CONFIG_ICU862)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */
# define STATUS_LED_PERIOD (2 * HZ)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */
# define STATUS_LED_PERIOD1 (1 * HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** DAB4K ********************************************************/
/* STATUS_LED_XXXs are defined in arch/ppc/platforms/dab4k.h */
#elif defined(CONFIG_DAB4K)
/************************************************************************/
#elif defined(CONFIG_RCB8270)
# define STATUS_LED_PAR im_ioport.iop_pparc
# define STATUS_LED_DIR im_ioport.iop_pdirc
# define STATUS_LED_DAT im_ioport.iop_pdatc
# undef STATUS_LED_ODR
# define STATUS_LED_BIT 0x20000000 /* LED 0 is on PC.2 OPERATE_LED */
# define STATUS_LED_PERIOD (HZ)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x10000000 /* LED 1 is on PC.3 ALARM_LED */
# define STATUS_LED_PERIOD1 (HZ)
# define STATUS_LED_STATE1 STATUS_LED_ON
# define STATUS_LED_BIT2 0x08000000 /* LED 2 is on PC.4 BOOT_LED */
# define STATUS_LED_PERIOD2 (HZ)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 2 /* LED 0 used for boot status */
#define PCMCIA_LED 0
#define STATUS_LED 1
#define FRONT_LED 2
#else
# error Status LED configuration missing
#endif
void status_led_tick (unsigned long timestamp);
void status_led_set (int state);
#endif /* __KERNEL__ */
#endif /* _PPC_STATUS_LED_H */
^ permalink raw reply
* Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board
From: S. van Beek @ 2005-03-17 12:49 UTC (permalink / raw)
To: Linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1212 bytes --]
Hello there,
This is our first post on this list, hi all!
We're two Dutch students working with a Virtex-II pro ff672 board from Memec with the Communications 2 module. We've compiled a simple kernel wich comes with MontaVista Linux 3.1 (2.4.20) with ethernet and a serial port. It mounts its root filesystem over NFS and everything seems to work nicely. The next step we wanted to make was adding support for the Flash on the com board. We added the IP to the hardware and loaded the new bitstream in the FPGA. Next thing, we enabled support for MTD devices in the kernel. After that, the kernel did not seem to boot anymore. It stopped at the message 'Now booting the kernel'. So we read some documentation about debugging. We recompiled this kernel with the -g -ggdb options and removed the -O (optimalization) flag. Then we did not even see the ppc boot loader messages anymore when trying to boot. So we tried to compile the first kernel (with only serial and ethernet support) -wich worked fine before- with debugging and it gave us the same result.. no output at all.
Can anyone give us some hints on what we can try more to find out what is going wrong?
Regards,
Sander van Beek
Daniel van Os
[-- Attachment #2: Type: text/html, Size: 1923 bytes --]
^ permalink raw reply
* RE: FW: LED driver
From: srinivas.surabhi @ 2005-03-17 12:47 UTC (permalink / raw)
To: hans.schillstrom; +Cc: linuxppc-embedded
Thanks a lot for your help. But in my sources I could not find=0D
immap_cpm2.h file. There is immap_8260.h file, I don't know it is
similar to that of immap_cpum2.h.=0D
Can you send the immap_cpum2.h file please?
I am working on kernel 2.4.20=0D
-Thanks once again..
SS
-----Original Message-----
From: Hans Schillstrom [mailto:hans.schillstrom@pwav.com]=0D
Sent: Thursday, March 17, 2005 3:17 PM
To: Srinivas Surabhi (WT01 - TELECOM SOLUTIONS)
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: FW: LED driver
Hi,
I have made a driver for our mpc8270 board=0D
It is based upon Denx led_driver and made for 2.6 kernel
(See atached file)
To control the leds you have to perfom some ioctl's
first create your devices=0D
mknod led0 c 151 0 ...
Example howto use it:
void led_off( int file )
{
if (ioctl(file,STATUSLED_SET,0) < 0)
perror("led off: ");
}
void led_blink( int file )
{
if (ioctl(file,STATUSLED_SET,1) < 0)
perror("led blink: ");
}
void led_on( int file )
{
if (ioctl(file,STATUSLED_SET,2) < 0)
perror("led on: ");
}
void led_per( int file, int period )
{
if (ioctl(file,STATUSLED_PERIOD,period) < 0)
perror("led on: ");
}
...
int led0 =3D open("/dev/led0",O_RDWR)
...
led_blink(led0); /* turn on green LED */
..
/Hans
On Thu, 2005-03-17 at 06:15, srinivas.surabhi@wipro.com wrote:
>=0D
> -----Original Message-----
> From: Srinivas Surabhi (WT01 - TELECOM SOLUTIONS)
> Sent: Thursday, March 17, 2005 7:53 AM
> To: linuxppc-embedded@ozlabs.org
> Subject: LED driver
>=0D
> Hi,
>=0D
> I am working on the MPC8270 board having connected GPIO 3 lines
> connected to 3 LEDs. So can any one help me in finding out the best
> solution of controlling the LEDs from MVlinux (kernel and user space)
or
> any pointers who has done it before.
>=0D
> Thanks & Rgds
> SS
>=0D
>=0D
>=0D
>=0D
> Confidentiality Notice
>=0D
> The information contained in this electronic message and any
attachments to this message are intended
> for the exclusive use of the addressee(s) and may contain confidential
or privileged information. If
> you are not the intended recipient, please notify the sender at Wipro
or Mailadmin@wipro.com immediately
> and destroy all copies of this message and any attachments.
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>=0D
Confidentiality Notice=0D
The information contained in this electronic message and any attachments to=
this message are intended
for the exclusive use of the addressee(s) and may contain confidential or=
privileged information. If
you are not the intended recipient, please notify the sender at Wipro or=
Mailadmin@wipro.com immediately
and destroy all copies of this message and any attachments.
^ permalink raw reply
* About using ext2
From: Wouter Thielen @ 2005-03-17 12:01 UTC (permalink / raw)
To: Linuxppc-embedded
In a mail of May 2nd 2004:
> > For many classes of embedded system I don't consider unannounced power
> > failure to be 'mis-use'. That's why we run powerfail tests on JFFS2 and
>
> Neither do I. My "mis-use" only referred to the fact of using an ext2
> filesystem in a system where powerfails are expected to happen.
>
> Best regards,
>
> Wolfgang Denk
Can't that be fixed somehow in the ext2 code? Anything I should
check/know when I'm going to try and fix it myself?
--
Wouter Thielen
MuLogic B.V. Netherlands
^ permalink raw reply
* Re: FW: LED driver
From: Wolfgang Denk @ 2005-03-17 11:35 UTC (permalink / raw)
To: Hans Schillstrom; +Cc: linuxppc-embedded
In-Reply-To: <1111052805.13233.42.camel@hawk.allgon.net>
Dear Hans,
in message <1111052805.13233.42.camel@hawk.allgon.net> you wrote:
>
> I have made a driver for our mpc8270 board
> It is based upon Denx led_driver and made for 2.6 kernel
> (See atached file)
...
/******************************************************************************
*
* (C) Copyright 2004
* LGP Allgon AB
* Hans Schillstrom, hans.schillstrom@lgpallgon.com
*
* Based upon DENX status_led.c
*
* This Device driver handles LED blinks etc., Relay outputs and Alarm inputs
*
...
Will you please restore our copyright messages back into this driver
source?
It is **NEVER OK TO DELETE COPYRIGHT DECLARATIONS** like that. NEVER.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
The high cost of living hasn't affected its popularity.
^ permalink raw reply
* Re: mapping large amount of memory on physical addresses
From: Jean-Christophe Dubois @ 2005-03-17 10:58 UTC (permalink / raw)
To: scarayol; +Cc: linuxppc-embedded
In-Reply-To: <1111053440.5587.31.camel@fr-jdubois1.ad.mc.com>
On Thu, 2005-03-17 at 10:57 +0100, Jean-Christophe Dubois wrote:
> Hello Sophie,
>=20
> If you really need the 36MB block in DV to be a physically contiguous
> memory block one possible simple solution would be to exclude both high
> memory blocks from Linux at boot time with mem=3D220M on the cmdline.
An alternate way is to integrate the bigphysarea patch (which uses
bootmem allocation) to your kernel. In this case you could reserve 36MB
of memory by providing "bigphysarea=3D37748736" on the command line. I
assume the MC memory will always be excluded from Linux main memory on
your platform.
see: http://ozlabs.org/pipermail/linuxppc64-dev/2005-March/003576.html
Note that this patch doesn't provide you with mapping capabilities from
user space so you would still have to write some kind of mapping driver
using the bigphysarea allocator if you want/need your application to get
at it.
JC
> =20
> On Thu, 2005-03-17 at 09:51 +0100, scarayol@assystembrime.com wrote:
> > Hello,
> >=20
> > Could you help me : I work on embedded Linux on a MPC885 processor
> > (PowerPC). On my embedded system, i have 2 different components of RAM.=
One
> > (name =3D DV, total size of 256 MB ) is only accessed by the processor,=
the
> > other (name =3D MC, size =3D 2MB on the top of the RAM) is also access =
by an
> > FPGA. I want to do data transferts between each others. For that, I hav=
e to
> > allocate a big structure on DV for a size of 36 MB.
> > - Could I do like that to have contiguous memory on DV ?
> > For MC, it would be more complicated : I have to map on the physical
> > adresses of MC (for example 1300 0000-13FF FFFF) in order to be sure th=
at
> > the memory will be really allocated on MC and not on DV (as there is en=
ough
> > place on DV).
> > - How can I do that ?
> > - Do I have to write a driver and use ioremap on the physical address o=
f MC
> > (with reserving the top of memory with 'mem=3D' at boot time) ? Can i u=
se
> > physical addresses with ioremap or is it only virtual addresses ?
> > I think i can reserve the memory early in boot via the bootmem allocato=
r
> > but i think it isn't with physical addresses only an amount of memory a=
nd
> > it's only forbdrivers directly linked in the kernel image and i want a
> > module.
> > - Is there another solution to do that ?
> >=20
> > Thank you really for your help.
> >=20
> > Best regards.
> >=20
> > ----------------------------------------------------------
> > Sophie CARAYOL
> >=20
> > TECHNOLOGIES & SYSTEMES
> > 50 rue du Pr=C3=A9sident Sadate
> > F - 29337 QUIMPER CEDEX
> >=20
> > T=C3=A9l: +33 2 98 10 30 06
> > mailto:scarayol@assystembrime.com
> > ----------------------------------------------------------
> >=20
> >=20
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>=20
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: Posix message queue
From: Murray Jensen @ 2005-03-17 21:53 UTC (permalink / raw)
To: Vlad L, Embedded Linux
In-Reply-To: <20050317082021.79119.qmail@web90204.mail.scd.yahoo.com>
At 07:20 PM 17/03/2005, Vlad L wrote:
>I have MPC5200 based board and looking for Posix
>Message Queue for kernel 2.4... Can you, please,
>direct me to resorce where I can load such patch or
>library.
I typed "linux posix message queues" into google and came up with these:
<http://lists.debian.org/debian-mentors/2004/07/msg00420.html>http://lists.debian.org/debian-mentors/2004/07/msg00420.html
http://www.uwsg.iu.edu/hypermail/linux/kernel/0211.3/1184.html
<http://www-users.mat.uni.torun.pl/~golbi/priv/index-en.html>http://www-users.mat.uni.torun.pl/~golbi/priv/index-en.html
http://www.geocities.com/wronski12/posix_ipc/index.html
<http://www.xenotime.net/linux/linux-posix.html>http://www.xenotime.net/linux/linux-posix.html
http://www.garret.ru/~knizhnik/sal.html
<http://lwn.net/Articles/52273/>http://lwn.net/Articles/52273/
http://lwn.net/Articles/52274/
The kernel code is for 2.6, but there are some user level implementations
that might be good enough. Cheers!
Murray...
--
Murray Jensen, CSIRO Manufacturing & Infra. Tech. Phone: +61 3 9662 7763
Locked Bag No. 9, Preston, Vic, 3072, Australia. Fax: +61 3 9662 7853
Internet: Murray.Jensen@csiro.au
To the extent permitted by law, CSIRO does not represent, warrant and/or
guarantee that the integrity of this communication has been maintained or
that the communication is free of errors, virus, interception or interference.
The information contained in this e-mail may be confidential or privileged.
Any unauthorised use or disclosure is prohibited. If you have received this
e-mail in error, please delete it immediately and notify Murray Jensen on
+61 3 9662 7763. Thank you.
^ permalink raw reply
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